MC33889 [FREESCALE]
System Basis Chip with Low Speed Fault Tolerant CAN Interface; 系统基础芯片，低速容错CAN接口
| 型号： | MC33889 |
| 厂家： | 
Freescale |
| 描述： | System Basis Chip with Low Speed Fault Tolerant CAN Interface |
| 文件： | 总60页 (文件大小：1420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33889
Rev. 11.0, 12/2006
Freescale Semiconductor
Technical Data
System Basis Chip with Low
Speed Fault Tolerant CAN
Interface
33889
An SBC device is a monolithic IC combining many functions
repeatedly found in standard microcontroller-based systems, e.g.,
protection, diagnostics, communication, power, etc. The 33889 is an
SBC having fully protected, fixed 5.0 V low drop-out regulator, with
current limit, over-temperature pre-warning and reset.
SYSTEM BASIS CHIP
An output drive with sense input is also provided to implement a
second 5.0 V regulator using an external PNP. The 33889 has Normal,
Standby, Stop and Sleep modes; an internally switched high-side
power supply output with two wake-up inputs; programmable timeout
or window watchdog, Interrupt, Reset, SPI input control, and a low-
speed fault tolerant CAN transceiver, compatible with CAN 2.0 A and
B protocols for module-to-module communications. The combination
is an economical solution for power management, high-speed
communication, and control in MCU-based systems.
DW SUFFIX
EG SUFFIX (PB-FREE)
PLASTIC PACKAGE
98ASB42345B
28-PIN SOICW
Features
• VDD1: 5.0 V low drop voltage regulator, current limitation,
overtemperature detection, monitoring and reset function with total
current capability 200 mA
• V2: tracking function of VDD1 regulator; control circuitry for external
bipolar ballast transistor for high flexibility in choice of peripheral
voltage and current supply
ORDERING INFORMATION
Temperature
Device
Package
Range (T )
A
MC33889BDW/R2
MCZ33889BEG/R2
MC33889DDW/R2
*MCZ33889DEG/R2
• Four operational modes
-40°C to 125°C
28 SOICW
• Low standby current consumption in Stop and Sleep modes
• Built-in low speed 125 kbps fault tolerant CAN physical interface.
• External high voltage wake-up input, associated with HS1 VBAT
switch
*Recommended for new designs
• 150 mA output current capability for HS1 VBAT switch allowing
drive of external switches pull-up resistors or relays
• Pb-Free Packaging Designated by Suffix Code EG
V
PWR
33889
VDD1
GND
VSUP
5.0 V
V
2
V2CTRL
V2
RST
INT
MCU
HS1
Local Module Supply
Wake-Up Inputs
Safe Circuits
CS
SCLK
MOSI
MISO
L0
L1
CS
SCLK
MOSI
MISO
SPI
WDOG
RTH
Twisted
Pair
TXD
RXD
CANH
CANL
CAN Bus
RTL
Figure 1. 33889 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as
may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations Between the 33889D and 33889B Versions (1)
Device Part Number
Parameters
Symbol
Trait
MC33889B(2)
MC33889D(2)
Differential Receiver, Recessive To Dominant Threshold
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
max
max
max
3.2 V
2.6 V
3.5 V
3.0 V
(By Definition, VDIFF = VCANH-VCANL
)
VDIFF1
2.1 V
2.5 V
Differential Receiver, Dominant To Recessive Threshold
(Bus Failures 1, 2, 5)
3.2 V
3.5 V
VDIFF2
ICANH
ICANL
2.6 V
3.0 V
2.1 V
2.5 V
CANH Output Current (VCANH = 0; TX = 0.0)
CANL Output Current (VCANL = 14 V; TX = 0.0)
50 mA
75 mA
110 mA
50 mA
90 mA
135 mA
Vsup/2 + 5V
N/A
50 mA
100 mA
130 mA
50 mA
140 mA
170 mA
Vsup/2 + 4.55V
1.5us
Detection threshold for Short circuit to Battery voltage
loop time Tx to Rx, no bus failure, ISO configuration
loop time Tx to Rx, with bus failure, ISO configuration
Vcanh
tLOOPRD
tLOOPRD-F
N/A
1.9us
loop time Tx to Rx, with bus failure and +-1.5V gnd shift,
5 node network, ISO configuration
tLOOPRD/DR-F+GS
N/A
3.6us
Minimum Dominant time for Wake up on CANL or CANH
(Tem Vbat mode)
tWAKE
T2spi
min
typ
N/A
30
8
16
max
min
N/A
30
T2SPI timing
not specified, 25us
spec applied
25us
DEVICE BEHAVIOR
CANH or CANL open wire recovery principle
Reference MC33889B: on page
33
after 4 non
consecutive pulses
after 4 consecutive
pulses
Rx behavior in TermVbat mode
Reference MC33889D: on page Rx recessive, no pulse Rx recessive, dominant
34
pulse to signal bus
traffic
Notes
1. This datasheet uses the term 33889 in the inclusive sense, referring to both the D version (33889D) and the B version (33689B).
2. The 33889D and 33889B versions are nearly identical. However, where variations in characteristic occur, these items will be separated
onto individual lines.
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
33889 Internal Block Diagram
V2CTRL
Dual Voltage Regulator
V
V
Voltage Monitor
Voltage Monitor
VSUP
HS1
V2
SUP
DD1
VDD1
Oscillator
HS1 Control
INT
Interrupt
Watchdog
Reset
Programmable
Wake-Up Inputs
WDOG
RST
L0
L1
Mode Control
TX
CS
SCLK
MOSI
MISO
GND
RX
SPI
Interface
Fault Tolerant
CAN
Transceiver
RTH
CAN H
CAN L
RTL
V
SUP
V
2
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
PIN CONNECTIONS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RX
TX
VDD1
RST
WDOG
CS
2
3
MOSI
MISO
SCLK
GND
GND
GND
GND
CANL
CANH
RTL
4
5
INT
6
GND
GND
GND
GND
V2CTRL
VSUP
HS1
7
8
9
10
11
12
13
14
L0
L1
RTH
V2
Figure 2. 33889 Pin Connections
Table 2. Pin Definitions
A functional description of each pin can be found in the Functional pin description section page 24.
Pin
Pin
Pin Name
Formal Name
Definition
CAN bus receive data output pin
Function
Output
Input
1
2
3
Receiver Data
Transmitter Data
RX
TX
CAN bus receive data input pin
5.0 V pin is a 2% low drop voltage regulator for to the microcontroller
supply.
Power
Output
Voltage Regulator One
VDD1
RST
This is the device reset output pin whose main function is to reset the
MCU.
4
5
Output
Output
Ground
Output
Reset
Interrupt
This output is asserted LOW when an enabled interrupt condition
occurs.
INT
These device ground pins are internally connected to the package lead
frame to provide a 33889-to-PCB thermal path.
6 -9,
20 - 23
GND
Ground
Output drive source for the V2 regulator connected to the external series
pass transistor.
10
11
V2CTRL
VSUP
Voltage Source 2 Control
Voltage Supply
Supply input pin.
Power
Input
Output of the internal high-side switch.
12
13 - 14
15
HS1
Output
Input
High-Side Output
Level 0 - 1 Inputs
Inputs from external switches or from logic circuitry.
L0, L1
V2
5.0 V pin is a low drop voltage regulator dedicated to the peripherals
supply.
Input
Voltage Regulator Two
Pin for connection of the bus termination resistor to CANH.
Pin for connection of the bus termination resistor to CANL.
CAN high output pin.
16
17
18
19
24
RTH
RTL
Output
Output
Output
Output
Input
RTH
RTL
CAN High
CAN Low
System Clock
CANH
CAN low output pin.
CANL
Clock input pin for the Serial Peripheral Interface (SPI).
SCLK
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
PIN CONNECTIONS
Table 2. Pin Definitions (continued)
A functional description of each pin can be found in the Functional pin description section page 24.
Pin
Function
Pin
Pin Name
Formal Name
Definition
SPI data sent to the MCU by the 33889. When CSLOW is HIGH, the pin
is in the high impedance state.
25
MISO
Output
Master In/Slave Out
SPI data received by the 33889.
26
27
MOSI
CS
Input
Input
Master Out/Slave In
Chip Select
The CSLOW input pin is used with the SPI bus to select the 33889. When
the CSLOW is asserted LOW, the 33889 is the selected device of the SPI
bus.
The WDOG output pin is asserted LOW if the software watchdog is not
correctly triggered.
28
WDOG
Output
Watchdog
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Max
Unit
ELECTRICAL RATINGS
Supply Voltage at VSUP
Continuous voltage
V
VSUP
-0.3 to 27
40
Transient voltage (Load dump)
Logic Signals
(RX, TX, MOSI, MISO, CS, SCLK, RST, WDOG, INT)
VLOG
-0.3 to VDD1 +0.3
Internally Limited
V
Output current VDD1
I
mA
HS1
Voltage
V
I
-0.2 to VSUP +0.3
Internally Limited
V
A
Output Current
L0, L1
DC Input voltage
DC Input current
VWU
IWU
-0.3 to 40
-2.0 to 2.0
+-100
V
mA
V
Transient input voltage (according to ISO7637 specification) and with
external component per Figure 3.
VTRWU
DC voltage at V2 (V2INT)
V2INT
VBUS
0 to 5.25
V
V
DC Voltage On Pins CANH, CANL
-20 to +27
Transient Voltage At Pins CANH, CANL
VCANH/VCANL
-40 to +40
V
0.0 < V2-INT < 5.5 V; VSUP = 0.0; T < 500 ms
Transient Voltage On Pins CANH, CANL
(Coupled Through 1.0 nF Capacitor)
VTR
-150 to +100
-0.3 to +27V
-0.3 to +40
V
V
V
DC Voltage On Pins RTH, RTL
VRTL, VRTH
Transient Voltage At Pins RTH, RTL
VRTH/VRTL
0.0 < V2-INT < 5.5 V; VSUP = 0.0; T < 500 ms
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Max
Unit
ESD voltage (HBM 100 pF, 1.5 k) (3)
VESDH
kV
CANL, CANH, HS1, L0, L1
RTH, RTL
±4.0
±3.0
±2.0
All other pins
ESD voltage (Machine Model) All pins, MC33889B (3) (4)
VESD-MM
±200
V
V
ESD voltage (CDM) All pins, MC33889D (4)
Pins 1,14,15, & 28
VESD-CDM
750
500
All other pins
RTH, RTL Termination Resistance
THERMAL RATINGS
RT
500 to 16000
ohms
Junction Temperature
-40 to 150
-55 to 165
-40 to 125
20
TJ
TS
°C
°C
Storage Temperature
Ambient Temperature (for info only)
Thermal resistance junction to gnd pin (5)
Notes:
TA
°C
RTHJ/P
°C/W
3. Testing done in accordance with the Human Body Model (CZAP=100 pF, RZAP=1500 ), Machine Model (CZAP=200 pF, RZAP=0 ).
4. ESD machine model (MM) is for MC33889B only. MM is now replaced by CDM (Charged Discharged model).
5. Gnd pins 6,7,8,9,20, 21, 22, 23.
Transient Pulse
1nF
Generator
(note)
LX
10 k
Gnd
Gnd
Note: Waveform in accordance to ISO7637 part1, test pulses 1, 2, 3a and 3b.
Figure 3. Transient test pulse for L0 and L1 inputs
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics .
Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Description
Symbol
Min
Typ
Max
Unit
INPUT PIN (VSUP)
Nominal DC Voltage range
VSUP
5.5
4.5
-
-
18
V
V
Extended DC Voltage range 1
Reduced functionality (6)
VSUP-EX1
5.5
Extended DC Voltage range 2 (8)
VSUP-EX2
VSUPLD
18
-
-
-
27
40
V
V
Input Voltage during Load Dump
Load dump situation
Input Voltage during jump start
Jump start situation
VSUPJS
-
-
-
27
V
Supply Current in Sleep Mode (7)
ISUP
95
130
µA
VDD1 & V2 off, VSUP ≤ 12 V, oscillator running (10)
(SLEEP1)
Supply Current in Sleep Mode (7)
ISUP
-
-
55
90
µA
µA
VDD1 & V2 off, VSUP ≤ 12 V, oscillator not running
(SLEEP2)
Supply current in sleep mode (7)
ISUP
170
270
VDD1 & V2 off, VSUP = 18 V, oscillator running (10)
(SLEEP3)
Supply Current in Stand-by Mode (7),(9)
ISUP STDBY
(
)
-
-
-
42
45
45
mA
mA
µA
Iout at VDD1 = 40 mA, CAN recessive state or disabled
Supply Current in Normal Mode (7)
ISUP(NORM)
42.5
120
Iout at VDD1 = 40 mA, CAN recessive state or disabled
Supply Current in Stop mode (7),(9)
ISUP
150
I out VDD1 < 2.0 mA, VDD1 on (11), VSUP ≤ 12 V, oscillator
(STOP1)
running (10)
Supply Current in Stop mode (7),(9)
ISUP
-
-
80
110
285
µA
µA
Iout VDD1 < 2.0 mA, VDD1 on (11) VSUP ≤ 12V, oscillator
not running (10)
(STOP2)
Supply Current in Stop mode (7),(9)
ISUP
200
Iout VDD1 < 2.0 mA, VDD1 on (11), VSUP = 18 V, oscillator
running (10)
(STOP3)
Notes
6. VDD1 > 4.0 V, reset high, if RSTTH-2 selected and IOUT VDD1 reduced, logic pin high level reduced, device is functional.
7. Current measured at VSUP pin.
8. Device is fully functional. All modes available and operating, Watchdog, HS1 turn ON turn OFF, CAN cell operating, L0 and L1 inputs
operating, SPI read write operation. Over temperature may occur.
9. Measured in worst case condition with 5.0 V at V2 pin (V2 pin tied to VDD1).
10. Oscillator running means “Forced Wake-Up” or “Cyclic Sense” or “Software Watchdog” timer activated. Software Watchdog is
available in stop mode only.
11. VDD1 is ON with 2.0 mA typical output current capability.
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued).
Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Description
Supply Fail Flag internal threshold
Supply Fail Flag hysteresis (12)
Symbol
Min
Typ
Max
Unit
VTHRESH
VDETHYST
BFEW
1.5
-
3.0
1.0
6.1
4.0
-
V
V
V
Battery fall early warning threshold
In normal & standby mode
5.8
6.4
Battery fall early warning hysteresis
In normal & standby mode (12)
BFEWH
0.1
0.2
0.3
V
V
OUTPUT PIN (VDD1) (13)
VDD1 Output Voltage
IDD1 from 2.0 to 200mA
VDD1OUT
5.5 V < VSUP < 27 V
4.5 V < VSUP < 5.5 V
4.9
4.0
5.0
-
5.1
-
Drop Voltage VSUP > VDDOUT
IDD1 = 200 mA
VDD1DROP
-
-
0.2
0.1
0.5
V
V
Drop Voltage VSUP > VDDOUT, limited output current
IDD1 = 50 mA
VDD1DP2
0.25
4.5 V < VSUP < 27 V
IDD1 Output Current
Internally limited
IDD1
200
4.75
2.0
270
5.00
3.5
350
5.25
6.0
mA
V
VDD1 Output Voltage in stop mode
Iout < 2.0 mA
VDDSTOP
IDD1 stop output current to wake-up SBC
Default value after reset. (14)
IDD1S-WU1
mA
IDD1 stop output current to wake-up SBC (14)
IDD1S-WU2
10
40
14
55
18
75
mA
IDD1 over current wake deglitcher
(with IDD1S-WU1 selected) (12)
IDD1-DGIT11
µs
IDD1 over current wake deglitcher
(with IDD1S-WU2 selected) (12)
IDD1-DGIT2
-
150
-
µs
°C
°C
°C
Thermal Shutdown
TSD
160
130
20
-
-
-
190
160
40
Normal or standby mode
Over temperature pre warning
VDDTEMP bit set
TPW
Temperature Threshold difference
TSD-TPW
Notes
12. Guaranteed by design
13. IDD1 is the total regulator output current. VDD specification with external capacitor C ≥ 22µF and ESR < 1O ohm.
14. Selectable by SPI
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued).
Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Description
Symbol
Min
Typ
Max
Unit
Reset threshold 1
VRST-TH1
4.5
4.6
4.7
V
Default value after reset. (15)
Reset threshold 2 (15)
VRST-TH2
RESET-DUR
VDD
4.1
0.85
1.0
4.2
1.0
-
4.3
2.0
-
V
ms
V
Reset duration
VDD1 range for Reset Active
Reset Delay Time
tD
5.0
-
20
µs
Measured at 50% of reset signal. (16)
Line Regulation
LR1
LR2
-
-
-
-
5.0
10
25
25
75
-
mV
mV
mV
mV
9.0 V < VSUP < 18, IDD = 10 mA
Line Regulation
5.5 V < VSUP < 27 V, IDD = 10 mA
Load Regulation
LD
25
1 mA < IIDD < 200 mA
Thermal stability
THERMS
5.0
VSUP = 13.5 V, I = 100 mA
V2 REGULATOR (V2) (17)
V2 Output Voltage
V2
I2
0.99
200
1.0
-
1.01
-
VDD1
I2 from 2.0 to 200 mA
5.5 V < VSUP < 27 V
I2 output current (for information only)
mA
Depending on the external ballast transistor
V2 CTRL sink current capability
V2LOW flag threshold
I2CTRL
V2LTH
IV2RS
10
3.75
3.8
-
-
mA
V
4.0
5.6
4.25
6.8
Internal V2 Supply Current (CAN and SBC in Normal
Mode). TX = 5.0 V, CAN in Recessive State
mA
Internal V2 Supply Current (CAN and SBC in Normal
Mode). TX = 0.0 V, No Load, CAN in Dominant State
IV2DS
4.0
5.8
80
35
7.0
120
60
mA
µA
µA
Internal V2 Supply Current (CAN in Receive Only Mode,
SBC in Normal mode). VSUP = 12 V
IV2R
Internal V2 Supply Current (CAN in Bus TermVbat mode,
SBC in normal mode), VSUP = 12 V
IV2BT
Notes
15. Selectable by SPI
16. Guaranteed by design
17. V2 TRACKING VOLTAGE REGULATOR - V2 specification with external capacitor
- option 1: C ≥ 22 µF and ESR < 10 ohm. Using a resistor of 2 kohm or less between the base and emitter of the external PNP is
recommended.
- option2: 1.0 µF < C < 22 µF and ESR < 10 ohm. In this case depending on the ballast transistor gain an additional resistor and
capacitor network between emitter and base of PNP ballast transistor might be required. Refer to Freescale application information
or contact your local technical support.
- option 3: 10uF < C < 22uF ESR > 0.2 ohms: a resistor of 2 kohm or less is required between the base and emitter of the external PNP.
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued).
Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Description
LOGIC OUTPUT PINS (MISO)
Symbol
Min
Typ
Max
Unit
Low Level Output Voltage
IOUT = 1.5 mA
VOL
VOH
IHZ
-
-
-
-
1.0
-
V
V
High Level Output Voltage
VDD1-0.9
IOUT = -250 µA
Tri-state MISO Leakage Current
0.0 V < Vmiso < VDD
-2.0
+2.0
µA
LOGIC INPUT PINS (MOSI, SCLK, CS)
High Level Input Voltage
VIH
VIL
0.7VDD1
-0.3
-
-
-
VDD1+0.3V
0.3 VDD1
-20
Low Level Input Voltage
V
Input Current on CS
-100
µA
IIH
IIL
VI = 4.0 V
VI = 1.0 V
Low Level Input Current CS
VI = 1.0 V
IIL
-100
-10
-
-
-20
10
µA
µA
MOSI, SCLK Input Current
0.0 < VIN < VDD
IIN
RESET PIN (RST)
High Level Output current
0.0 < Vout < 0.7 VDD
IOH
-350
-250
-150
µA
Low Level Output Voltage (I0 = 1.5 mA)
5.5 v < VSUP < 27 V
VOL
V
0.0
0.0
-
-
0.9
0.9
1.0 V < VDD1
Reset pull down current
IPDW
2.3
-
5.0
mA
WATCHDOG PIN (WDOG)
Low Level Output Voltage (I0 = 1.5 mA)
5.5 V < VSUP < 27 V
VOL
0.0
-
-
0.9
V
V
High Level Output Voltage (I0 = -250 µA)
INTERRUPT PIN (INT)
VOH
VDD1 -0.9
VDD1
Low Level Output Voltage (I0 = 1.5 mA)
High Level Output Voltage (I0 = -250 µA)
HIGH-SIDE OUTPUT PIN (HS1)
VOL
VOH
0.0
-
-
0.9
V
V
VDD1 -0.9
VDD1
RDSON at Tj = 25°C, and IOUT -150 mA
VSUP>9V
RDSON25
-
-
2.5
Ohms
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued).
Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Description
Symbol
Min
Typ
Max
Unit
RDSON at Tj = 125°C, and IOUT -150 mA
VSUP > 9.0 V
RDSON125
-
-
5.0
Ohms
RDSON at Tj = 125°C, and IOUT -120 mA
5.5 V < VSUP < 9.0 V
RDON125-2
-
4.0
5.5
Ohms
Output current limitation
Over temperature Shutdown
Leakage current
ILIM
OVT
ILEAK
VCL
160
155
-
-
-
-
-
500
190
10
mA
°C
µA
V
Output Clamp Voltage at IOUT = -1.0 mA (18)
no inductive load drive capability
-1.5
-0.3
INPUT PINS (L0 AND L1)
L0 Negative Switching Threshold
5.5 V < VSUP < 6.0 V
VTH0N
VTH0P
VTH1N
VTH1P
V
V
V
V
1.7
2.0
2.0
2.0
2.4
2.5
3.0
3.0
3.1
6.0 V < VSUP < 18 V
18 V < VSUP < 27 V
L0 Positive Switching Threshold
5.5 V < VSUP < 6.0 V
2.2
2.5
2.5
2.75
3.4
4.0
4.0
4.1
6.0 V < VSUP < 18 V
3.5
18 V < VSUP < 27 V
L1 Negative Switching Threshold
5.5 V < VSUP < 6.0 V
2.0
2.5
2.7
2.5
3.0
3.2
3.0
3.7
3.8
6.0 V < VSUP < 18 V
18 V < VSUP < 27 V
L1 Positive Switching Threshold
5.5 V < VSUP < 6.0 V
2.7
3.0
3.5
3.3
4.0
4.2
3.8
4.7
4.8
6.0 V < VSUP < 18V
18 V < VSUP < 27 V
Hysteresis
VHYST
0.6
-10
1.0
-
1.3
10
V
5.5 V < VSUP < 27 V
Input current
IIN
µA
-0.2 V < VIN < 40 V
CAN MODULE SPECIFICATION (TX, RX, CANH, CANL, RTH, AND RTL)
DC Voltage On Pins TX, RX
DC voltage at V2 (V2INT)
DC Voltage On Pins CANH, CANL
Notes
VLOGIC
V2INT
VBUS
-0.3
0.0
-20
VDD1 + 0.3
5.25
V
V
V
+27
18. Refer to HS1 negative maximum rating voltage limitation of -0.2V.
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued).
Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Description
Symbol
Min
Typ
Max
Unit
Transient Voltage At Pins CANH, CANL
VCANH/VCANL
-40
40
V
0.0 < V2-INT < 5.5 V; VSUP ≥ 0.0; T < 500 ms
Transient Voltage On Pins CANH, CANL (Coupled Through
1.0 nF Capacitor)
VTR
-150
100
V
V
V
Detection Threshold For Short-circuit To Battery Voltage
(Term VBAT Mode) MC33889B
VCANH
VSUP/2+3
VSUP/2+3
VSUP/2+5
Detection Threshold For Short-circuit To Battery Voltage
(Term VBAT Mode) MC33889D
VCANH
VSUP/
2+4.55
DC Voltage On Pins RTH, RTL
VRTL, VRTH
VRTH/VRTL
-0.3
-0.3
+27
V
V
Transient Voltage At Pins RTH, RTL
40
0.0 < V2-INT < 5.5 V; VSUP ≥ 0.0; T < 500 ms
TRANSMITTER DATA PIN (TX)
High Level Input Voltage
VIH
VIL
0.7*V2
-0.3
V2+0.3V
0.3 * V2
-25
V
V
Low Level Input Voltage
TX High Level Input Current (VI = 4.0 V)
TX Low Level Input Current (VI = 1.0 V)
RECEIVE DATA PIN (RX)
ITXH
ITXL
-100
-100
-50
-50
µA
µA
-25
High Level Output Voltage RX (I0 = -250 µA)
Low Level Output Voltage (I0 = 1.5 mA)
CAN HIGH AND CAN LOW PINS (CANH, CANL)
Differential Receiver, Recessive To Dominant Threshold
VOH
VOL
V2-INT - 0.9
0.0
V2-INT
0.9
V
V
VDIFF1
V
V
(By Definition, VDIFF = VCANH-VCANL
For 33889D
)
-3.5
-3.2
-3.0
-2.6
-2.5
-2.1
For 33889B
Differential Receiver, Dominant To Recessive Threshold
(Bus Failures 1, 2, 5)
VDIFF2
For 33889D
For 33889B
-3.5
-3.2
-3.0
-2.6
-2.5
-2.1
CANH Recessive Output Voltage
TX = 5.0 V; R(RTH) < 4.0 k
VCANH
0.2
V
V
CANL Recessive Output Voltage
TX = 5.0 V; R(RTL) < 4.0 k
VCANL
V2-INT - 0.2
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued).
Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Description
Symbol
Min
Typ
Max
Unit
CANH Output Voltage, Dominant
VCANH
V2 - 1.4
V
TX = 0.0 V; ICANH = -40 mA; Normal Operating Mode (19)
CANL Output Voltage, Dominant
VCANL
1.4
V
TX = 0.0 V; ICANL = 40 mA; Normal Operating Mode (19)
CANH Output Current (VCANH = 0; TX = 0.0)
ICANH
mA
For 33889D
For 33889B
50
50
100
75
130
110
CANL Output Current (VCANL = 14 V; TX = 0.0)
ICANL
mA
For 33889D
For 33889B
50
50
140
90
170
135
Detection Threshold For Short-circuit To Battery Voltage
(Normal Mode)
VCANH, VCANL
7.3
7.9
8.9
V
V
Detection Threshold For Short-circuit To Battery Voltage
(Term VBAT Mode), MC33889B
VcanH
Vsup/2+3
Vsup/2+3
Vsup/2+5
Vsup/
2+4.55
Detection Threshold For Short-circuit To Battery Voltage
(Term VBAT Mode), MC33889D
VcanH
ICANH
V
CANH Output Current (Term VBAT Mode; VCANH = 12 V,
Failure3)
5.0
0.0
10
µA
CANL Output Current (Term VBAT Mode; VCANL = 0.0 V;
VBAT = 12 V, Failure 4)
ICANL
2.0
µA
CANL Wake-Up Voltage Threshold
CANH Wake-Up Voltage Threshold
Wake-Up Threshold Difference (Hysteresis)
VWAKE,L
VWAKE,H
VWAKEL
2.5
1.2
0.2
3.0
2.0
3.9
2.7
V
V
V
-
VWAKEH
VSE, CANH
VSE, CANL
ICANL,PU
ICANH,PD
RDIFF
CANH Single Ended Receiver Threshold (Failures 4, 6, 7)
CANL Single Ended Receiver Threshold (Failures 3, 8)
CANL Pull Up Current (Normal Mode)
1.5
2.8
45
1.85
3.05
75
2.15
3.4
90
V
V
µA
µA
kohm
V
CANH Pull Down Current (Normal Mode)
Receiver Differential Input Impedance CANH / CANL
Differential Receiver Common Mode Voltage Range (20)
CANH To Ground Capacitance
45
75
90
100
-10
300
10
VCOM
CCANH
50
pF
pF
pF
°C
CANL To Ground Capacitance
CCANL
50
CCANL to CCANH Capacitor Difference
DCCAN
tCSD
10
CAN Driver Thermal Shutdown
150
160
Notes
19. For MC33889B, after 128 pulses on TX and no bus failure.
20. Guaranteed by design
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued).
Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Description
Symbol
Min
Typ
Max
Unit
BUS TERMINATION PINS (RTH, RTL)
RTL to V2 Switch On Resistance
RRTL
10
30
90
ohms
(IOUT < -10 mA; Normal Operating Mode)
RTL to BAT Switch Series Resistance (term VBAT Mode)
RRTL
RRTH
8.0
10
12.5
30
20
90
kohm
ohm
RTH To Ground Switch On Resistance (IOUT < 10 mA;
Normal Operating Mode)
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
VSUP From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40°C to 150°C unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Conditions
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE TIMING (SCLK, CS, MOSI, MISO)
SPI operation frequency
FREQ
tPCLK
-
-
-
4.0
MHz
ns
SCLK Clock Period
250
125
125
100
-
-
-
-
SCLK Clock High Time
tWSCLKH
tWSCLKL
tlLEAD
-
ns
SCLK Clock Low Time
-
ns
Falling Edge of CS to Rising
Edge of SCLK
50
ns
Falling Edge of SCLK to Rising Edge of CS
MOSI to Falling Edge of SCLK
Falling Edge of SCLK to MOSI
MISO Rise Time (CL = 220 pF)
MISO Fall Time (CL = 220 pF)
tLAG
tSISU
tSIH
100
40
40
-
50
25
25
25
25
-
-
-
ns
ns
ns
ns
ns
ns
-
tRSO
tfSO
50
50
-
Time from Falling or Rising Edges of CS to:
- MISO Low Impedance
-
tSOEN
tSODIS
50
50
- MISO High Impedance
Time from Rising Edge of SCLK to MISO Data Valid
tVALID
-
-
-
50
34
ns
0.2 V1 ≤ SO ≥ 0.8 V1, CL = 200 pF
Delay between CS low to high transition (at end of SPI stop
command) and Stop or sleep mode activation (21)
TCS-STOP
18
µs
detected by V2 off
Interrupt low level duration
SBC in stop mode
TINT
7.0
-
10
13
-
µs
Internal oscillator frequency
OSC-F1
100
kHz
All modes except Sleep and Stop (21)
Notes
21. Guaranteed by design
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
VSUP From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40°C to 150°C unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Conditions
Symbol
Min
Typ
Max
Unit
Internal low power oscillator frequency
Sleep and Stop modes (22)
OSC-F2
-
100
-
kHz
Watchdog period 1
WD1
8.58
39.6
88
9.75
45
10.92
50.4
112
392
12
ms
ms
ms
ms
%
Normal and standby modes
Watchdog period 2
WD2
Normal and standby modes
Watchdog period 3
WD3
100
350
-
Normal and standby modes
Watchdog period 4
WD4
308
-12
Normal and standby modes
Watchdog period accuracy
Normal and standby modes
F1ACC
Normal request mode timeout
Normal request mode
NRTOUT
WD1STOP
WD2STOP
WD3STOP
WD4STOP
F2ACC
308
6.82
31.5
70
350
9.75
45
392
12.7
58.5
130
455
30
ms
ms
ms
ms
ms
%
Watchdog period 1 - stop
Stop mode
Watchdog period 2- stop
Stop mode
Watchdog period 3 - stop
Stop mode
100
350
-
Watchdog period 4 - stop
Stop mode
245
-30
Stop mode watchdog period accuracy
Stop mode
Cyclic sense/FWU timing 1
Sleep and stop modes
CSFWU1
CSFWU2
3.22
6.47
4.6
9.25
5.98
12
ms
ms
Cyclic sense/FWU timing 2
Sleep and stop modes
Notes
22. Guaranteed by design
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
VSUP From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40°C to 150°C unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Conditions
Symbol
Min
Typ
Max
Unit
Cyclic sense/FWU timing 3
CSFWU3
12.9
18.5
24
ms
Sleep and stop modes
Cyclic sense/FWU timing 4
Sleep and stop modes
CSFWU4
CSFWU5
CSFWU6
CSFWU7
CSFWU8
tON
25.9
51.8
66.8
134
271
200
-30
-
37
74
48.1
96.2
124
248
504
400
+30
22
ms
ms
ms
ms
ms
µs
Cyclic sense/FWU timing 5
Sleep and stop modes
Cyclic sense/FWU timing 6
Sleep and stop modes
95.5
191
388
300
-
Cyclic sense/FWU timing 7
Sleep and stop modes
Cyclic sense/FWU timing 8
Sleep and stop modes
Cyclic sense On time
in sleep and stop modes
Cyclic sense/FWU timing accuracy
in sleep and stop mode
tACC
%
Delay between SPI command and HS1 turn on (23)
Normal or standby mode, VSUP > 9.0 V
tS-HSON
-
µs
Delay between SPI command and HS1 turn off (23)
Normal or standby mode, VSUP > 9.0 V
tS-HSOFF
-
-
22
µs
Delay between SPI and V2 turn on (23)
Standby mode
tS-V2ON
tS-V2OFF
tS-NR2N
9.0
9.0
15
-
-
25
25
70
µs
µs
µs
Delay between SPI and V2 turn off (23)
Normal modes
Delay between Normal Request and Normal mode, after
W/D trigger command
35
Normal request mode
Notes
23. State Machine Timing - Delay starts at rising edge of CS (end of SPI command) and start of Turn on or Turn off of HS1 or V2.
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
VSUP From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40°C to 150°C unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Conditions
Symbol
Min
Typ
Max
Unit
Delay between SPI and “CAN normal mode”
SBC Normal mode (24)
tS-CANN
-
-
10
µs
Delay between SPI and “CAN sleep mode”
SBC Normal mode (24)
tS-CANS
-
-
10
90
µs
µs
Delay between CS wake-up (CS low to high) and SBC
normal request mode (VDD1 on & reset high)
tW-CS
15
40
SBC in stop mode
Delay between CS wake-up (CS low to high) and first
accepted SPI command
tW-SPI
90
20
-
-
-
-
µs
SBC in stop mode
Delay between INT pulse and 1st SPI command accepted
In stop mode after wake-up
tS-1STSPI
µs
µs
Delay between two SPI messages addressing the same
register
t2SPI
For 33889D only
25
-
-
INPUT PINS (L0 AND L1)
Wake-up Filter Time (enable/disable option on L0 input)
(If filter enabled)
tWUF
8.0
20
38
µs
PIN AC CHARACTERISTICS (CANH, CANL, RX, TX)
CANL and CANH Slew Rates (25% to 75% CAN signal). (25)
Recessive to Dominant state
tSLDR
V/µs
2.0
2.0
8.0
9.0
Dominant to Recessive state
Propagation Delay
tONRX
µs
µs
TX to RX Low. -40°C < T ≤ 25°C. (26)
TX to RX Low. 25°C < T < 125°C. (26)
1.2
1.1
1.6
1.8
Propagation Delay TX to RX High. (26)
tOFFRX
1.8
2.2
Notes
24. Guaranteed by design
25. Dominant to recessive slew rate is dependant upon the bus load characteristics.
26. AC Characteristics measured according to schematic Figure 4
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
VSUP From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40°C to 150°C unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Conditions
Symbol
Min
Typ
Max
Unit
Loop time Tx to Rx, no bus failure, MC33889D only ((27),
Figure 5) (ISO ICT test series 10)
tLOOPRD
µs
Tx high to low transition (dominant edge)
Tx low to high transition (recessive edge)
1.15
1.45
1.5
1.5
Loop time Tx to Rx, with bus failure, MC33889D only ((27),
Figure 6) (ISO ICT test series 10)
tLOOPRD-F
µs
Tx high to low transition (dominant edge)
Tx low to high transition (recessive edge)
-
-
1.9
1.9
Loop time Tx to Rx, with bus failure and +-1.5V gnd shift, 5
nodes network, MC33889D,((28), Figure 7, ISO ICT tests
series 11)
tLOOPRD/DR-F+GS
3.6
µs
µs
Min. Dominant Time For Wake-up On CANL or CANH
(Term Vbat; VSUP = 12V) Guaranteed by design.
MC33889B
tWAKE
30
16
MC33889D
8.0
10
30
80
Failure 3 Detection Time (Normal Mode)
tDF3
tDR3
tDF6
30
160
200
200
1.5
µs
µs
Failure 3 Recovery Time (Normal Mode)
Failure 6 Detection Time (Normal Mode)
50
150
0.75
10
500
1000
4.0
µs
Failure 6 Recovery Time (Normal Mode)
tDR6
tDF47
tDR47
tDF8
µs
Failure 4, 7 Detection Time (Normal Mode)
Failure 4, 7 Recovery Time (Normal Mode)
Failure 3a, 8 Detection Time (Normal Mode)
Failure 3a, 8 Recovery Time (Normal Mode)
Failure 4, 7 Detection Time, (Term VBAT; VSUP = 12 V)
Failure 4, 7 Recovery Time (Term VBAT; VSUP = 12 V)
Failure 3 Detection Time (Term VBAT; VSUP = 12 V)
Failure 3 Recovery Time (Term VBAT; VSUP = 12 V)
Failure 3a, 8Detection Time (Term VBAT; VSUP = 12 V)
Failure 3a, 8 Recovery Time (Term VBAT; VSUP = 12 V)
ms
µs
30
60
0.75
0.75
0.8
1.7
4.0
ms
ms
ms
ms
ms
ms
ms
ms
tTDR8
tDR47
tDR47
tDR3
tDR3
tDR8
tDR8
1.5
4.0
1.2
8.0
1.92
3.84
1.92
2.3
1.2
Notes
27. AC characteristic according to ISO11898-3, tested per figure 5 and 6. Guaranteed by design, room temperature only.
28. AC characteristic according to ISO11898-3, tested per figure 7. Max reported is the typical measurement under the worst condition
(gnd shift, dominant/recessive edge, at source or destination node. ref to ISO test specification). Guaranteed by design, room
temperature only.
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
VSUP From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40°C to 150°C unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Conditions
Symbol
Min
Typ
Max
Unit
Edge Count Difference Between CANH and CANL for Failures
1, 2, 5 Detection (Failure bit set, Normal Mode)
ECDF
3
Edge Count Difference Between CANH And CANL For
Failures 1, 2, 5 Recovery (Normal Mode)
ECDR
tTX,D
tTX,E
3
TX Permanent Dominant Timer Disable Time
(Normal Mode And Failure Mode)
0.75
10
4.0
60
ms
TX Permanent Dominant Timer Enable Time
(Normal Mode And Failure Mode)
µs
5V
RcanL
VDD
RtL
500
500
1nF
R
C
C
Tx
CANL
CANL
CANH
MC33889D
R = 100ohms
C = 1nF
C
CANH
Rx
RcanH
1nF
RtH
R
RcanL = RcanH = 125 ohms
Figure 5. ISO loop time without bus failure
Figure 4. Test Circuit for AC Characteristics
Vbat
RtL
500
500
RcanL
RcanH
1nF
1nF
Tx
CANL
Bus
MC33889D
Failure
Generator (*)
CANH
Rx
RtH
RcanL = RcanH = 125 ohms
except for failure CANH short to CANL
(Rcanl = 1M ohms)
(*) List of failure
CANL short to gnd, Vdd, Vbat
CANHshort to gnd, Vdd, Vbat
CANL short to CANH
CANL and CANH open
Figure 6. ISO Loop Time with Bus Failure
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Figure 7. Test Set Up for Propagation Delay with GND Shift in a 5 Node Configuration
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
TX HIgh: RECESSIVE Bit
TX High: RECESSIVE Bit
VTX
TX Low: DOMINANT Bit
5.0V
3.6V
CANL
1.4V
0.0V
CANH
2.2V
V
TH(DR)
VDIFF
VRX
VTH(RD)
tOFFTX
-5.0V
0.7VCC
0.3VCC
tONRX
tOFFRX
t
RECESSIVE Bit
DOMINANT Bit
RECESSIVE Bit
Figure 8. Device Signal Waveforms
TPCLK
CS
TWCLKH
TLEAD
TLAG
SCLK
TWCLKL
TSIH
TSISU
MOSI
MISO
Undefined
D0
Don’t Care
D7
Don’t Care
TVALID
TSOEN
TSODIS
D0
D7
Don’t Care
Figure 9. Timing Characteristic
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The MC33889 is an integrated circuit dedicated to
automotive applications. It includes the following functions:
• Reset, programmable watchdog function
• Four operational modes
• Wake-up capabilities: Forced wake-up, cyclic sense and
wake-up inputs, CAN and the SPI
• One full protected voltage regulator with 200 mA total
output current capability.
• Can low speed fault tolerant physical interface.
• Driver for external path transistor for V2 regulator function.
FUNCTIONAL PIN DESCRIPTION
RECEIVE AND TRANSMIT DATA (RX AND TX)
VOLTAGE SUPPLY (VSUP)
The RX and TX pins (receive data and transmit data pins,
respectively) are connected to a microcontroller’s CAN
protocol handler. TX is an input and controls the CANH and
CANL line state (dominant when TX is LOW, recessive when
TX is HIGH). RX is an output and reports the bus state (RX
LOW when CAN bus is dominant, HIGH when CAN bus is
recessive).
The VSUP pin is the battery supply input of the device.
HIGH-SIDE OUTPUT 1 (HS1)
The HS pin is the internal high-side driver output. It is
internally protected against overcurrent and
overtemperature.
LEVEL 0-1 INPUTS (L0: L1)
VOLTAGE REGULATOR ONE (VDD1)
The L0: L1 pins can be connected to contact switches or
the output of other ICs for external inputs. The input states
can be read by the SPI. These inputs can be used as wake-
up events for the SBC when operating in the Sleep or Stop
mode.
The VDD1 pin is the output pin of the 5.0 V internal
regulator. It can deliver up to 200 mA. This output is protected
against overcurrent and overtemperature. It includes an
overtemperature pre-warning flag, which is set when the
internal regulator temperature exceeds 130°C typical. When
the temperature exceeds the overtemperature shutdown
(170°C typical), the regulator is turned off. VDD1 includes an
undervoltage reset circuitry, which sets the RST pin LOW
when VDD is below the undervoltage reset threshold.
VOLTAGE REGULATOR TWO (V2)
The V2 pin is the input sense for the V2 regulator. It is
connected to the external series pass transistor. V2 is also
the 5.0 V supply of the internal CAN interface. It is possible to
connect V2 to an external 5.0 V regulator or to the VDD
output when no external series pass transistor is used. In this
case, the V2CTRL pin must be left open.
RESET (RST)
The Reset pin RST is an output that is set LOW when the
device is in reset mode. The RST pin is set HIGH when the
device is not in reset mode. RST includes an internal pullup
current source. When RST is LOW, the sink current capability
is limited, allowing RST to be shorted to 5.0 V for software
debug or software download purposes.
RTH (RTH)
Pin for the connection of the bus termination resistor to
CANH
RTL (RTL)
INTERRUPT (INT)
Pin for the connection of the bus termination resistor to
CANL
The Interrupt pin INT is an output that is set LOW when an
interrupt occurs. INT is enabled using the Interrupt Register
(INTR). When an interrupt occurs, INT stays LOW until the
interrupt source is cleared. INT output also reports a wake-up
event by a 10 sec. typical pulse when the device is in Stop
mode.
CAN HIGH AND CAN LOW OUTPUTS
(CANH AND CANL)
The CAN High and CAN Low pins are the interfaces to the
CAN bus lines. They are controlled by TXD input level, and
the state of CANH and CANL is reported through RXD output.
GROUND (GND)
This pin is the ground of the integrated circuit.
SYSTEM CLOCK (SCLK)
V2CTRL (V2CTRL)
SCLK is the Serial Data Clock input pin of the serial
peripheral interface.
The V2CTRL pin is the output drive pin for the V2 regulator
connected to the external series pass transistor.
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MASTER IN/SLAVE OUT (MISO
CHIP SELECT (CS)
MISO is the Master In Slave Out pin of the serial peripheral
interface. Data is sent from the SBC to the microcontroller
through the MISO pin.
CS is the Chip Select pin of the serial peripheral interface.
When this pin is LOW, the SPI port of the device is selected.
WATCH DOG (WDOG)
MASTER OUT/SLAVE IN (MOSI)
The Watchdog output pin is asserted LOW to flag that the
software watchdog has not been properly triggered.
MOSI is the Master Out Slave In pin of the serial peripheral
interface. Control data from a microcontroller is received
through this pin.
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
DEVICE SUPPLY
HS1 VBAT SWITCH OUTPUT
The device is supplied from the battery line through the
VSUP pin. An external diode is required to protect against
negative transients and reverse battery. It can operate from
4.5 V and under the jump start condition at 27 V DC. This pin
sustains standard automotive voltage conditions such as
load dump at 40 V. When VSUP falls below 3.0 V typical, the
MC33889 detects it and stores the information in the SPI
register, in a bit called “BATFAIL”. This detection is available
in all operation modes.
HS1 output is a 2.0 ohm typical switch from the VSUP pin.
It allows the supply of external switches and their associated
pullup or pull-down circuitry, for example, in conjunction with
the wake-up input pins. Output current is limited to 200 mA
and HS1 is protected against short-circuit and has an over
temperature shutdown (reported into the IOR register). The
HS1 output is controlled from the internal register and the
SPI. It can be activated at regular intervals in sleep mode
thanks to an internal timer. It can also be permanently turned
on in normal or stand-by modes to drive external loads, such
as relays or supply peripheral components. In case of
inductive load drive, external clamp circuitry must be added.
VDD1 VOLTAGE REGULATOR
VDD1 Regulator is a 5.0 V output voltage with total current
capability of 200 mA. It includes a voltage monitoring circuitry
associated with a reset function. The VDD1 regulator is fully
protected against overcurrent, short-circuit and has
overtemperature detection warning flags and shutdown with
hysteresis.
SPI
The complete device control as well as the status report is
done through an 8 bit SPI interface. Refer to the SPI
paragraph.
V2 REGULATOR
CAN
V2 Regulator circuitry is designed to drive an external path
transistor in order to increase output current flexibility. Two
pins are used: V2 and V2CTRL. Output voltage is 5.0 V and
is realized by a tracking function of the VDD1 regulator. A
recommended ballast transistor is the MJD32C. Other
transistors might be used, however depending upon the PNP
gain, an external resistor capacitor network might be
connected between the emitter and base of the PNP. The use
of external ballast is optional (refer to simplified typical
application). The state of V2 is reported into the IOR register
(if V2 is below 4.5 V typical, or in cases of overload or short-
circuit).
The device incorporates a low speed fault tolerant CAN
physical interface. The speed rate is up to 125 kBauds.
The state of the CAN interface is programmable through
the SPI. Reference the CAN transceiver description on page
30.
PACKAGE AND THERMAL CONSIDERATION
The device is proposed in a standard surface mount SO28
package. In order to improve the thermal performances of the
SO28 package, 8 pins are internally connected to the lead
frame and are used for heat transfer to the printed circuit
board.
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
INTRODUCTION
to stop” instruction must be the last instruction executed by
the MCU before going to low power mode.
The device has four modes of operation, normal, stand-by,
sleep and stop modes. All modes are controlled by the SPI.
An additional temporary mode called “normal request mode”
is automatically accessed by the device (refer to state
machine) after wake-up events. Special mode and
configurations are possible for software application debug
and flash memory programming.
In Stop mode, the Software watchdog can be “running” or
“not running” depending on the selection by the SPI. Refer to
the SPI description, RCR register bit WDSTOP. If the W/D is
enabled, the SBC must wake-up before the W/D time has
expired, otherwise a reset is generated. In stop mode, the
SBC wake-up capability is identical as in sleep mode.
STOP MODE: WAKE-UP FROM SBC SIDE, INT PIN
ACTIVATION
NORMAL MODE
In this mode both regulators are ON, and this corresponds
to the normal application operation. All functions are
available in this mode (watchdog, wake-up input reading
through the SPI, HS1 activation, and CAN communication).
The software watchdog is running and must be periodically
cleared through the SPI.
When an application is in stop mode, it can wake-up from
the SBC side. When a wake-up is detected by the SBC (CAN,
Wake-up input, forced wake-up, etc.), the SBC turns itself
into Normal request mode and activates the VDD1 main
regulator. When the main regulator is fully active, then the
wake-up is signalled to the MCU through the INT pin. The INT
pin is pulled low for 10 µs and then returns high. Wake-up
events can be read through the SPI registers.
STANDBY MODE
Only the Regulator 1 is ON. Regulator 2 is turned OFF by
disabling the V2CTRL pin. The CAN cell is not available, as
powered from V2. Other functions are available: wake-up
input reading through the SPI and HS1 activation. The
watchdog is running.
STOP MODE: WAKE-UP FROM MCU SIDE
When the application is in stop mode, the wake-up event
may come to the MCU. In this case, the MCU has to signal to
the SBC that it has to go into Normal mode in order for the
VDD1 regulator to be able to deliver full current capability.
This is done by a low to high transition of the CS pin. The CS
pin low to high activation has to be done as soon as possible
after the MCU. The SBC generates a pulse at the INT pin.
Alternatively the L0 and L1 inputs can also be used as wake-
up from the Stop mode.
SLEEP MODE
Regulators 1 and 2 are OFF. In this mode, the MCU is not
powered. The device can be awakened internally by cyclic
sense via the wake-up input pins and HS1 output, from the
forced wake function, the CAN physical interface, and the SPI
(CS pin).
STOP MODE CURRENT MONITORING
STOP MODE
If the current in Stop mode exceeds the IDD1S-WU
threshold, the SBC jumps into Normal request mode,
activates the VDD1 main regulator, and generates an
interrupt to the MCU. This interrupt is not maskable and a not
bit are set into the INT register.
Regulator 2 is turned OFF by disabling the V2CTRL pin.
Regulator 1 is activated in a special low power mode which
allows it to deliver 2.0 mA. The objective is to supply the MCU
of the application while it is turned into a power saving
condition (i.e stop or wait mode).
Stop mode is entered through the SPI. Stop mode is
dedicated to powering the Microcontroller when it is in low
power mode (stop, pseudo stop, wait etc.). In these modes,
the MCU supply current is less than 1.0 mA. The MCU can
restart its software application very quickly without the
complete power up and reset sequence.
SOFTWARE WATCHDOG IN STOP MODE
If the watchdog is enabled (register MCR, bit WDSTOP
set), the MCU has to wake-up independently of the SBC
before the end of the SBC watchdog time. In order to do this,
the MCU has to signal the wake-up to the SBC through the
SPI wake-up (CS pin low to high transition to activated the
SPI wake-up). Then the SBC wakes up and jumps into the
normal request mode. The MCU has to configure the SBC to
go to either into normal or standby mode. The MCU can then
choose to go back into stop mode.
When the application is in stop mode (both MCU and
SBC), the application can wake-up from the SBC side (ex
cyclic sense, forced wake-up, CAN message, wake-up
inputs) or the MCU side (key wake-up etc.).
When Stop mode is selected by the SPI, stop mode
becomes active 20 µs after end of the SPI message. The “go
If no MCU wake-up occurs within the watchdog timing, the
SBC will activate the reset pin and jump into the normal
request mode. The MCU can then be initialized.
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
NORMAL REQUEST MODE
WAKE-UP CAPABILITIES
This is a temporary mode automatically accessed by the
device after a wake-up event from sleep or stop mode, or
after device power up. In this mode, the VDD1 regulator is
ON, V2 is off, and the reset pin is high. As soon as the device
enters the normal request mode, an internal 350 ms timer is
started. During these 350 ms, the microcontroller of the
application must address the SBC via the SPI and configure
the watchdog register (TIM1 register). This is the condition for
the SBC to leave the Normal request Mode and enter the
Normal mode, and to set the watchdog timer according to the
configuration done during the Normal Request mode.
Several wake-up capabilities are available for the device
when it is in sleep or stop mode. When a wake-up has
occurred, the wake-up event is stored into the WUR or CAN
registers. The MCU can then access the wake-up source.
The wake-up options are selectable through the SPI while the
device is in normal or standby mode, and prior to entering low
power mode (sleep or stop mode).
WAKE-UP FROM WAKE-UP INPUTS (L0, L1) WITHOUT
CYCLIC SENSE
The wake-up lines are dedicated to sense external switch
states, and when changes occur to wake-up the MCU (In
sleep or stop modes). The wake-up pins are able to handle
40 V DC. The internal threshold is 3.0 V typical, and these
inputs can be used as an input port expander. The wake-up
inputs state can be read through the SPI (register WUR). L0
has a lower threshold than L1 in order to allow a connection
and wake-up from a digital output such as a CAN physical
interface.
The “BATFAIL flag” is a bit which is triggered when VSUP
falls below 3.0 V. This bit is set into the MCR register. It is
reset by the MCR register read.
INTERNAL CLOCK
This device has an internal clock used to generate all
timings (reset, watchdog, cyclic wake-up, filtering time
etc....).
CYCLIC SENSE WAKE-UP (CYCLIC SENSE TIMER AND
WAKE-UP INPUTS L0, L1)
RESET PIN
A reset output is available in order to reset the
microcontroller. Reset causes are:
The SBC can wake-up from a state change of one of the
wake-up input lines (L0, L1), while the external pullup or
pulldown resistor of the switches associated to the wake-up
input lines are biased with HS1 VSUP switch. The HS1 switch
is activated in sleep or stop mode from an internal timer.
Cyclic sense and forced wake-up are exclusive. If Cyclic
sense is enabled, the forced wake-up can not be enabled.
• VDD1 falling out of range: if VDD1 falls below the reset
threshold (parameter RST-TH), the reset pin is pulled low
until VDD1 returns to the nominal voltage.
• Power on reset: at device power on or at device wake-up
from sleep mode, the reset is maintained low until VDD1 is
within its operation range.
• Watchdog timeout: if the watchdog is not cleared, the SBC
will pull the reset pin low for the duration of the reset
duration time (parameter: RESET-DUR).
INFO FOR CYCLIC SENSE + DUAL EDGE SELECTION
In case the Cyclic sense and Lx both level sensitive
conditions are use together, the initial value for Lx inputs are
sampled in two cases:
For debug purposes at 25°C, the reset pin can be shorted
to 5.0 V.
1) When the register LPC[D3 and D0] are set and
2) At cyclic sense event, that is when device is in sleep or
stop mode and HS1 is active.
SOFTWARE WATCHDOG (SELECTABLE WINDOW OR
TIMEOUT WATCHDOG)
The consequence is that when the device wake up by Lx
transition, the new value is sampled as default, then when the
device is set back into low power again, it will automatically
wake up.
The software watchdog is used in the SBC normal and
stand-by modes for monitoring the MCU. The watchdog can
be either a window or timeout. This is selectable by the SPI
(register TIM, bit WDW). Default is the window watchdog.
The period of the watchdog is selectable by the SPI from 5.0
to 350 ms (register TIM, bits WDT0 and WDT1). When the
window watchdog is selected, the closed window is the first
half of the selected period, and the open window is the
second half of the period. The watchdog can only be cleared
within the open window time. An attempt to clear the
watchdog in the closed window will generate a reset. The
Watchdog is cleared through the SPI by addressing the TIM
register.
The user should reset the LPC bits [D3 and D0] to 0 and
set them again to the desired value prior to enter sleep or
stop mode.
FORCED WAKE-UP
The SBC can wake-up automatically after
a
predetermined time spent in sleep or stop mode. Forced
wake-up is enabled by setting bit FWU in the LPC register.
Cyclic sense and forced wake-up are exclusive. If forced
wake-up is enabled, the Cyclic sense can not be enabled.
Refer to ”table for reset pin operations” operation in mode
2.
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
CAN WAKE-UP
BATTERY FALL EARLY WARNING
The device can wake-up from a CAN message. A CAN
wake-up cannot be disabled.
This function provides an interrupt when the VSUP
voltage is below the 6.1 V typical. This interrupt is maskable.
A hysteresis is included. Operation is only in Normal and
Stand-by modes. VBAT low state reports in the IOR register.
SPI WAKE-UP
The device can wake-up by the CS pin in sleep or stop
mode. Wake-up is detected by the CS pin transition from a
low to high level. In stop mode this correspond to the
condition where the MCU and SBC are both in Stop mode,
and when the application wake-up events come through the
MCU.
RESET AND WDOG OPERATION
The following figure shows the reset and watchdog output
operations. Reset is active at device power up and wake-up.
Reset is activated in case the VDD1 falls or the watchdog is
not triggered. The WDOG output is active low as soon as the
reset goes low and stays low for as long as the watchdog is
not properly re-activated by the SPI.
SYSTEM POWER UP
The WDOG output pin is a push pull structure than can
drive external components of the application, for instance to
signal the MCU is in a wrong operation. Even if it is internally
turned on (low-state), the reset pin can be forced to 5.0 V at
25°C only, thanks to its internally limited current drive
capability. The WDOG stays low until the Watchdog register
is properly addressed through the SPI.
At power up the device automatically wakes up.
DEVICE POWER UP, SBC WAKE UP
After device or system power up or a wake-up from sleep
mode, the SBC enters into “reset mode” then into “normal
request mode”.
Watchdog timeout
VDD1
RESET
Watchdog
period
WDOG
SPI
W/D clear
SPI CS
Watchdog register addressed
Figure 10. Reset and WDOG Function Diagram
DEBUG MODE APPLICATION HARDWARE AND
SOFTWARE DEBUG WITH THE SBC.
DEBUG MODES WITH SOFTWARE WATCHDOG
DISABLED THOUGH SPI (NORMAL DEBUG, STANDBY
DEBUG AND STOP DEBUG)
When the SBC is mounted on the same printed circuit
board as the micro controller, it supplies both application
software and the SBC with a dedicated routine that must be
debugged. The following features allow the user to debug the
software by disabling the SBC internal software watchdog
timer.
The software watchdog can be disabled through the SPI.
In order to avoid unwanted watchdog disables, and to limit the
risk of disabling the watchdog during an SBC normal
operation, the watchdog disable has to be performed with the
following sequence:
Step 1) Power down the SBC
DEVICE POWER UP, RESET PIN CONNECTED TO VDD1
Step 2) Power up the SBC (The BATFAIL bit is set, and the
SBC enters normal request mode)
Step 3) Write to the TIM1 register to allow the SBC to enter
Normal mode
Step 4) Write to the MCR register with data 0000 (this
enables the debug mode). (Complete SPI byte: 000 1 0000)
At SBC power up, the VDD1 voltage is provided, but if no
SPI communication occurs to configure the device, a reset
occurs every 350 ms. In order to allow software debugging
and avoid an MCU reset, the Reset pin can be connected
directly to VDD1 by a jumper.
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
28
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Step 5) Write to the MCR register normal debug (0001
x101), stand-by debug (0001 x110), or Stop debug (0001
x111)
While in debug mode, the SBC can be used without
having to clear the W/D on a regular basis to facilitate
software and hardware debugging.
Step 6) To leave the debug mode, write 0000 to the MCR
register.
To avoid entering the debug mode after a power up, first
read the BATFAIL bit (MCR read) and write 0000 into the
MCR.
Figure 11 illustrates entering the debug mode.
VSUP
VDD1
BATFAIL
TIM1(step 3)
MCR(step4)
MCR (step5)
SPI: read batfail
SBC in debug Mode, no W/D
MCR (step6)
SPI
debug mode
SBC not in debug Mode and W/D on
Figure 11. Debug Mode Enter
MCU FLASH PROGRAMMING CONFIGURATION
output by external signal sources to zero or 5.0 V without
damage. This supplies the complete application board with
external power supply and applies the correct signal to the
reset pin.
To facilitate the possibility of down loading software into
the application memory (MCU EEPROM or Flash), the SBC
allows the following capabilities: The VDD1 can be forced by
an external power supply to 5.0 V and the reset and WDOG
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
CAN TRANSCEIVER DESCRIPTION
Vsup
V2
VSE-H (1.85V)
SH
CANH
Driver
Vdiff
CANH
RTL
CANL
SL
SRL
Stvbat
VSE-L (3.05V)
RtL
RXD
Rx multiplexer
RTH
SRH
RtH
V2
Failure detection
CANL
TXD
Driver
Tx driver
V2
Vwake-H (2V)
CANH
Hwake
CAN
mode control
GND
CANL
SPI
Lwake
Vwake-L (3V)
Figure 12. Simplified Block Diagram of the CAN Transceiver of the MC33889
General description
CAN driver:
Stvbat. Each node must have a resistor connected between
CANH and RTH and between CANL and RTL. The resistor
value should be between 500 and 16000 ohms.
The CANH driver is a “high side” switch to the V2 voltage
(5V). The CANL driver is a “low side” switch to gnd.The turn
on and turn off time is controlled in order to control the slew
rate, and the CANH and CANL driver have a current limitation
as well as an over temperature shutdown.
Transmitter Function
CAN bus levels are called Dominant and Recessive, and
correspond respectively to Low and High states of the TX
input pin.
The CAN H or CANL driver can be disabled in case a
failure is detected on the CAN bus (ex: CANH driver is
disabled in case CANH is shorted to VDD). The disabling of
one of the drivers is controlled by the CAN logic and the
communication continues via the other drivers. When the
failure is removed the logic detects a failure recovery and
automatically reenables the associated driver.
Dominant state:
The CANH and CANL drivers are on. The voltage at CANL
is <1.4V, the voltage at CANH is >3.6V, and the differential
voltage between CANH and CANL line is >2.2V (3.6V-1.4V).
Recessive state:
This is a weak state, where the CANH and CANL drivers
are off. The CANL line is pulled up to 5V via the RTL pin and
RTL resistor, and the CANH line is pull down via the RTH and
RTH resistor. The resultant voltage at CANL is 5V and 0V at
CANH. The differential voltage is -5V (0V - 5V). The
recessive state can be over written by any other node forcing
a Dominant state.
The CAN drivers are also disabled in case of a Tx failure
detection.
Bus termination:
The bus is terminated by pull up and pull down resistors,
which are connected to GND, VDD or VBAT through
dedicated RTL and RTH pins and internal switches Srh, Srl,
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
30
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Receiver Function
RTL resistor and internal pull up resistor of 12.5kOhms. In
this mode, the device monitors the bus activity and if a wake
up conditions is encountered on the CAN bus, it will wakes up
the MC33889.
In normal operation (no bus failures), RX is the image of
the differential bus voltage. The differential receiver inputs
are connected to CANH and CANL.
The device will enter into a normal request mode if low
power mode was in sleep, or generates an INT. It enters into
Normal request mode if low power mode was in stop mode.
If the device was in normal or stand by mode, the Rx pin will
report a wake up (feature not available on the MC33889B).
See Rx pin behavior.
The device incorporates single ended comparators
connected to CANH and CANL in order to monitor the bus
state as well as detect bus failures. Failures are reported via
the SPI.
In normal operation when no failure is present, the
differential comparator is active. Under a fault condition, one
of the two CANH or CANL pins can be become non-
operational. The single ended comparator of either CANH or
CANL is activated and continues to report a bus state to Rx
pin. The device permanently monitors the bus failure and
recovery, and as soon as fault disappears, it automatically
switches back to differential operation.
Bus Failure Detection
General description:
The device permanently monitors the bus lines and
detects faults in normal and receive only modes. When a fault
is detected, the device automatically takes appropriate
actions to minimize the system current consumption and to
allow communication on the network. Depending on the type
of fault, the mode of operation, and the fault detected, the
device automatically switches off one or more of the following
functions: CANL or CANH line driver, RTL or RTH termination
resistors, or internal switches. These actions are detailed in
the following table.
CAN interface operation Mode
The CAN has 3 operation modes: TxRx (Transmit-
Receive), Receive Only, and Term-VBAT (Terminated to
VBAT). The mode is selected by the SPI. As soon as the
MC33889 mode is sleep or stop (selected via MCR register),
the CAN interface automatically enters Tem-Vbat mode.
The device permanently monitors the faults and in case of
fault recovery, it automatically switches back to normal
operation and reconnects the open functions. Fault detection
and recovery circuitry have internal filters and delays timing,
detailed in the AC characteristics parameters.
Tx Rx mode:
In this mode, the CAN drivers and receivers are enabled,
and the device is able to send and receive messages. Bus
failures are detected and managed, this means that in case
of a bus failure, one of the CAN drivers can be disabled, but
communication continues via the remaining drivers.
The failure list identification and the consequence on the
device operation are described in following table. The failure
detection, and recovery principle, the transceiver state after a
failure detected, timing for failure detection and recovery can
be found in the ISO11898-3 standard.
Receive Only mode:
In this mode, the transmitter path is disabled, so the device
does not drive the bus. It maintains CANL and CANH in the
recessive state. The receiver function operates normally.
The following table is a summary of the failure
identifications and of the consequences on the CAN driver
and receiver when the CAN is in Tx Rx mode.
TermVbat mode:
In this mode, the transmitter and receiver functions are
disabled. The CANL pin is connected to VSUP through the
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Bus failure
Description
identification
Consequence on CAN driver
Consequence on Rx pin
no failure
default operation: CAN H and CANL driver active,
RTH and RTL termination switched ON
default operation: Report differential
receiver output
1
5
CANH open wire
default operation
default operation
default operation
default operation
CANH shorted to gnd
8, 3a
CANH shorted to Vdd
(5V)
CANH driver turn OFF. RTH termination switched
OFF
Rx report CANL single ended receiver
3
CANH shorted to Vbat
CANL open wire
CANH driver turn OFF. RTH termination switched
OFF
Rx report CANL single ended receiver
2
default operation
default operation
4, 7
CANL shorted to gnd or
CANL shorted to CANH
CANL driver is OFF. RTL termination switched
OFF
Rx report CANH single ended receiver
9
6
CANL shorted to Vdd (5V)
CANL shorted to Vbat
CANL driver is ON. RTL termination active
default operation
CANL driver is OFF. RTL termination switched
OFF
Rx report CANH single ended receiver
Open wire detection operation:
Description:
MC33889 will receive information on one wire only and the
consequences are as follows:
when the bus is set in dominant:
The CANH and CANL open wire failures are not described
in the ISO document. Open wire is only diagnostic
information, as no CAN driver or receiver state will change in
case of an open wire condition.
- The differential receiver will toggle
- Only one of the single ended receivers CANH or of CANL
will toggle
The following figure illustrates the CAN signal during
normal communication and in the example of a CANH open
wire. The single ended receiver is sampled at the differential
receiver switching event, in a window of 1µs.
In case one of the CAN wires are open, the communication
will continue through the remaining wire. In this situation the
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
32
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
(No open wire, or open wire recovery)
(CAN H open wire)
Rec
Dom
Rec
Rec
Dom
Rec
CANL
CANL
CANH
CANH
Sampling point
Sampling point
-3.2V
Diff
-3.2V
Diff
S-L
S-L
S-H
S-H
1us
Sampling recessive level
= > open wire “detection pulse”
Sampling dominant level
= > no failure or “recovery pulse”
Figure 13. CAN Normal Signal Communication and CAN Open Wire
S-H
Sampling
1us
CANH
CANL
Diff
Rec
Dom
S-L
Sampling
1us
CANH counter
L-counter +/-
(count = 4) (count = 0)
L-open recover
Figure 14. Open Wire Detection Principle
Open wire detection, MC33889B and D:
Open wire recovery:
When the open wire failure has recovered, the difference
Failure detection:
in count is reduced and the device detects the open wire
recovery.
The device will detect a difference in toggling counts
between the differential receiver and one of the single ended
receivers. Every time a difference in count is detected a
counter is incremented. When the counter reaches 4, the
device detects and reports an open wire condition. The open
wire detection is performed only when the device
receives a message and not when it send message.
MC33889B:
When detection is complete, the counter is no longer
incremented. It can only be decremented by sampling of the
dominant level on the S-H (S-L) (recovery pulse). When it
reaches zero, the failure has recovered.
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
In application, with CAN communication, a recovery
condition is detected after 4 acknowledge bits are sent by the
MC33889B.
permanent dominant bus state. If TX is low for more than
0.75-4ms, the bus output driver is disabled. This avoids
blocking communication between other nodes of the network.
TXD is reported via the SPI (RCR register bit D1:
TXFAILURE). Tx permanent dominant recovery is done with
TX recessive for more than typ 32us.
MC33889D:
When detection is complete, the counter is decremented
by sampling the dominant pulse (recovery pulse) on S-H (S-
L), and incremented (up to 4) by sampling the recessive pulse
(detection pulses) on S-H (S-L). It is necessary to get 4
consecutive dominant samples (recovery pulse) to get to
zero. When reaching zero, the failure is recovered.
Rx pin behavior while CAN interface is in TermVbat.
The MC33889D is able to signal bus activity on Rx while
the CAN interface is in TermVbat and the SBC in normal or
standby mode. When the bus is driven into a dominant state
by another sending node, each dominant state is reported at
In application with real CAN communication, a recovery
condition will not be detected by a single acknowledge bit
send by MC33889D, but requires a complete CAN message
(at least 4 dominant bits) send in dual wire mode, without
reception of any bit in single wire mode.
Rx by a low level, after a delay of TWAKE
.
The bus state report is done through the CAN interface
wake up comparator on CANL and CANH, and thus operates
also in case of bus failure. This is illustrated in the following
figure.
Tx permanent dominant detection:
In addition to the previous list, the MC33889 detects a
permanent low state at the TX input which results in a
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
34
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Other CAN node send
CANL terminated to Vbat
Recessive
state
Recessive
state
Dominant
state
Dominant
state
CANL
CANH
Rx
TWAKE
TWAKE
CAN in TxRx
MC33889D in Normal mode
CAN in TermVbat
MC33889D in Normal mode, Standby mode or in stop mode
CAN in TxRx
MC33889D in Normal mode
TWAKE: duration of the CAN wake up filter, typ 16µs. The MC33889D Rx dominant low level duration is the difference
between the duration of the bus minus the Twake, as illustrated below (Trx_dom = Tbus_dom - Twake)
Tx sender node
Example: A dominant duration at the bus level of 5
bits of 8us each results in a 40us bus dominant.
This results in a 24µs (40µs-16µs) dominant level at
Dominant state
Rx of MC33889D (while the CAN of the MC33889D
is in TermVbat).
Tx MC33889D
Rx MC33889D
TWAKE
TRX_DOM
TBUS_DOM
Figure 15. Bus State Report of the CAN Interface Wake-Up Comparator on CANL and CANH
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The following table summarizes the device behavior when a CAN Wake Up event occurs.
Table 6. Summary of RX Pin Operations for Wake up Signaling
SBC mode
CAN state
MC33889B
MC33889D
Normal
Standby
Sleep
TermVbat
TermVbat
TermVbat
no event on RX, no bit set
no event on RX, no bit set
RX pulse (1), bit CANWU is not set
RX pulse (1), bit CANWU is not set
SBC mode transition to Normal
request, bit CANWU set
SBC mode transition to Normal
request, bit CANWU set
Stop
TermVbat
INT pulse, bit CANWU set
Int pulse, bit CANWU set
Notes
29. pulse duration is bus dominant duration minus Twake.
GND SHIFT DETECTION
GENERAL
DETECTION PRINCIPLE
The gnd shift to detect is selected via the SPI from 4
different values (-0.3 V, -0.7 V, -1.2 V, -1.7 V). At each TX
falling edge (end of recessive state), the CANH voltage is
sensed. If it is detected to be below the selected gnd shift
threshold, the bit SHIFT is set at 1 in the IOR register. No filter
is implemented. Required filtering for reliable detection
should be done by software (e.g. several trials).
When normally working in two-wire operating mode, the
CAN transmission can afford some ground shift between
different nodes without trouble. Should a bus failure occur, the
transceiver switches to single-wire operation, therefore
working with less noise margin. The affordable ground shift is
decreased.
The SBC provides a ground shift detection for diagnosis
purpose. The four ground shift levels are selectable and the
detection is stored in the IOR register which is accessible via
the SPI.
DEVICE STATE DESCRIPTION
Table 7. 33889 Table of Operations
The table below describe the SBC operation modes.
VOLTAGE
REGULATOR
HS1 SWITCH
WAKE-UP
CAPABILITIES
(IF ENABLED)
SOFTWARE
WATCHDOG
MODE
RESET PIN
INT
CAN CELL
Normal Request
VDD1: ON
V2: OFF
Low for 1ms, then
high
term Vbat
HS1: OFF
Normal
VDD1: ON
V2: ON
Normally high.
Active low if W/D signal failure
or VDD1 under
voltage occur
If enabled,
Running
Running
Term Vbat
Tx/Rx
(VDD pre
warning temp,
CAN, HS1)
HS1 controllable
Rec only
Standby
Stop
VDD1: ON
V2: OFF
Normally high.
Active low if W/D signal failure
or VDD1 under
voltage occur
If enabled,
Term Vbat
Tx/Rx
(VDD temp,
HS1)
HS1 controllable
Rec only
VDD1: ON
CAN (always enable)
SPI and L0,L1
Normally high.
Active low if W/D
or VDD1 under
voltage occur
Signal SBC
wake-up
- Running if
enabled
Term Vbat.
(limited current
capability)
(not maskable) - Not Running
if disabled
Cyclic sense or
V2: OFF
Forced Wake-up
HS1: OFF or cyclic
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
36
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 7. 33889 Table of Operations
The table below describe the SBC operation modes.
VOLTAGE
REGULATOR
HS1 SWITCH
WAKE-UP
CAPABILITIES
(IF ENABLED)
SOFTWARE
CAN CELL
MODE
RESET PIN
INT
WATCHDOG
Sleep
VDD1: OFF
V2: OFF
CAN (always enable
SPI and L0,L1
Low
Not active
No Running
Term Vbat.
HS1 OFF or cyclic
Cyclic sense
Forced Wake-up
State Machine (not valid in debug modes)
W/D: timeout OR VDD1 low
W/D: timeout & Nostop & !BATFAIL
Reset counter
(1 ms) expired
SPI: standby &
2
1
W/D
trigger
(note1)
3
Standby
Reset
Normal Request
1
VDD1 low OR W/D: time
out 350 ms & !Nostop
4
2
Power
Down
1
Normal
Stop
SPI: Stop & CS
low to high
transition
1
W/D: timeout OR VDD1 low
Wake-up
(VDD1 high temperature OR (VDDd1 low > 100 ms & VSUP >BFew)) & Nostop & !BATFAIL
Sleep
denotes priority
1
2
3
4
State machine description:
“W/D: timeout” means TIM1 register not written before W/D timeout period
expired, or W/D written in incorrect time window if window W/D selected
(except stop mode). In normal request mode timeout is 355 ms p2.2 (350 ms
p3)ms.
“Nostop” means Nostop bit = 1
“! Nostop” means Nostop bit = 0
“BATFAIL” means Batfail bit = 1
“! BATFAIL” means Batfail bit = 0
“VDD1 over temperature” means VDD1 thermal shutdown occurs
“VDD1 low” means VDD1 below reset threshold
“VDD1 low > 100 ms” means VDD1 below reset threshold for more than
“SPI: Sleep” means SPI write command to MCR register, data sleep
“SPI: Stop” means SPI write command to MCR register, data stop
“SPI: Normal” means SPI write command to MCR register, data normal
“SPI: Standby” means SPI write command to MCR register, data standby
100 ms
Note 1: these 2 SPI commands must be send in this sequence and
“W/D: Trigger” means TIM1 register write operation.
consecutively.
VSUP > BFew means VSUP > Battery Fall Early Warning (6.1 V typical)
Note 2: if W/D activated
Figure 16. Simplified State Machine
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Behavior at SBC power up
Figure 17. Behavior at SBC Power Up
Transitions to enter debug modes
W/D: timeout 350 ms
Power
Down
Reset counter
Reset
Normal Request
(1.0 ms) expired
SPI: MCR (0000) & Normal Debug
Normal Debug
Normal
SPI: MCR (0000) & Standby Debug
Standby Debug
Figure 18. Transitions to Enter Debug Modes
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
38
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Simplified State machine in debug modes
W/D: timeout 350ms
Wake-up
Wake-up
Reset counter
(1ms) expired
Reset
Sleep
Stop (1)
Normal Request
R
R
R
R
R
Normal
Standby
E
E
SPI: Standby debug
SPI: Normal debug
Normal Debug
Standby Debug
R
R
(1) If stop mode entered, it is entered without watchdog, no matter the WDSTOP bit.
(E) debug mode entry point (step 5 of the debug mode entering sequence).
(R) represents transitions to reset mode due to Vdd1 low.
Figure 19. Simplified State Machine in Debug Mode
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SPI INTERFACE
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
A2 A1 A0 R/W D3 D2 D1
Bit0
D0
MISO
MOSI
Read operation: R/W bit = 0
Write operation: R/W bit = 1
address
data
Figure 20. Data Format Description
The SPI is a 8 bit SPI. First 3 bits are used to identify the internal SBC register address, bit 4 is a read/write bit. The last 4 bits
are data send from MCU to SBC or read back from SBC to MCU.
During write operation state of MISO has no signification.
During read operation only the last 4 bits at MISO have a meaning (content of the accessed register)
Following tables describe the SPI register list, and register bit meaning.
Registers “reset value” is also described, as well as the “reset condition”. reset condition is the condition which cause the bit
to be set at the “reset value”.
Possible reset condition are:
Power On Reset: POR
SBC mode transition:
NR2R - Normal Request to Reset mode
NR2N - Normal Request to Normal mode
N2R - Normal to Reset mode
STB2R - Standby to Reset mode
STO2R - Stop to Reset mode
SBC mode:RESET - SBC in Reset mode
33889
Analog Integrated Circuit Device Data
40
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 8. List of Registers
Name
Address
Description
Comment and usage
Write: Control of normal, standby, sleep, and stop modes
Read: BATFAIL flag and other status bits and flags
MCR
$0 0 0
Mode control register
Write: Configuration of reset voltage level, WD in stop mode, low power
mode selection
RCR
CAN
$0 0 1
$0 1 0
Reset control register
CAN control register
Read: CAN wake-up event, Tx permanent dominant
Write: CAN module control: TX/RX, Rec only, term VBAT, Normal and
extended modes, filter at L0 input.
Read: CAN failure status bits
Write: HS1 (high-side switch) control in normal and standby mode.
Gnd shift register level selection
Read: HS1 over temp bit, SHIFT bit (gnd shift above selection), VSUP
below 6.1V, V2 below 4.0 V
IOR
$0 1 1
I/O control register
Write: Control of wake-up input polarity
Read: Wake-up input, and real time LX input state
WUR
TIM
$1 0 0
$1 0 1
$1 1 0
$1 1 1
Wake-up input register
Timing register
Write: TIM1, Watchdog timing control, window or Timeout mode.
Write: TIM2, Cyclic sense and force wake-up timing selection
Low power mode
control register
Write: HS1 periodic activation in sleep and stop modes
Force wake-up control
LPC
INTR
Write: Interrupt source configuration
Read: INT source
Interrupt register
Register description
Table 9. MCR Register
MCR
D3
D2
D1
D0
$000b
W
MCTR2
VDDTEMP
0
MCTR1
GFAIL
MCTR0
WDRST
0
R
BATFAIL
0
Reset
0
Reset condition
POR, RESET
POR, RESET
POR, RESET
Table 10. Control bits
MCTR2
MCTR1
MCTR0
SBC MODE
DESCRIPTION
0
0
0
Enter/leave debug mode
To enter debug mode, SBC must be in Normal or
Standby mode and BATFAIL(1) must be still at 1. To
leave debug mode, BATFAIL must be at 0.
0
0
0
0
1
1
1
0
1
Normal
Standby
Stop, watchdog off (2)
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
MCTR2
MCTR1
MCTR0
SBC MODE
Stop, watchdog on (2)
DESCRIPTION
0
1
1
1
0
0
1
0
1
Sleep (3)
Normal
No watchdog running, debug mode
1
1
0
Standby
Stop (4)
1
1
1
(1): Bit BATFAIL cannot be set by SPI. BATFAIL is set when VSUP falls below 3V.
(2): Watchdog ON or OFF depends on the RCR register bit D3.
(3): Before entering sleep mode, bit NOSTOP in RCR register must be previously set to 1.
(4): Stop command should be replaced by Stop Watchdog OFF. MCTR2=0, MCTR1= MCTR0=1
Table 11. Status bits
STATUS BIT
DESCRIPTION
GFAIL
BATFAIL
VDDTEMP
WDRST
Logic OR of CAN failure, HS1 failure, V2LOW
Battery fail flag (VSUP<3V)
Temperature pre-warning on VDD (latched)
Watchdog reset occurred
Table 12. RCR register
RCR
D3
D2
D1
D0
RSTTH
CANWU
0
$001b
W
R
WDSTOP
NOSTOP
TXFAILURE
Reset
1
0
Reset condition
POR, RESET
POR, NR2N
POR
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
42
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 13. Control bits
Status bit
Bit value
Description
WDSTOP
0
1
0
1
0
1
1
1
No watchdog in stop mode
Watchdog runs in stop mode
NOSTOP
RSTTH
Stop mode is default low power mode
Sleep mode is default low power mode
Reset threshold 1 selected (typ 4.6V)
Reset threshold 2 selected (typ 4.2V)
Wake-rom CAN
CANWU
TXFAILURE
Tx permanent dominant (CAN)
Table 14. CAN register
Some description.
CAN
D3
FDIS
CS3
0
D2
D1
D0
CCTR0
CS0
$010b
W
R
CEXT
CS2
CCTR1
CS1
Reset
0
0
0
Reset condition
POR, CAN
POR, CAN
POR, CAN
POR, CAN
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Fault tolerant CAN transceiver standard modes
The CAN transceiver standard mode can be programmed by setting CEXT to 0. The transceiver cell will then be behave as
known from MC33388.
Table 15. CAN Transceiver Modes
CEXT
CCTR1
CCTR0
Mode
0
0
0
0
0
0
1
1
0
1
0
1
TermVBAT
RxOnly
RxTx
Table 16. CAN transceiver extended modes (CAN with CEXT bit =1 is not recommended)
CEXT (1)
CCTR1
CCTR0
Mode
TermVBAT
TermVDD
RxOnly
1
1
1
1
0
0
1
1
0
1
0
1
RxTx
Fault tolerant CAN transceiver extended modes
By setting CEXT to 1 the transceiver cell supports sub bus communication
Note1: CEXT Bit should be set at 0. The CAN operation in extended mode is not recommended.
FDIS
L0 wake input filter (20 µs typical)
Enable (LO wake threshold selectable by WUR register)
0
1
Disable (L0 wake-up threshold is low level only, no matter D0 and D1 bits set in WUR register).
Note: if DFIS bit is set to 1, WUR register must be read before going into sleep or stop mode in order to clear the wake-up flag.
During read out L0 must be at high level and should stay high when entering sleep or stop.
33889
Analog Integrated Circuit Device Data
44
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 17. Status bits
CS3
0
CS2
0
CS1
0
CS0
0
Bus failure #
Description
no failure
0
0
0
1
1
5
CANH open wire
0
1
0
1
CANH short circuit to
ground
VDD
0
1
1
0
8, 3a
3
0
1
1
1
VBAT
1
0
0
1
2
CANL open wire
CANL short circuit to
1
1
0
1
4, 7
9
ground / CANH
VDD
1
1
1
0
1
1
1
1
6
VBAT
Comments:
CS2 bit at 0 = open failure. CS2 bit at 1 = short failure.
(CS3 bit at 0 and (CS1 = 1 or CS2 =1)) = CANH failure. CS3 bit at 1 = CANL failure.
CS1 and CS0 bits: short type failure coding (gnd, VDD or VBAT).
In case of multiple failures, the last failure is reported.
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 18. IOR register.
IOR
D3
D2
HS1ON
HS1OT
0
D1
GSLR1
V2LOW
0
D0
GSLR0
$011b
W
R
SHIFT
VSUPLOW
0
Reset
Reset condition
POR, RESET
POR, RESET
POR, RESET
Table 19. Control bits
HS1ON
HS1
0
1
HS1 switch turn OFF
HS1 switch turn ON
Table 20. Gnd shift selection
GSLR1
GSLR0
Typical gnd shift comparator level
0
0
1
1
0
1
0
1
-0.3 V
-0.7 V
-1.2 V
-1.7 V
Shift
State
0
1
Gnd shift value is lower than the level selected by the GSLR1 and GSLR2 bit
Gnd shift value is higher than the level selected by the GSLR1 and GSLR2 bit
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
46
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 21. Status bits
Status bit
HS1OT (*)
SHIFT
Description
High-side 1 over temperature
gnd shift level selected by GSLR1 and GSLR2 bits is reached
V2 below 4.0 V typical
V2LOW
VSUPLOW
VSUP below 6.1 V typical
(*) Once the HS1 switch has been turned off because of over temperature, it can be turned on again by setting the appropriate
control bit to “1”.
WUR REGISTER
The local wake-up inputs L0 and L1 can be used in both normal and standby mode as port expander and for waking up the
SBC in sleep or stop mode.
Table 22. WUR Register
WUR
D3
LCTR3
L1WUb
1
D2
LCTR2
L1WUa
1
D1
LCTR1
L0WUb
1
D0
LCTR0
L0WUa
1
$100b
W
R
Reset
Reset condition
POR, NR2R, N2R, STB2R, STO2R
Table 23. Control bits:.
LCTR3
LCTR2
LCTR1
LCTR0
L0 configuration
inputs disabled
L1 configuration
X
X
X
X
0
0
1
1
X
X
X
X
0
1
0
1
0
0
0
1
high level sensitive
low level sensitive
both level sensitive
1
0
1
1
X
X
X
X
X
X
X
X
inputs disabled
high level sensitive
low level sensitive
both level sensitive
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 24. Status bits
FDIS bit in CAN
register
L0WUb
L0WUa
Description
0
0
0
0
1
No wake-up occurred at L0 (sleep or stop mode).
Low level state on L0 (standby or normal mode)
1
0
1
1
Wake-up occurred at L0 (sleep or stop mode).
High level state on L0 (standby or normal mode)
Wake-up occurred at L0 (sleep or stop mode with L0 filter disable). WUR must be set
to xx00 before sleep or stop mode.
L1WUb
L1WUa
Description
0
1
0
1
No wake-up occurred at L1 (sleep or stop mode).
Low level state on L1 (standby or normal mode)
Wake-up occurred at L1 (sleep or stop mode).
High level state on L1 (standby or normal mode)
TIM REGISTERS
Description: This register is split into 2 sub registers, TIM1 and TIM2.
TIM1 controls the watchdog timing selection as well as the window or timeout option. TIM1 is selected when bit D3 is 0.
TIM2 is used to define the timing for the cyclic sense and forced wake-up function. TIM2 is selected when bit D3 is 1.
No read operation is allowed for registers TIM1 and TIM2
TIM REGISTER
Table 25. TIM Register.
TIM1
D3
D2
D1
D0
$101b
W
R
0
WDW
WDT1
WDT0
Reset
0
0
0
Reset condition
POR, RESET
POR, RESET
POR, RESET
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
48
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 26. Watch dog
WDW
WDT1
WDT0
Watchdog timing [ms]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10
50
no window watchdog
100
350
10
window watchdog enabled (window lenght is
half the watchdog timing)
50
100
350
Table 27. jWatchdog operation (window and timeout)
window closed
no watchdog clear
window open
for watchdog clear
window open
for watchdog clear
WD timing * 50%
WD timing * 50%
Watchdog period
Watchdog period
(WD timing selected by TIM 1 bit WDW=1)
(WD timing selected by TIM 1, bit WDW=0)
Window watchdog
Timeout watchdog
TIM2 REGISTER
The purpose of TIM2 register is to select an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices
by switching on or off HS1
Table 28. TIM2 Register
TIM2
D3
D2
D1
D0
$101b
W
R
1
CSP2
CSP1
CSP0
Reset
0
0
0
Reset
POR, RESET
POR, RESET
POR, RESET
condition
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
49
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 29. Cyclic Sense Timing
CSP2
CSP1
CSP0
Cyclic sense timing [ms]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5
10
20
40
75
100
200
400
Cyclic sense on time
Cyclic sense timing
10 µs to 20 µs
HS1
Sample
t
LPC REGISTER
Description: This register controls:
- The state of HS1 in stop and sleep mode (HS1 permanently off or HS1 cyclic)
- Enable or Disable the forced wake-up function (SBC automatic wake-up after time spend in sleep or stop mode, time defined
by TIM2 register)
- Enable or disable the sense of the wake-up inputs (LX) at sampling point of the cyclic sense period (LX2HS1 bit).
Table 30. LPC Register
LPC
D3
D2
D1
D0
$110b
W
R
LX2HS1
FWU
IDDS
HS1AUTO
Reset
0
0
0
0
Reset condition
POR, NR2R, N2R,
STB2R, STO2R
POR, NR2R, N2R,
STB2R, STO2R
POR, NR2R, N2R,
STB2R, STO2R
POR, NR2R, N2R,
STB2R, STO2R
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
50
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LX2HS1
HS1AUTO
Wake-up inputs supplied by HS1
Autotiming HS1
X
X
0
1
0
1
off
On, HS1 cyclic, period defined in TIM2 register
X
X
no
Yes, LX inputs sensed at sampling point
Bit
Description
FWU
IDDS
If this bit is set, and the SBC is turned into sleep or stop mode, the SBC wakes up after the time selected in the
TIM2 register
Bit = 0: IDDS-WU1 selected (lowest value, typ 3.5mA)
Bit = 1: IDDS-WU2 selected (highest value, typ 14mA)
Table 31. INTR register
INTR
D3
D2
HS1OT-V2LOW
HS1OT
D1
VDDTEMP
VDDTEMP
0
D0
CANF
$111b
W
R
VSUPLOW
VSUPLOW
0
CANF
Reset
0
0
Reset condition
POR, RESET
POR, RESET
POR, RESET
POR, RESET
Table 32. Control bits:
Control bit
CANF
Description
Mask bit for CAN failures (OR of any CAN failure)
Mask bit for VDD medium temperature
VDDTEMP
HS1OT-V2LOW
VSUPLOW
Mask bit for HS1 over temperature OR V2 below 4V
Mask bit for SUP below 6.1V
When the mask bit has been set, INT pin goes low if the appropriate condition occurs.
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
51
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 33. Status bits:
Status bit
CANF
Description
CAN failure
VDDTEMP
HS1OT
VDD medium temperature
HS1 over temperature
VSUP below 6.1V typical
VSUPLOW
Notes:
Bit D2 = 1: INT source is HS1OT
Bit D2 = 0: INT source is V2LOW.
If HS1OT-V2LOW interrupt is only selected (only bit D2 set
in INTR register), reading INTR register bit D2 leads to two
possibilities:
Upon a wake-up condition from stop mode due to over current detection (IDD1S-WU1 or IDD1S-WU2), an INT pulse is generated,
however INTR register contain remains at 0000 (not bit set into the INTR register).
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
52
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
5V
Q1
RB
VBAT
V2CTRL
V2
VSUP monitor
Dual Voltage Regulator
VDD1 Monitor
CAN
VSUP
supply
5V/200mA
VDD1
5V/200mA
Mode control
Oscillator
HS1 control
HS1
INT
Interrupt
Watchdog
Reset
Programmable
wake-up input
L0
L1
WDOG
RESET
MOSI
SCLK
MISO
SPI Interface
CS
RTH
RRTH
RRTL
V2
Low Speed
CANH
TXD
Fault Tolerant CAN
Physical Interface
RXD
GND
CANL
RTL
Figure 21. 33889D/33889B Simplified Typical Application with Ballast Transistor
5V/100mA
VBAT
V2CTRL (open)
V2
VSUP Monitor
Dual Voltage Regulator
VDD1 Monitor
CAN
supply
VSUP
VDD1
5V/200mA
5V/100mA
Mode Control
Oscillator
HS1 Control
HS1
INT
Interrupt
Watchdog
Reset
Programmable
wake-up input
L0
L1
WDOG
RESET
MOSI
SCLK
MISO
SPI Interface
CS
RTH
RRTH
RRTL
V2
Low Speed
CANH
TX
Fault Tolerant CAN
Physical Interface
RX
GND
CANL
RTL
Figure 22. 33889D/33889B Simplified Typical Application without Ballast Transistor
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
53
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A
number listed below.
DW SUFFIX
EG SUFFIX (PB-FREE)
28-PIN
PLASTIC PACKAGE
98ASB42345B
ISSUE G
33889
Analog Integrated Circuit Device Data
54
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
DW SUFFIX
EG SUFFIX (PB-FREE)
28-PIN
PLASTIC PACKAGE
98ASB42345B
ISSUE G
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
55
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
ADDITIONAL DOCUMENTATION
33889
THERMAL ADDENDUM (REV 1.0)
Introduction
This thermal addendum is provided as a supplement to the MC33889 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
28-PIN
SOICW
Packaging and Thermal Considerations
The MC33889 is offered in a 28 pin SOICW, single die package. There is a
single heat source (P), a single junction temperature (TJ), and thermal resistance
(RθJA).
DWB SUFFIX
98ASB42345
28-PIN SOICW
TJ
.
=
RθJA
P
Note For package dimensions, refer to
the 33889 device datasheet.
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not
meant to and will not predict the performance of a package in an application-
specific environment. Stated values were obtained by measurement and
simulation according to the standards listed below.
Standards
Table 34. Thermal Performance Comparison
Thermal Resistance
[°C/W]
(1) (2)
Ρ
Ρ
Ρ
42
11
69
23
θJA
θJB
θJA
(2) (3)
(1) (4)
Ρ ϑΧ (5)
θ
Notes
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the center lead.
20 Terminal SOICW
1.27 mm Pitch
18.0 mm x 7.5 mm Body
4. Single layer thermal test board per JEDEC JESD51-3.
5. Thermal resistance between the die junction and the
package top surface; cold plate attached to the package top
surface and remaining surfaces insulated.
Figure 23. Surface Mount for SOIC Wide Body
Non-Exposed Pad
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
56
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RX
TX
VDD1
RST
WDOG
CS
A
2
3
MOSI
MISO
SCLK
GND
GND
GND
GND
CANL
CANH
RTL
4
5
INT
6
GND
GND
GND
GND
V2CTRL
VSUP
HS1
7
8
9
10
11
12
13
14
L0
L1
RTH
V2
33889DWB Pin Connections
28-Pin SOICW
1.27 mm Pitch
18.0 mm x 7.5 mm Body
Figure 24. Thermal Test Board
Device on Thermal Test Board
Table 35. Thermal Resistance Performance
Material:
Single layer printed circuit board
FR4, 1.6 mm thickness
Thermal
Area A (mm2)
(°C/W)
Resistance
Cu traces, 0.07 mm thickness
Ρ
0
69
53
48
θJA
Outline:
80 mm x 100 mm board area,
including edge connector for thermal
testing
300
600
Area A:
Cu heat-spreading areas on board
surface
ΡθJA ισ τηε τηερµαλ ρεσιστανχε βετωεεν διε ϕυνχτιον ανδ
αµβιεντ αιρ.
Ambient Conditions: Natural convection, still air
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
57
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
80
70
60
50
40
30
20
10
0
x
ΡθJA
0
300
Heat spreading area [mm²]
600
A
Figure 25. Device on Thermal Test Board RθJA
100
10
1
x
ΡθJA
0.1
1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04
Time[s]
Figure 26. Transient Pin Resistance ΡθJA
Device on Thermal Test Board Area A = 600 (mm2)
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
58
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
• Implemented Revision History page
• Added “EG” PB-Free package type
5/2006
7.0
• Removed MC33889DW version, and added MC33889B and MC33889D versions
• Converted to the Freescale format, and updated to the prevailing form and style
• Modified Device Variations Between the 33889D and 33889B Versions (1) on page 2
• Added Thermal Addendum (rev 1.0) on page 56
• Changed the Maximum Ratings on page 6 to the standard format
• Added CAN transceiver description section
• Corrected two instances where pin LO had an overline, and one instance where pin
WDOG did not.
6/2002
8/2006
9/2006
8.0
9.0
• Removed MC33889BEG/R2 and MC33889DEG/R2 and replaced them with
MCZ33889BEG/R2 and MCZ33889DEG/R2 in the Ondering Information block
• Replaced the label Logic Inputs with Logic Signals (RX, TX, MOSI, MISO, CS, SCLK,
RST, WDOG, INT) on page 6
10.0
• Changed CS to CS at various places in the document
• Made changes to Supply Current in Stand-by Mode (7),(9) on page 8 and Supply Current
12/2006
11.0
in Normal Mode (7) on page 8
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
59
How to Reach Us:
Home Page:
www.freescale.com
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
For information on Freescale’s Environmental Products program, go to http://
www.freescale.com/epp.
Tempe, Arizona 85284
+1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Semiconductor was negligent regarding the design or manufacture of the part.
Denver, Colorado 80217
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
© Freescale Semiconductor, Inc., 2006. All rights reserved.
MC33889
Rev. 11.0
12/2006
相关型号：
©2020 ICPDF网 联系我们和版权申明