MC33385DHR2 [FREESCALE]

Quad Low-side Driver; 四通道低侧驱动器
MC33385DHR2
型号: MC33385DHR2
厂家: Freescale    Freescale
描述:

Quad Low-side Driver
四通道低侧驱动器

驱动器 接口集成电路 光电二极管
文件: 总18页 (文件大小:402K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Document Number: MC33385  
Rev. 6.0, 11/2006  
Freescale Semiconductor  
Technical Data  
Quad Low-side Driver  
33385  
The MC33385 is a Quad Low-side Driver fully protected switch. This  
device is a general purpose Low-side Driver but has been especially  
designed to operate in engine management applications as injector  
driver or automotive gear box. It is interfaced directly with a  
microcontroller for parallel control of the load and the individual output  
diagnostic is done through a SPI. The diagnostic logic recognizes 4  
failure types at each output stage: overcurrent, short to GND, open  
load, and over-temperature.  
LOW-SIDE DRIVER  
Features  
• RDSON of 250mper Output at 25°C  
• Supplied from the main 5V VCC  
DH SUFFIX  
VW SUFFIX (PB-FREE)  
98ASH70702A  
• Input CMOS Compatible  
• Diagnostic through SPI  
• Nominal Current of 2A per Output  
20-PIN HSOP  
• Current Limitation at 3A with Automatic Turn Off  
• Output Internally Clamped at 50V typ for Inductive Load Drive  
• Junction to Case Thermal Resistance of 4.4°C/W  
• Individual Output over Temperature Shutdown  
• Pb-Free Packaging Designated by Suffix Code VW  
ORDERING INFORMATION  
Temperature  
Package  
Device  
Range (T )  
A
MC33385DH/R2  
MC33385VW/R2  
-40°C to 125°C  
20 HSOP  
V
PWR  
33385  
Voltage  
Regulator  
OUT1  
VCC  
OUT2  
OUT3  
OUT4  
NCS  
CLK  
GND1-4  
SDI  
SDO  
MCU  
NRE  
NON1  
NON2  
NON3  
NON4  
Figure 1. MC33385 Simplified Application Diagram  
There are no disclaimers required on the Final publication of a data sheet.  
© Freescale Semiconductor, Inc., 2007. All rights reserved.  
BLOCK DIAGRAM  
BLOCK DIAGRAM  
VCC  
Charge Pump  
TRIGGER  
NON1  
NON2  
NON3  
NON4  
OUT1  
OUT2  
S
URES  
RES  
dv/dt control  
DRIVER  
OUT3  
OUT4  
R
RES  
Over-temp. detection  
URES  
ON1  
FR Reset  
IRES  
VCC  
I-SCB filter  
t-ISCB  
ON1  
SDI  
VCC  
I-OL filter  
t-IOL  
CLK  
VCC  
NON1  
SCG filter  
t-SCG  
Failure  
Register  
(FR)  
Shift  
Register  
V
ref  
NCS  
SDO  
URES  
RES  
OSC  
IRES  
Under Voltage  
Reset  
Reset  
Oscillator  
GND  
NRES  
Figure 2. 33385 Simplified Internal Block Diagram  
33385  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
2
PIN CONNECTIONS  
PIN CONNECTIONS  
21  
1
2
GND2  
OUT2  
N.C  
20 GND1  
19  
18  
17  
16  
OUT1  
N.C  
3
4
NON2  
NON1  
SDO  
5
SDI  
CLK  
Heat sink  
6
5
1
NRES  
VCC  
NCS  
7
14  
NON4  
OUT4  
GND4  
3
NON3  
8
1
9
12 OUT3  
11  
10  
GND3  
21  
Figure 3. 33385 Pin Connections  
Table 1. 33385 Pin Definitions  
Pin Number  
Pin Name  
GND2  
Definition  
Ground 2  
1
2
OUT2  
Output Channel 2  
NC  
3
NON2  
SDI  
Input Control Signal for Channel 2  
Serial Data Input  
4
5
CLK  
Clock Line for Serial Interface  
Chip Select for Serial Interface  
Input Control Signal for Channel 4  
Output Channel 4  
6
NCS  
7
NON4  
OUT4  
GND4  
GND3  
OUT3  
NON3  
Vcc  
8
9
Ground 4  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Ground 3  
Output Channel 3  
Input Control Signal for Channel 3  
5V Power Supply  
NRES  
SDO  
Reset Input  
Data Output of Serial Interface  
Input Control Signal Channel 1  
NC  
NON1  
OUT1  
GND1  
Case  
Output Channel 1  
Ground 1  
Connected to the PCB Ground for Thermal Purposes  
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3
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
Table 2. Maximum Ratings  
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or  
permanent damage to the device.  
Ratings  
Symbol  
Value  
Unit  
ELECTRICAL RATINGS  
Voltage Range  
Vcc  
VOUT  
IOUTC  
IOUTP  
WOFF  
VIN  
7.0  
45  
V
V
A
Continuous Output Voltage (With no reverse current)  
Continuous Current  
2.5  
Peak Output Current  
ISCBMAX  
70  
A
mJ for 1ms  
Clamped Energy at the Switching OFF (See Figure 9)  
Input Voltage (Inputs)  
VCC + 0.3  
1.0  
V
mA  
V
Input Protection Diode Current  
IIN  
Input Voltage (Outputs)  
VO  
VCC + 0.3  
1.0  
Input Protection Diode Current  
IO  
mA  
THERMAL RATINGS  
Operating Junction Temperature  
Thermal Resistance : Junction-case (One power stage in use)  
TJ  
150  
4.5  
°C  
RTHJC  
RTHJA  
TPPRT  
kΩ  
Thermal Resistance : Junction-ambient (Device soldered on printed circuit board)  
50  
kΩ  
(2)  
Peak Package Reflow Temperature During Reflow (1)  
,
Note 2  
°C  
Notes  
1. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may  
cause malfunction or permanent damage to the device.  
2. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow  
Temperature and Moisture Sensitivity Levels (MSL),  
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.  
MC33xxxD enter 33xxx), and review parametrics.  
33385  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
4
ELECTRICAL CHARACTERISTICS  
STATIC CHARACTERISTICS  
STATIC CHARACTERISTICS  
Table 3. Static Electrical Characteristics  
Characteristics noted under conditions 7.0 V VSUP 18 V, -40°C TA 125°C, GND = 0 V unless otherwise noted. Typical  
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
SUPPLY VOLTAGE  
Supply Voltage Range  
JUNCTION TEMPERATURE  
VCC  
4.5  
5.5  
V
Junction Temperature Continuous (Continuous)  
Junction Temperature Dynamical (Time limited)  
OUTPUT CURRENT  
TJ1  
TJ2  
- 40  
150  
185  
°C  
°C  
Output Current Range  
IOUT  
ISCBMAX  
Α
RESET BEHAVIOUR  
Reset Changeable (at NRES-Pin)  
VCC  
VCCRES  
3.35  
5.5  
V
V
Undervoltage Reset (Independent of NRES)  
Active for VCC = 0V to VCCPRO  
VCCRES  
3.95  
UNDERVOLTAGE PROTECTION  
Protection active for VCC =0V to VCCPRO  
OVER TEMPERATURE  
VCCPRO  
1.5  
4.0  
V
Temperature Detection Threshold  
SUPPLY CURRENT  
TOFF  
155  
185  
°C  
Standby Current (without load) (NON1...NON4 = High Level)  
5.15V VCC  
5.5V VCC  
ICCSTB1  
ICCSTB2  
6.0  
7.0  
mA  
mA  
Operating Mode (For 5.15V VCC) (Iout 1...4) = 2A  
ICCOPM  
17  
mA  
ICC During Reverse Output Current  
ICC  
100  
50  
mA  
mA  
(IOUT = - 5A on one output)  
INPUTS (NONx, NCS, CLK, NRES, SDI)  
Low Threshold  
VINL  
VINH  
VHYST  
IIN  
-0.3  
0.7*VCC  
0.85  
0.2*VCC  
V
V
High Threshold  
VCC + 0.3  
Hysteresis  
V
Input Current (VIN = VCC  
)
10  
µA  
µA  
Input Current (VCC >VRES & 0V<VIN < 0.9*VCC  
SERIAL DATA OUTPUT  
)
IIN  
- 100  
VCC - 0.4  
- 10  
- 20  
High Output Level (ISDO = -2mA)  
Low Output Level (ISDO = 3.2mA)  
VSDOH  
VSDOL  
ISDOL  
V
V
0.4  
10  
Tristate Leakage Current (NCS = HIGH, VSDO = 0V to VCC  
OUTPUTS (OUT 1...4)  
)
µA  
Average Output Current  
IOUTA  
IOUTP  
2.5  
A
A
Output Peak Current  
ISCBMAX  
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5
ELECTRICAL CHARACTERISTICS  
STATIC CHARACTERISTICS  
Table 3. Static Electrical Characteristics (continued)  
Characteristics noted under conditions 7.0 V VSUP 18 V, -40°C TA 125°C, GND = 0 V unless otherwise noted. Typical  
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Leakage Current 1 (NON = High, VOUT = 25V, VCC = 5V)  
Leakage Current 2 (NON = High, VOUT = 16V, VCC = 1V)  
Output Clamp Voltage (IOUT = 1A)  
Symbol  
Min  
Typ  
Max  
Unit  
IOUTL  
IOUTL2  
VCLP  
10  
10  
µA  
µA  
45  
VCLP-1  
50  
50  
58  
V
Matching Clamp Voltage (Between two outputs)  
Clamped Energy at the Switching OFF (See Figure 9)  
On Resistance (IOUT = 2A, TJ = 150°C, NON = LOW)  
Output Low Voltage Limitation (IOUT = 150mA)  
Output Capacitance (Guaranteed by design)  
OUTPUTS REVERSE DIODE  
VCLPM  
WOFF  
VCLP+1  
V
mJ for 1ms  
mΩ  
RDSON  
VOUTLIM  
COUT  
500  
220  
350  
65  
mV  
pF  
Reverse Output Current  
IRD  
2,5  
5.0  
A
A
Reverse Peak current (1)  
IRDP  
Reverse Voltage Drop  
- IOUT = - 5A  
- IOUT = - 2,5A  
VRD1  
VRD2  
1.0  
1.7  
1.7  
V
V
0.85  
POWERSTAGE PROTECTION  
Short Current Limit  
ISCB  
3.0  
5
A
V
VCC Undervoltage  
VCCMIN  
3.35  
3.95  
DIAGNOSTIC  
Short to GND Threshold Voltage for IOUT 2A  
Open Load Threshold Current  
Pull-up Resistor  
VREF  
IOL  
0.390xVCC  
0.435xVCC  
V
10  
2.0  
155  
50  
8.0  
185  
mA  
kΩ  
°C  
ROL  
TOFF  
Temperature Detection Threshold  
Notes  
1. For t 2ms. Max. reverse current is limited to - 10A (for all outputs together)  
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ELECTRICAL CHARACTERISTICS  
DYNAMIC CHARACTERISTIC  
DYNAMIC CHARACTERISTIC  
Table 4. Dynamic Electrical Characteristics  
Characteristics noted under conditions 7.0 V VSUP 18 V, -40°C TA 125°C, GND = 0 V unless otherwise noted. Typical  
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
INPUTS  
Input Frequency (NON1 to NON4)  
OUTPUTS TIMING  
fIN  
0.0  
1000  
Hz  
Positive Output Voltage Ramp (with inductive load)  
VOUT = 4V... 16V  
VOUT = 16V... Vclp  
OVRP1  
OVRP2  
2.0  
3.5  
3.0  
6.0  
5.0  
10  
V/µs  
V/µs  
Negative Output Voltage Ramp (25%... 75%)  
Internal Switch-on-Time Charge Pump  
OVRN  
tDCP  
1.75  
3.0  
4.0  
40  
V/µs  
µs  
(NON = LOW... VGATE = 0.9 * VBAT  
)
Turn ON Delay  
tDON  
1.0  
2.5  
5.0  
µs  
(NON = 50%, VOUT = 0.9 * VBAT  
Turn OFF Delay  
)
)
(NON = 50%, VOUT = 0.1 * VBAT  
(NON = 50%, VOUT = 4V)  
tDOFFA  
tDOFFB  
1.0  
4.7  
3.0  
7.5  
µs  
µs  
Undervoltage Protection  
tRPON  
100  
µs  
Max ON time after a output voltage ramp from  
0V to 25V at VCC = 0V...VCCPRO  
Matching Turn ON Delay  
tMON  
- 3.0  
3.0  
12  
µs  
µs  
(NON = 50%, VOUT = 0.9 * VBAT  
)
Rise time Turn OFF  
tROFF  
8.5  
(10% - 90% of VCLP  
DIAGNOSTIC  
)
Short to GND Filter Time  
Open Load Filter Time  
TSCG  
tOL  
140  
140  
250  
250  
µs  
µs  
SERIAL DIAGNOSTIC LINK : LOAD CAPACITOR AT SDI AND SDO = 100PF  
Clock Frequency (50% duty cycle)  
fCLK  
tCLH  
3.0  
100  
100  
MHz  
ns  
Minimum Time CLK = HIGH  
Minimum Time CLK = LOW  
tCLL  
ns  
Propagation Delay (CLF Data at SDO valid)  
NCS = LOW to Data at SDO Valid  
tPCLD  
tPCLD  
tSCLCH  
100  
100  
ns  
ns  
CLK Low Before NCS Low  
100  
ns  
(Setup time CLK to NCS change High/Low)  
CLK Change Low/High after NCS = Low  
tHCLCL  
tSCLD  
100  
20  
ns  
ns  
SDI Input Set up Time  
(CLK change High/Low after SDI data valid)  
SDI Input Hold Time (SDI data hold after CLK change High/Low)  
CLK Low Before NCS High  
tHCLD  
20  
ns  
ns  
tSCLCL  
150  
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7
ELECTRICAL CHARACTERISTICS  
DYNAMIC CHARACTERISTIC  
Table 4. Dynamic Electrical Characteristics (continued)  
Characteristics noted under conditions 7.0 V VSUP 18 V, -40°C TA 125°C, GND = 0 V unless otherwise noted. Typical  
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
CLK High After NCS High  
tHCLCH  
tPCHDZ  
tPCLD  
150  
ns  
ns  
pF  
ns  
NCSLow/High to Output Data Flout  
100  
10  
Capacitance at SDI, SDO, CLk, CS  
NCS Filter time (Pulses tFNCS will be ignored)  
tFNCS  
10  
40  
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ELECTRICAL CHARACTERISTICS  
TIMING DIAGRAMS  
TIMING DIAGRAMS  
NCS  
CLK  
FSL  
LSB  
D1  
D2  
D3  
D4  
D5  
D6  
MSB  
SDO  
SDI  
LSB  
D1  
D2  
D3  
D4  
D5  
D6  
MSB  
FR-RESET  
NOTE : FR -RESET means Reset failure storage (internal signal)  
Figure 4. Timing Diagram to Read the Diagnostic Register  
MSB  
LSB  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
FSL  
FAILURE INDICATOR BIT  
Only valid during NCS = LOW to the first  
Low to High CLK change  
1 : failure stored  
0 : no failure  
STATUS CHANNEL 4  
11 : no failure  
01 : open circuit  
10: short to battery or overtemperature  
00 : short to gnd  
STATUS CHANNEL 3  
STATUS CHANNEL 2  
STATUS CHANNEL 1  
Figure 5. Diagnostic Failure Register Structure  
.
NCS  
CLK  
t
t
t
t
t
t
HCLCH  
SCLCH  
HCLCH  
CLH  
CLL  
SCLCH  
t
t
t
PCHDZ  
CSDV  
PCLD  
FSL  
D0  
D7  
SDO  
SDI  
t
HCLD  
t
CSDV  
D0  
D1  
D7  
Figure 6. Serial Interface Timing  
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ELECTRICAL CHARACTERISTICS  
TIMING DIAGRAMS  
Failure detection time  
for an SCG failure  
off  
NON  
on  
SCG-failure  
V
DRAIN  
V
< V  
at off-state  
DRAIN  
REF  
t-SCG (filter-time)  
Failure detection  
Filter time  
Failure store  
Figure 7. Diagram to Short-Circuit to GND Failure (SCG-Failure) Detection  
Sporadic failure detection  
Statical failure detection  
Failure detection active  
for an sporadic OL-failure  
off  
on  
NON  
Iload  
I-OL  
Iload > I-OL  
Iload > IOL for t > tol  
retrigger t filter  
Diagnostic active  
t-ol (filter-time)  
t < t-ol  
retrigger filter  
tol  
Sporadic failure-detection  
Failure detection  
Failure store  
Figure 8. Diagram to Open Load Failure (OL-Failure) Detection  
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10  
ELECTRICAL CHARACTERISTICS  
ELECTRICAL PERFORMANCE CURVES  
350  
300  
- 40°C  
250  
200  
150  
100  
50  
25°C  
125°C  
0
0
0,5  
1
1,5  
2
2,5  
3
3,5  
4
Pulse-Duration (ms)  
Figure 9. Max Clamp- Energy Specification  
ELECTRICAL PERFORMANCE CURVES  
380  
3
375  
370  
2,75  
2,50  
V
CC=5,5V  
CC=4,5V  
365  
2,25  
2
360  
355  
VCC=5,5V  
V
1,75  
350  
345  
340  
V
CC=5,15V  
1,50  
1,25  
1
-50  
-25  
0
25  
50  
75  
C)  
100 125  
-50  
-25  
0
25  
50  
75  
C)  
100 125  
T, TEMPERATURE (  
°
T, TEMPERATURE (  
°
Figure 12. Low Threshold Input Voltage versus  
Temperature  
Figure 10. Standby Current versus Temperature  
12,50  
624  
12,00  
11,50  
623  
622  
11,00  
10,50  
621  
VCC=4,5V ou 5,5V  
620  
619  
10,00  
9,50  
9,00  
8,50  
618  
617  
616  
V
CC=5,15V  
All outputs=2A  
-50  
-25 25  
0
50  
75  
C)  
100 125  
-50  
-25  
0
25  
50  
75  
C)  
100 125  
T, TEMPERATURE (  
°
T, TEMPERATURE (  
°
Figure 11. Operating Mode Current versus Temperature  
Figure 13. High Threshold Input Voltage versus  
Temperature  
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ELECTRICAL CHARACTERISTICS  
ELECTRICAL PERFORMANCE CURVES  
55,00  
3,78  
54,50  
54,00  
3,77  
3,76  
53,50  
53,00  
3,75  
3,74  
IOUT1=1A  
52,50  
3,73  
52,00  
51,50  
51,00  
3,72  
3,71  
3,70  
-50  
-25  
0
25  
50  
75  
C)  
100 125  
-50  
-25  
0
25  
50  
75  
C)  
100 125  
T, TEMPERATURE (  
°
T, TEMPERATURE (  
°
Figure 14. Output Clamp Voltage versus Temperature  
Figure 17. Vcc Undervoltage versus Temperature  
400  
4,60  
4,50  
V
CC=4,5V  
375  
350  
IOUT1=3A  
VCC=5,5V  
4,40  
4,30  
4,20  
325  
300  
4,10  
4,00  
275  
250  
225  
200  
VCC=4,5V  
3,90  
3,80  
-50  
-25  
0
25  
50  
75  
C)  
100 125  
-50  
-25  
0
25  
50  
75  
C)  
100 125  
T, TEMPERATURE (  
°
T, TEMPERATURE (  
°
Figure 18. Short Current Limit versus Temperature  
Figure 15. Rdson versus Temperature  
24,50  
24,25  
24,00  
23,75  
23,50  
23,25  
23,00  
22,75  
22,50  
-50  
-25  
0
25  
50  
75  
C)  
100 125  
T, TEMPERATURE (  
°
Figure 16. Open Load versus Temperature  
Figure 19. Inductive Switching  
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ELECTRICAL CHARACTERISTICS  
ELECTRICAL PERFORMANCE CURVES  
In1 (1V/div)  
V
(2V/div)  
OUT1  
V
(2V/div)  
t
OUT1  
DON  
t
DOFFA  
t
DOFFB  
In1 (1V/div)  
Figure 20. Turn on Delay  
Figure 21. Turn off Delay  
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FUNCTIONAL DESCRIPTION  
INTRODUCTION  
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
The device is a Quad Low-side Driver driven by four  
CMOS input stages. Each output power transistor is  
protected against short to VBAT by a zener clamp against  
overvoltage.  
If the current through the output stage is lower than the  
IOL-reference, after a filter time an OL failure will be  
recognized. This measurement is active while the power  
stage is switched on.  
A diagnostic logic recognizes four failure types at the  
output stage : overcurrent, short to GND, open-load and  
overtemperature.  
The SCG failure will recognize when the drain voltage is  
lower than the OL reference limit, while the output stage is  
switched off. All four outputs have an independent  
overtemperature detection and shutdown. All failures are  
stored in individual registers.  
The failures are individually stored in a byte which can be  
read out via the serial interface (SPI).  
They can be read by the microprocessor via the serial  
interface. There is no failure detected if the power stage  
control time is shorter than the filter time.  
OUTPUT STAGE CONTROL  
Each of the four output stages is switched ON and OFF by  
an individual control line (NON-Input). The logic level of the  
control line is CMOS compatible. The output transistors are  
switched off when the inputs are not connected.  
DIAGNOSTIC INTERFACE  
The communication between the microprocessor and the  
failure register runs via the SPI link. If there is a failure stored  
in the failure register, the first bit of the shift register is set to  
a high level. With the High/Low change on the NCS pin, the  
first bit of the diagnostic shift register will be transmitted to the  
SDO output. The SDO output is the serial output from the  
diagnostic shift register and it is put into a tri-state when the  
NCS pin is high. The CLK pin clocks the diagnostic shift  
register. New SDO data will appear on every rising edge of  
this pin and new SDI data will be latched on every CLK’s  
falling edge into the shift register. With the first positive pulse  
of the CLK, the failure register will be cleared. There is no bus  
collision at a small spike at the NCS. The CLK is always LOW  
while the NCS-signal is changing.  
POWER TRANSISTORS  
Each of the four output stages has its own zener clamp.  
This causes a voltage limitation at the power transistors when  
inductive loads are switched off. The drain voltage ramp  
occurring when output is switched on or off, is within defined  
limits. Output transistors can be connected in parallel to  
increase current capability. In this case, the associated inputs  
should be connected together.  
SHORT-CIRCUIT AND OVERTEMPERATURE  
PROTECTION  
If the output current increases above the short current limit  
for a time longer than tSCB or if the temperature increases  
above TOFF then the power transistor is immediately  
switched off. It remains switched off until the control signal on  
the NON-Input is switched off and on again.  
RESET  
There are two different reset functions realized :  
Under voltage reset : as long as the VCC voltage is lower  
than VCCRES, the power stages are switched off and the  
failure-registers are reset.  
DIAGNOSTICS  
Reset pin : as long as the NRES-pin is low, following  
circuits are reset :  
The following failures at the output stage are recognized :  
Short -Circuit to VBAT or overtemp = SCB (Highest priority)  
Short -Circuit to GND.................... = SCG  
• Power stages  
• Failure register  
Open Load...................................... = OL (Lowest priority)  
The SCB failure is recognized by an overcurrent (current  
above the short current limit) or an overtemperature.  
UNDERVOLTAGE PROTECTION  
At low VCC voltage, the device remains switched off even  
if there is a voltage ramp at the OUT pin.  
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REVISION HISTORY  
REVISION HISTORY  
REVISION  
DATE  
DESCRIPTION OF CHANGES  
Implemented Revision History page  
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11/2006  
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MC33385  
Rev. 6.0  
11/2006  

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