K70P256M150SF3 [FREESCALE]
K70 Sub-Family Data Sheet; K70次系列数据手册
| 型号： | K70P256M150SF3 |
| 厂家： | 
Freescale |
| 描述： | K70 Sub-Family Data Sheet |
| 文件： | 总92页 (文件大小：1313K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: K70P256M150SF3
Rev. 3, 2/2012
Freescale Semiconductor
Data Sheet: Advance Information
K70P256M150SF3
K70 Sub-Family Data Sheet
Supports the following:
MK70FX512VMJ15,
MK70FN1M0VMJ15
Features
Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
•
Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
•
•
•
– Tamper detect and secure storage
– Hardware random-number generator
– Hardware encryption supporting DES, 3DES, AES,
MD5, SHA-1, and SHA-256 algorithms
– 128-bit unique identification (ID) number per chip
Performance
– Up to 150 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
Human-machine interface
– Graphic LCD controller
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
•
•
Memories and memory interfaces
– Up to 1024 KB program flash memory on non-
FlexMemory devices
– Up to 512 KB program flash memory on
FlexMemory devices
Analog modules
– Four 16-bit SAR ADCs
– Up to 512 KB FlexNVM on FlexMemory devices
– 16 KB FlexRAM on FlexMemory devices
– Up to 128 KB RAM
– Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
– Two 12-bit DACs
– Serial programming interface (EzPort)
– FlexBus external bus interface
– DDR controller interface
– Four analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
– NAND flash controller interface
Timers
•
Clocks
– Programmable delay block
– Two 8-channel motor control/general purpose/PWM
timers
– Two 2-channel quadrature decoder/general purpose
timers
•
•
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
System peripherals
– IEEE 1588 timers
– 10 low-power modes to provide power optimization
based on application requirements
– Memory protection unit with multi-master
protection
– 32-channel DMA controller, supporting up to 128
request sources
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
This document contains information on a new product. Specifications and
information herein are subject to change without notice.
© 2012 Freescale Semiconductor, Inc.
Preliminary
Communication interfaces
•
– Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability
– USB high-/full-/low-speed On-the-Go controller with ULPI interface
– USB full-/low-speed On-the-Go controller with on-chip transceiver
– Two Controller Area Network (CAN) modules
– Three SPI modules
– Two I2C modules
– Six UART modules
– Secure Digital host controller (SDHC)
– Two I2S modules
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
2
Freescale Semiconductor, Inc.
Preliminary
Table of Contents
1 Ordering parts...........................................................................5
5.4.2
Thermal attributes...............................................26
1.1 Determining valid orderable parts......................................5
2 Part identification......................................................................5
2.1 Description.........................................................................5
2.2 Format...............................................................................5
2.3 Fields.................................................................................5
2.4 Example............................................................................6
3 Terminology and guidelines......................................................6
3.1 Definition: Operating requirement......................................6
3.2 Definition: Operating behavior...........................................6
3.3 Definition: Attribute............................................................7
3.4 Definition: Rating...............................................................7
3.5 Result of exceeding a rating..............................................8
3.6 Relationship between ratings and operating
6 Peripheral operating requirements and behaviors....................27
6.1 Core modules....................................................................27
6.1.1
6.1.2
Debug trace timing specifications.......................27
JTAG electricals..................................................27
6.2 System modules................................................................30
6.3 Clock modules...................................................................30
6.3.1
6.3.2
6.3.3
MCG specifications.............................................30
Oscillator electrical specifications.......................32
32kHz Oscillator Electrical Characteristics.........34
6.4 Memories and memory interfaces.....................................35
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
Flash (FTFE) electrical specifications.................35
EzPort Switching Specifications.........................38
NFC specifications..............................................39
DDR controller specifications..............................42
Flexbus Switching Specifications........................45
requirements......................................................................8
3.7 Guidelines for ratings and operating requirements............8
3.8 Definition: Typical value.....................................................9
3.9 Typical value conditions....................................................10
4 Ratings......................................................................................10
4.1 Thermal handling ratings...................................................10
4.2 Moisture handling ratings..................................................11
4.3 ESD handling ratings.........................................................11
4.4 Voltage and current operating ratings...............................11
5 General.....................................................................................12
5.1 AC electrical characteristics..............................................12
5.2 Nonswitching electrical specifications...............................13
6.5 Security and integrity modules..........................................48
6.5.1 DryIce Tamper Electrical Specifications.............48
6.6 Analog...............................................................................49
6.6.1
6.6.2
6.6.3
6.6.4
ADC electrical specifications..............................50
CMP and 6-bit DAC electrical specifications......58
12-bit DAC electrical characteristics...................60
Voltage reference electrical specifications..........63
6.7 Timers................................................................................64
6.8 Communication interfaces.................................................64
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
6.8.7
Ethernet switching specifications........................64
USB electrical specifications...............................66
USB DCD electrical specifications......................66
USB VREG electrical specifications...................67
ULPI timing specifications...................................67
CAN switching specifications..............................68
DSPI switching specifications (limited voltage
range).................................................................69
DSPI switching specifications (full voltage
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
Voltage and current operating requirements......13
LVD and POR operating requirements...............15
Voltage and current operating behaviors............16
Power mode transition operating behaviors.......18
Power consumption operating behaviors............19
EMC radiated emissions operating behaviors....22
Designing with radiated emissions in mind.........23
Capacitance attributes........................................23
6.8.8
6.8.9
5.3 Switching specifications.....................................................23
range).................................................................70
I2C switching specifications................................72
5.3.1
5.3.2
Device clock specifications.................................23
General switching specifications.........................24
6.8.10 UART switching specifications............................72
6.8.11 SDHC specifications...........................................72
6.8.12 I2S/SAI Switching Specifications........................73
5.4 Thermal specifications.......................................................25
5.4.1 Thermal operating requirements.........................25
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
3
Preliminary
6.9 Human-machine interfaces (HMI)......................................75
8 Pinout........................................................................................79
8.1 K70 Signal Multiplexing and Pin Assignments..................79
8.2 K70 Pinouts.......................................................................89
9 Revision History........................................................................90
6.9.1
6.9.2
TSI electrical specifications................................75
LCDC electrical specifications............................76
7 Dimensions...............................................................................79
7.1 Obtaining package dimensions.........................................79
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
4
Freescale Semiconductor, Inc.
Preliminary
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to http://www.freescale.com and perform a part number
search for the following device numbers: PK70 and MK70.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
A
Kinetis family
Key attribute
• K70
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
5
Terminology and guidelines
Field
Description
Values
FFF
Program flash memory size
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
CC
N
Package identifier
• MJ = 256 MAPBGA (17 mm x 17 mm)
• 15 = 150 MHz
Maximum CPU frequency (MHz)
Packaging type
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK70FN1M0VMJ15
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
6
Freescale Semiconductor, Inc.
Terminology and guidelines
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
7
Preliminary
Terminology and guidelines
3.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
3.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
3.6 Relationship between ratings and operating requirements
Fatal
range
Normal
operating
range
Fatal
range
- Probable permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- Probable permanent failure
Handling range
- No permanent failure
–∞
∞
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
8
Freescale Semiconductor, Inc.
Preliminary
Terminology and guidelines
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
9
Preliminary
Ratings
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
TJ
150 °C
105 °C
25 °C
–40 °C
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
V
VDD
3.3 V supply voltage
3.3
4 Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
10
Freescale Semiconductor, Inc.
Preliminary
Ratings
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
ILAT
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 105°C
-500
-100
+500
+100
V
2
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage1
–0.3
3.8
V
VDD_INT
VDD_DDR
IDD
Core supply voltage
DDR I/O supply voltage
Digital supply current
Core supply current
DDR supply current
–0.3
–0.3
—
3.8
3.8
V
V
300
185
220
5.5
mA
mA
mA
V
IDD_INT
IDD_DDR
VDIO
—
—
Digital input voltage (except RESET, EXTAL0/XTAL0, and
EXTAL1/XTAL1) 2
–0.3
VDTamper
VDDDR
Tamper input voltage
DDR input voltage
–0.3
–0.3
VBAT + 0.3
V
V
VDD_DDR
0.3
+
Analog3, RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1 input
voltage
VAIO
–0.3
VDD + 0.3
V
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
11
General
Symbol
Description
Min.
Max.
Unit
ID
Instantaneous maximum current single pin limit (applies to all
digital pins except Tamper and DDR pins)
–25
25
mA
ID_DDR
Instananeous maximum current single pin limit (applies to
DDR pins)
TBD
TBD
TBD
TBD
mA
mA
ID_Tamper
Instananeous maximum current single pin limit (applies to
Tamper pins)
VDDA
VUSB_DP
VUSB_DM
VREGIN
VBAT
Analog supply voltage
USB_DP input voltage
USB_DM input voltage
USB regulator input
VDD – 0.3
–0.3
VDD + 0.3
3.63
V
V
V
V
V
–0.3
3.63
–0.3
6.0
RTC battery supply voltage
–0.3
3.8
1. It applies for all port pins except Tamper pins.
2. It covers digital pins except Tamper pins and DDR pins.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
12
Freescale Semiconductor, Inc.
Preliminary
General
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDD
Supply voltage
max(VDD_DD
R,1.71)
3.6
V
VDD_INT
Core supply voltage
1.71
VDD
V
VDD_DDR
DDR voltage — memory I/O buffers
• DDR1
2.3
1.7
2.7
1.9
V
V
• DDR2/LPDDR
VREF_DDR Input reference voltage (DDR1/DDR2)
0.49 ×
0.51 ×
V
VDD_DDR
VDD_DDR
VDDA
Analog supply voltage
1.71
–0.1
–0.1
1.71
3.6
0.1
0.1
3.6
V
V
V
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
VBAT
VIH
RTC battery supply voltage
Input high voltage (digital pins except Tamper pins
and DDR pins)
0.7 × VDD
—
—
V
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
VIL
Input low voltage (digital pins except Tamper pins and
DDR pins)
—
—
0.35 × VDD
0.3 × VDD
V
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
VIH_DDR
Input high voltage (DDR pins)
VREF_DDR
0.15
+
+
—
—
—
V
V
V
• DDR1
• DDR2
• LPDDR
VREF_DDR
0.125
0.7 ×
VDD_DDR
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
13
General
Table 1. Voltage and current operating requirements (continued)
Symbol
VIL_DDR
Description
Min.
Max.
Unit
Notes
Input low voltage (DDR pins)
—
—
—
VREF_DDR
0.15
–
–
V
V
V
• DDR1
• DDR2
• LPDDR
VREF_DDR
0.125
0.3 ×
VDD_DDR
VIH_Tamper Tamper input high voltage
• 2.7 V ≤ VBAT ≤ 3.6 V
0.7 × VBAT
—
—
V
V
0.75 × VBAT
• 1.7 V ≤ VBAT ≤ 2.7 V
VIL_Tamper Tamper input low voltage
• 2.7 V ≤ VBAT ≤ 3.6 V
—
—
0.35 × VBAT
0.3 × VBAT
V
V
• 1.7 V ≤ VBAT ≤ 2.7 V
VHYS
Input hysteresis (digital pins except Tamper pins and
DDR pins)
0.06 × VDD
0.06 × VBAT
-5
—
—
—
V
V
VHYS_Tamper Input hysteresis (Tamper pins)
IICDIO Digital pin (except Tamper pins and DDR pins)
1
mA
negative DC injection current — single pin
• VIN < VSS-0.3V
IICDIO_DDR DDR pin negative DC injection current -- single pin
TBD
TBD
mA
• TBD
IICDIO_Tamper Tamper pin negative DC injection current — single pin
-0.2
—
—
mA
mA
• VIN < VSS-0.3V
• VIN > VBAT
2.0
Analog2, EXTAL0/XTAL0, and EXTAL1/XTAL1 pin DC
injection current — single pin
IICAIO
3
mA
-5
—
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
—
+5
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
-25
—
—
mA
• Negative current injection
• Positive current injection
+25
VRAM
VDD (VDD_INT) voltage required to retain RAM
1.2
—
—
V
V
VRFVBAT
VBAT voltage required to retain the VBAT register file
VPOR_VBAT
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection
to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
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Freescale Semiconductor, Inc.
Preliminary
General
the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current
limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN
(=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting
resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC
injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is
calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.
5.2.2 LVD and POR operating requirements
Table 2. LVD and POR operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period
factory trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
15
General
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
Output high current total for all ports
—
—
100
100
mA
mA
IOHT_io60
VOH_DDR
Output high current total for fast digital ports
Output high voltage for DDR pins
• DDR1 (IOH = -16.2 mA)
VDD_DDR
0.36
-
-
-
—
—
—
—
—
V
V
V
V
V
• DDR2 half strength (IOH = TBD mA)
• DDR2 full strength (IOH = -13.4 mA)
• LPDDR half strength (IOH = -0.1 mA)
• LPDDR full strength (IOH = -0.1 mA)
VDD_DDR
0.28
VDD_DDR
0.28
0.9 x
VDD_DDR
0.9 x
VDD_DDR
IOHT_DDR
Output high current total for DDR pins
—
TBD
mA
• DDR1
• DDR2
• LPDDR
VOH_Tamper Output high voltage — high drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -10mA
VBAT – 0.5
VBAT – 0.5
—
—
V
V
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -3mA
Output high voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -0.6mA
VBAT – 0.5
VBAT – 0.5
—
—
V
V
IOH_Tamper Output high current total for Tamper pins
—
TBD
mA
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
16
Freescale Semiconductor, Inc.
General
Notes
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
VOL
Output low voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
—
0.5
0.5
V
V
IOLT
Output low current total for all ports
—
—
TBD
TBD
mA
mA
IOLT_io60
VOL_DDR
Output low current total for fast digital ports
Output low voltage for DDR pins
• DDR1 (IOL = 16.2 mA)
—
—
—
—
—
0.37
0.28
0.28
V
V
V
V
V
• DDR2 half strength (IOL = TBD mA)
• DDR2 full strength (IOL = 13.4 mA)
• LPDDR half strength (IOL = 0.1 mA)
• LPDDR full strength (IOL = 0.1 mA)
0.1 x
VDD_DDR
0.1 x
VDD_DDR
IOLT_DDR
Output low current total for DDR pins
—
TBD
mA
• DDR1
• DDR2
• LPDDR
VOL_Tamper Output low voltage — high drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 10mA
—
—
0.5
0.5
V
V
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 3mA
Output low voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 0.6mA
—
—
0.5
0.5
V
V
IOL_Tamper Output low current total for Tamper pins
—
—
TBD
1
mA
μA
IIN
Input leakage current (per pin) for full temperature
range
1
1
IIN
Input leakage current (per pin) at 25°C
—
—
0.025
1
μA
μA
IIN_DDR
Input leakage current (per DDR pin) for full
temperature range
IIN_DDR
Input leakage current (per DDR pin) at 25°C
—
—
0.025
TBD
μA
μA
IIN_Tamper Input leakage current (per Tamper pin) for full
temperature range
IIN_Tamper Input leakage current (per Tamper pin) at 25°C
—
0.025
μA
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
17
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
Notes
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
IOZ_DDR
Hi-Z (off-state) leakage current (per DDR pin)
—
—
20
20
20
20
1
μA
μA
kΩ
kΩ
kΩ
kΩ
IOZ_Tamper Hi-Z (off-state) leakage current (per Tamper pin)
1
RPU
RPD
Internal pullup resistors
50
50
50
50
2
3
Internal pulldown resistors
RPU_Tamper Internal pullup resistors (per Tamper pin)
RPD_Tamper Internal pulldown resistors (per Tamper pin)
RODT
On-die termination (ODT) resistance for DDR2
60
90
Ω
Ω
• Rtt1(eff) - 75 Ω
• Rtt2(eff) - 150 Ω
120
180
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 150 MHz
• Bus clock = 75 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
—
300
μs
1
—
—
—
—
126
82
μs
μs
μs
μs
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
82
5.0
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
18
Freescale Semiconductor, Inc.
General
Notes
Table 5. Power mode transition operating behaviors (continued)
Symbol
Description
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFE_FOPT[LPBOOT]=1)
Min.
Max.
Unit
—
TBD
μs
—
TBD
μs
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
2
—
—
65
65
TBD
TBD
mA
mA
• @ 1.8V
• @ 3.0V
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
3
—
—
95
95
TBD
TBD
mA
mA
• @ 1.8V
• @ 3.0V
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
—
37
21
TBD
TBD
mA
mA
2
4
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
• @ 70°C
• @ 105°C
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
—
—
2.3
3.1
1.8
TBD
TBD
TBD
mA
mA
mA
5
6
7
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
IDD_VLPW Very-low-power wait mode current at 3.0 V
IDD_VLPS Very-low-power stop mode current at 3.0 V
—
—
—
200
TBD
TBD
TBD
TBD
TBD
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
• @ 105°C
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
19
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_LLS
Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
—
—
—
200
TBD
TBD
TBD
TBD
TBD
μA
μA
μA
• @ 70°C
• @ 105°C
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
—
—
—
6.5
37.4
148.3
TBD
TBD
TBD
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
—
—
—
3.4
TBD
TBD
TBD
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
13.4
58.5
• @ 105°C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
—
—
—
2.9
9.8
TBD
TBD
TBD
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
44.7
• @ 105°C
IDD_VBAT Average current when CPU is not accessing
RTC registers at 3.0 V
8
—
—
—
0.91
1.5
1.1
1.85
4.3
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
4.3
• @ 105°C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
3. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled, but peripherals are not in active operation.
4. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode.
5. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
6. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
7. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
8. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
20
Freescale Semiconductor, Inc.
Preliminary
General
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies. MCG in PEE mode is greater than 100 MHz frequencies.
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL
Figure 2. Run mode supply current vs. core frequency
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
21
Preliminary
General
Figure 3. VLPR mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 256MAPBGA
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
1, 2
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
TBD
TBD
TBD
TBD
K
dBμV
dBμV
dBμV
dBμV
—
VRE3
150–500
500–1000
0.15–1000
VRE4
2, 3
VRE_IEC
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
22
Freescale Semiconductor, Inc.
Preliminary
General
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to http://www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
—
7
9
pF
pF
CIN_D_io60
Input capacitance: fast digital pins
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
150
—
MHz
MHz
fSYS_USBFS
System and core clock when Full Speed USB in
operation
20
fSYS_USBHS
System and core clock when High Speed USB in
operation
60
—
MHz
MHz
fENET
System and core clock when ethernet in operation
• 10 Mbps
• 100 Mbps
5
—
—
75
50
—
fBUS
Bus clock
MHz
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
23
General
Table 9. Device clock specifications (continued)
Symbol
Description
FlexBus clock
Flash clock
Min.
—
Max.
50
Unit
MHz
MHz
Notes
FB_CLK
fFLASH
fDDR
—
25
DDR clock
—
—
150
25
MHz
MHz
fLPTMR
LPTMR clock
VLPR mode1
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
—
4
4
4
1
4
MHz
MHz
MHz
MHz
MHz
FB_CLK
fFLASH
fLPTMR
FlexBus clock
Flash clock
LPTMR clock
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, IEEE 1588 timer, and I2C signals.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
16
—
—
ns
ns
ns
2
2
2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
100
2
—
—
Mode select (EZP_CS) hold time after reset
deassertion
Bus clock
cycles
tio50
Port rise and fall time (high drive strength)
• Slew disabled
—
—
TBD
TBD
ns
ns
3
4
• Slew enabled
tio50
Port rise and fall time (low drive strength)
• Slew disabled
—
—
TBD
TBD
ns
ns
3
4
• Slew enabled
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
24
Freescale Semiconductor, Inc.
General
Table 10. General switching specifications (continued)
Symbol
Description
Min.
—
Max.
TBD
TBD
Unit
ns
Notes
tio60
Port rise and fall time (high drive strength)
• Slew disabled
3
4
—
ns
• Slew enabled
tio60
ttamper
ttamper
tddr
Port rise and fall time (low drive strength)
• Slew disabled
—
—
TBD
TBD
ns
ns
3
4
• Slew enabled
Port rise and fall time (high drive strength)
• Slew disabled
—
—
TBD
TBD
ns
ns
5
6
• Slew enabled
Port rise and fall time (low drive strength)
• Slew disabled
—
—
TBD
TBD
ns
ns
7
8
• Slew enabled
Port rise time
• DDR1
—
—
—
TBD
TBD
TBD
ns
ns
ns
9
10
11
• DDR2
• LPDDR
tddr
Port fall time
• DDR1
—
—
—
TBD
TBD
TBD
ns
ns
ns
9
10
11
• DDR2
• LPDDR
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 25pF load
4. 15pF load
5. 75pF load
6. 15pF load
7. 75pF load
8. 15pF load
9. DDR —rise and fall times at 50 Ω transmission line impedance terminated to 0.5 × VDD_DDR + 5 pF load.
10. Rising slew rate measured between 0.5 × VDD_DDR and 0.5 × VDD_DDR + 250 mV for all modes.
11. Falling slew rate measured between 0.5 × VDD_DDR and 0.5 × VDD_DDR – 250 mV for all modes.
5.4 Thermal specifications
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
25
Preliminary
General
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
5.4.2 Thermal attributes
Board type
Symbol
Description
256 MAPBGA
Unit
Notes
Single-layer (1s)
RθJA
Thermal
43
°C/W
1, 2
resistance, junction
to ambient (natural
convection)
Four-layer (2s2p)
Single-layer (1s)
Four-layer (2s2p)
RθJA
Thermal
28
36
25
°C/W
°C/W
°C/W
1,2, 3
1,3
resistance, junction
to ambient (natural
convection)
RθJMA
Thermal
resistance, junction
to ambient (200 ft./
min. air speed)
RθJMA
Thermal
1,3
resistance, junction
to ambient (200 ft./
min. air speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal
resistance, junction
to board
17
8
°C/W
°C/W
°C/W
4
5
6
Thermal
resistance, junction
to case
Thermal
2
characterization
parameter, junction
to package top
outside center
(natural
convection)
1.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2.
3.
4.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air) with the single layer board horizontal. Board meets JESD51-9 specification.
Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
26
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
5.
6.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Twh
Tr
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
2
2
—
—
3
ns
ns
ns
ns
ns
ns
—
—
3
Tf
3
Ts
—
—
Th
Data hold
2
Figure 4. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 5. Trace data specifications
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
6.1.2 JTAG electricals
Table 13. JTAG voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
TCLK frequency of operation
• JTAG
2.7
5.5
J1
MHz
—
—
10
5
• CJTAG
J2
J3
TCLK cycle period
TCLK clock pulse width
• JTAG
1/J1
—
ns
100
200
—
—
—
1
ns
ns
ns
ns
ns
• CJTAG
J4
J5
TCLK rise and fall times
—
TMS input data setup time to TCLK rise
—
53
112
8
• JTAG
• CJTAG
J6
J7
TDI input data setup time to TCLK rise
—
—
ns
ns
TMS input data hold time after TCLK rise
3.4
3.4
3.4
—
• JTAG
• CJTAG
J8
J9
TDI input data hold time after TCLK rise
—
ns
ns
TCLK low to TMS data valid
• JTAG
48
85
48
3
• CJTAG
J10
J11
TCLK low to TDO data valid
—
—
ns
ns
Output data hold/invalid time after clock edge1
1. They are common for JTAG and CJTAG.
J2
J4
J3
J3
TCLK (input)
J4
Figure 6. Test clock input timing
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 7. Boundary scan (JTAG) timing
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 8. Test Access Port timing
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
29
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 9. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 14. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
fints_t
Iints
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
Internal reference frequency (slow clock) — user
trimmed
31.25
—
39.0625
kHz
Internal reference (slow clock) current
—
—
TBD
0.3
—
µA
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.6
%fdco
1
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
0.2
0.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
10
—
—
%fdco
%fdco
1
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
4.5
fintf_ft
fintf_t
Iintf
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
4
5
MHz
MHz
µA
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
Internal reference (fast clock) current
—
TBD
—
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
30
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
FLL
ffll_ref
fdco
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
DCO output
Low range (DRS=00)
640 × ffll_ref
20.97
MHz
2, 3
frequency range
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
95.98
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
4, 5
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
FLL period jitter
—
—
180
150
—
—
• fVCO = 48 MHz
• fVCO = 98 MHz
Jacc_fll
FLL accumulated jitter of DCO output over a 1µs
time window
—
—
TBD
—
—
1
ps
tfll_acquire FLL target frequency acquisition time
ms
6
PLL0,1
fpll_ref
PLL reference frequency range
8
180
90
90
—
—
—
16
360
180
180
—
MHz
MHz
fvcoclk_2x VCO output frequency
fvcoclk
PLL output frequency
—
—
MHz
MHz
fvcoclk_90 PLL quadrature output frequency
Ipll
PLL operating current (fast)
7
TBD
µA
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
31
Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Ipll
PLL operating current (fast)
7
—
—
TBD
—
—
µA
s
100 × 10-6
+ 1075(1/
tpll_lock
Lock detector detection time
8
fpll_ref
TBD
TBD
)
Jcyc_pll
Jacc_pll
Jitter (cycle to cycle)
Jitter (accumulated)
—
—
50
ps
ps
500
9
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
9. Accumulated jitter will depend on VCO frequency and VDIV.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Table 15. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
32
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 15. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
25
400
500
2.5
3
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain mode
(HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
33
Preliminary
Peripheral operating requirements and behaviors
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2 Oscillator frequency specifications
Table 16. Oscillator frequency specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fosc_lo
Oscillator crystal or resonator frequency — low
32
—
40
kHz
frequency mode (MCG_C2[RANGE]=00)
fosc_hi_1
Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
3
8
—
—
8
MHz
MHz
1
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal
tdc_extal
tcst
Input clock frequency (external clock mode)
Input clock duty cycle (external clock mode)
—
40
—
—
50
60
60
—
MHz
%
2, 3
4, 5
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
1000
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
500
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Frequencies less than 8 MHz are not in the PLL range.
2. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
3. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it
remains within the limits of the DCO input clock frequency.
4. Proper PC board layout procedures must be followed to achieve specifications.
5. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
6.3.3 32kHz Oscillator Electrical Characteristics
This section describes the module electrical characteristics.
6.3.3.1 32kHz oscillator DC electrical specifications
Table 17. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
RF
Internal feedback resistor
—
100
—
MΩ
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
34
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 17. 32kHz oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Cpara
Parasitical capacitance of EXTAL32 and XTAL32
—
5
7
pF
1
Peak-to-peak amplitude of oscillation
—
0.6
—
V
Vpp
1. The EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to
any other devices.
6.3.3.2 32kHz oscillator frequency specifications
Table 18. 32kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
—
1
1. Proper PC board layout procedures must be followed to achieve specifications.
6.4 Memories and memory interfaces
6.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
6.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 19. NVM program/erase timing specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
thversscr
thversblk
Program Phrase high-voltage time
—
7.5
TBD
μs
Erase Flash Sector high-voltage time
Erase Flash Block high-voltage time
—
—
13
TBD
TBD
ms
ms
1
1
425
1. Maximum time based on expectations at cycling end-of-life.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
35
Peripheral operating requirements and behaviors
6.4.1.2 Flash timing specifications — commands
Table 20. Flash command timing specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
trd1blk
trd1sec4k
tpgmchk
trdrsrc
Read 1s Block execution time
—
1.5
TBD
ms
Read 1s Section execution time (4KB flash)
Program Check execution time
—
—
—
—
—
—
—
—
—
—
—
—
50
35
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
μs
μs
1
1
1
Read Resource execution time
35
μs
tpgm8
Program Phrase execution time
Erase Flash Block execution time
Erase Flash Sector execution time
65
μs
tersblk
450
15
ms
ms
ms
ms
μs
2
2
tersscr
tpgmsec4k Program Section execution time (4KB flash)
20
trd1all
Read 1s All Blocks execution time
Read Once execution time
1.5
17
trdonce
1
tpgmonce Program Once execution time
65
μs
tersall
Erase All Blocks execution time
900
25
ms
μs
2
1
tvfykey
Verify Backdoor Access Key execution time
Swap Control execution time
• control code 0x01
• control code 0x02
• control code 0x04
• control code 0x08
tswapx01
tswapx02
tswapx04
tswapx08
—
—
—
—
185
65
TBD
TBD
TBD
TBD
μs
μs
μs
μs
65
25
tpgmpart
Program Partition for EEPROM execution time
—
TBD
TBD
ms
Set FlexRAM Function execution time:
• 64 KB EEPROM backup
tsetram64k
tsetram128k
tsetram256k
tsetram512k
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ms
ms
ms
ms
• 128 KB EEPROM backup
• 256 KB EEPROM backup
• 512 KB EEPROM backup
teewr8bers Byte-write to erased FlexRAM location execution
time
—
100
TBD
μs
3
Byte-write to FlexRAM execution time:
teewr8b64k
teewr8b128k
teewr8b256k
teewr8b512k
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
• 512 KB EEPROM backup
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ms
ms
ms
ms
teewr16bers 16-bit write to erased FlexRAM location
execution time
—
100
TBD
μs
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
36
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 20. Flash command timing specifications (continued)
Symbol Description
16-bit write to FlexRAM execution time:
Min.
Typ.
Max.
Unit
Notes
teewr16b64k
teewr16b128k
teewr16b256k
teewr16b512k
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
• 512 KB EEPROM backup
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ms
ms
ms
ms
teewr32bers 32-bit write to erased FlexRAM location
execution time
—
200
TBD
μs
teewr32b64k 32-bit-write to FlexRAM execution time:
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
• 512 KB EEPROM backup
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ms
ms
ms
ms
teewr32b128k
teewr32b256k
teewr32b512k
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3 Flash (FTFE) current and power specfications
Table 21. Flash (FTFE) current and power specfications
Symbol
Description
Typ.
Unit
mA
IDD_PGM
Worst case programming current in program flash
10
6.4.1.4 Reliability specifications
Table 22. NVM reliability specifications
Typ.1
Symbol Description
Min.
Program Flash
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
tnvmretp100 Data retention after up to 100 cycles
nnvmcycp Cycling endurance
5
10
50
—
—
—
—
years
years
years
cycles
2
2
2
3
100
100
35 K
15
10 K
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k Data retention after up to 1 K cycles
tnvmretd100 Data retention after up to 100 cycles
nnvmcycd Cycling endurance
5
10
50
—
—
—
—
years
years
years
cycles
2
2
2
3
100
100
35 K
15
10 K
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
37
Peripheral operating requirements and behaviors
Table 22. NVM reliability specifications (continued)
Typ.1
Symbol Description
Min.
Max.
Unit
Notes
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
tnvmretee10 Data retention up to 10% of write endurance
tnvmretee1 Data retention up to 1% of write endurance
Write endurance
5
50
—
—
—
years
years
years
2
2
2
4
10
15
100
100
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree4k
nnvmwree32k
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 4096
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
—
—
—
—
writes
writes
writes
writes
writes
• EEPROM backup to FlexRAM ratio =
32,768
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C profile. Engineering Bulletin EB618 does not apply to this technology.
2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application).
3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
4. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling
endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and
typical values assume all byte-writes to FlexRAM.
6.4.1.5 Write endurance to FlexRAM for EEPROM
TBD
6.4.2 EzPort Switching Specifications
Table 23. EzPort switching specifications
Num
Description
Min.
1.71
—
Max.
3.6
Unit
V
Operating voltage
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
—
fSYS/8
—
MHz
ns
2 x tEZP_CK
5
5
—
ns
—
ns
2
—
ns
5
—
ns
—
16
ns
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
38
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 23. EzPort switching specifications (continued)
Num
EP8
EP9
Description
EZP_CK low to EZP_Q output invalid (hold)
Min.
Max.
Unit
ns
0
—
EZP_CS negation to EZP_Q tri-state
—
12
ns
EZP_CK
EZP_CS
EP3
EP4
EP2
EP9
EP8
EP7
EZP_Q (output)
EZP_D (input)
EP5
EP6
Figure 10. EzPort Timing Diagram
6.4.3 NFC specifications
The NAND flash controller (NFC) implements the interface to standard NAND flash
memory devices. This section describes the timing parameters of the NFC.
In the following table:
• TH is the flash clock high time and
• TL is flash clock low time,
which are defined as:
Tinput clock
TNFC = TL + TH
=
SCALER
The SCALER value is derived from the fractional divider specified in the SIM's
CLKDIV4 register:
SIM_CLKDIV4[NFCFRAC] + 1
SIM_CLKDIV4[NFCDIV] + 1
=
SCALER
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
39
Peripheral operating requirements and behaviors
In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%,
means TH = TL. In case the reciprocal of SCALER is not an integer:
TNFC
TL = (1 + SCALER / 2) x
2
TNFC
TH = (1 – SCALER / 2) x
2
For example, if SCALER is 0.2, then TH = TL = TNFC/2.
TNFC
TH TL
However, if SCALER is 0.667, then TL = 2/3 x TNFC and TH = 1/3 x TNFC
.
TNFC
TH TL
NOTE
The reciprocal of SCALER must be a multiple of 0.5. For
example, 1, 1.5, 2, 2.5, etc.
Table 24. NFC specifications
Num
Description
Min.
Max.
Unit
tCLS
NFC_CLE setup time
2TH + TL – 1
—
ns
tCLH
tCS
NFC_CLE hold time
NFC_CEn setup time
NFC_CEn hold time
NFC_WP pulse width
NFC_ALE setup time
NFC_ALE hold time
Data setup time
TH + TL – 1
2TH + TL – 1
TH + TL
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCH
tWP
tALS
tALH
tDS
TL – 1
2TH + TL
TH + TL
TL – 1
tDH
tWC
tWH
tRR
tRP
Data hold time
TH – 1
Write cycle time
TH + TL – 1
TH – 1
NFC_WE hold time
Ready to NFC_RE low
NFC_RE pulse width
4TH + 3TL + 90
TL + 1
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
40
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 24. NFC specifications (continued)
Num
Description
Min.
Max.
Unit
tRC
Read cycle time
TL + TH – 1
—
ns
tREH
tIS
NFC_RE high hold time
Data input setup time
TH – 1
11
—
—
ns
ns
NFC_CLE
tCLS
tCS
tCLH
tCH
NFC_CEn
NFC_WE
NFC_IOn
tWP
tDS
tDH
Figure 11. Command latch cycle timing
NFC_ALE
NFC_CEn
NFC_WE
NFC_IOn
tALS
tCS
tALH
tCH
tWP
tDS
tDH
address
Figure 12. Address latch cycle timing
tCS
tCH
tWC
NFC_CEn
NFC_WE
NFC_IOn
tWP
tDS
tWH
tDH
data
data
data
Figure 13. Write data latch cycle timing
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
41
Peripheral operating requirements and behaviors
tCH
tRC
tRP
NFC_CEn
tREH
NFC_RE
NFC_IOn
NFC_RB
tIS
data
data
data
tRR
Figure 14. Read data latch cycle timing in non-fast mode
tCH
tRC
tRP
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
tREH
tIS
data
data
data
tRR
Figure 15. Read data latch cycle timing in fast mode
6.4.4 DDR controller specifications
The following timing numbers must be followed to properly latch or drive data onto the
DDR memory bus. All timing numbers are relative to the DQS byte lanes.
Table 25. DDR controller — AC timing specifications
Symbol
Description
Frequency of operation
• DDR1
Min.
Max.
Unit
Notes
2
83.3
1251
50
150
150
150
MHz
MHz
MHz
• DDR2
• LPDDR
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
42
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 25. DDR controller — AC timing specifications (continued)
Symbol
Description
Clock period
• DDR1
Min.
Max.
Unit
Notes
tDDRCK
6.6
6.6
6.6
12
8
ns
ns
ns
• DDR2
• LPDDR
20
VOX-AC
DDRCK AC differential cross point voltage
0.5 x VDD_DDR 0.5 x VDD_DDR
– 0.2 V + 0.2 V
0.5 x VDD_DDR 0.5 x VDD_DDR
– 0.125 V + 0.125 V
0.4 x VDD_DDR 0.4 x VDD_DDR
V
V
V
• DDR1
• DDR2
• LPDDR
tDDRCKH
tDDRCKL
tCMV
Pulse width high
Pulse width low
0.45
0.45
0.55
0.55
—
tDDRCK
tDDRCK
ns
3
3
4
Address, DDR_CKE, DDR_CAS, DDR_RAS,
DDR_WE, DDR_CSn — output valid
0.5 x tDDRCK
1
–
–
tCMH
tDQSS
tQS
Address, DDR_CKE, DDR_CAS, DDR_RAS,
DDR_WE, DDR_CSn — output hold
0.5 x tDDRCK
1
—
ns
ns
ns
ns
ns
Write command to first DQS latching transition
WL – 0.2 x
tDDRCK
WL + 0.2 x
tDDRCK
Data and data mask output setup (DQ→DQS)
relative to DQS (DDR write mode)
0.25 x tDDRCK
– 1
—
5, 6
7
tQH
Data and data mask output hold (DQS→DQ)
relative to DQS (DDR write mode)
0.25 x tDDRCK
– 1
—
tDQSQ
DQS-DQ skew for DQS and associated DQ
signals
– (0.25 x
tDDRCK – 1)
0.25 x tDDRCK
– 1
8
1. This is minimum frequency of operation according to JEDEC DDR2 specification.
2. DDR data rate = 2 x DDR clock frequency
3. Pulse width high plus pulse width low cannot exceed min and max clock period.
4. Command output valid should be 1/2 the memory bus clock (tDDRCK) plus some minor adjustments for process,
temperature, and voltage variations.
5. This specification relates to the required input setup time of DDR memories. The microprocessor's output setup should be
larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation.
DDR_DQ[15:8] is relative to DDR_DQS[1]; DDR_DQ[7:0] is relative to DDR_DQS[0].
6. The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
are valid for each subsequent DQS edge.
7. This specification relates to the required hold time of DDR memories. DDR_DQ[15:8] is relative to DDR_DQS[1];
DDR_DQ[7:0] is relative to DDR_DQS[0]
8. Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or
other factors).
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
43
Preliminary
Peripheral operating requirements and behaviors
tDDRCKL
tDDRCKH
tDDRCK
DDR_CLK
DDR_CLK
tCMV
CMD
tCMH
DDR_CSn, DDR_WE
DDR_CAS, DDR_RAS
tDQSS
DDR_An
ROW
COL
tQS
DDR_DMn
DDR_DQSn
DDR_DQn
tQH
tQS
WD1 WD2 WD3 WD4
tQH
Figure 16. DDR write timing
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
44
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
tDDRCKH
tDDRCKL
tDDRCK
DDR_CLK
DDR_CLK
DDR_CSn, DDR_WE
DDR_CAS, DDR_RAS
DDR_An
CMD
tCMV
tCMH
ROW
COL
CL=2.5
DQS read
postamble
DQS read
preamble
DDR_DQS (CL=2.5)
DDR_DQn (CL=2.5)
DDR_DQS (CL=3)
DDR_DQn (CL=3)
RD1 RD2 RD3 RD4
CL=3
DQS read
preamble
DQS read
postamble
tIH
RD1 RD2 RD3 RD4
tIS
Figure 17. DDR read timing
Figure 18. DDR read timing, DQ vs. DQS
6.4.5 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
45
Preliminary
Peripheral operating requirements and behaviors
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 26. Flexbus limited voltage range switching specifications
Num
Description
Min.
2.7
—
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
20
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
—
11.5
—
ns
1
1
2
2
0.5
8.5
0.5
ns
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 27. Flexbus full voltage range switching specifications
Num
Description
Min.
1.71
—
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
1/FB_CLK
—
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
13.5
—
ns
1
1
2
2
0
ns
13.7
0.5
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
46
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB3
FB5
Address
FB4
FB2
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 19. FlexBus read timing diagram
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
47
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB2
FB3
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
Address
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 20. FlexBus write timing diagram
6.5 Security and integrity modules
6.5.1 DryIce Tamper Electrical Specifications
Table 28. DryIce Tamper Electrical Specifications
Symbol
Description
Min
Typ
Max
Unit
Notes
VBAT
3.3V supply voltage
1.71
3.6
V
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
48
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 28. DryIce Tamper Electrical Specifications (continued)
Symbol
Description
Supply current
• clock tamper enabled
Min
Typ
Max
Unit
Notes
ITAM
0.9
TBD
TBD
TBD
μA
μA
μA
• clock and voltage tamper enabled
1.01
1.35
• clock, voltage and temperature tamper enabled
EXTAL32 input clock
Low Voltage Detect
• assertion
32.768
kHz
1
1.55
1.7
1.60
1.75
1.65
1.8
V
V
• negation
High Voltage Detect assertion
Voltage Tamper Detect operational temperature
• no false alarms
3.65
3.7
3.75
V
-50
-60
150
160
°C
°C
• with possible false alarms
Temperature Tamper Detect assertion
• low temperature detect
2
-55
-45
°C
°C
• high temperature detect
110
130
Temperature Tamper Detect operational voltage
• no false alarms
1.6
3.7
V
V
• with possible false alarms
< 1.5
> 3.8
Clock Tamper Detect assertion
• low frequency
3
20
kHz
kHz
ms
• high frequency
40
• delay after loss of clock
2
Clock Tamper Detect operational temperature
• no false alarms
-50
-60
150
160
°C
• with possible false alarms
Clock Tamper Detect operational voltage
• no false alarms
1.6
3.7
V
V
• with possible false alarms
< 1.5
> 3.8
1. EXTAL32 oscillator must be enabled before enabling DryIce tamper detect.
2. Temperature tamper detector assertion/negation is refreshed each 28 EXTAL32 clock cycles.
3. Clock tamper detector assertion/negation is refreshed each 28 EXTAL32 clock cycles.
6.6 Analog
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
49
Preliminary
Peripheral operating requirements and behaviors
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 29 and Table 30 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are
not direct device pins. Accuracy specifications for these pins are defined in Table 31 and
Table 32.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1 16-bit ADC operating conditions
Table 29. 16-bit ADC operating conditions
Typ.1
Symbol Description
Conditions
Absolute
Min.
1.71
-100
Max.
3.6
Unit
V
Notes
VDDA
Supply voltage
Supply voltage
—
ΔVDDA
Delta to VDD (VDD
-
0
+100
mV
2
2
VDDA
)
ΔVSSA
Ground voltage
Delta to VSS (VSS
-
-100
0
+100
mV
VSSA
)
VREFH
ADC reference
voltage high
1.13
VSSA
VREFL
VDDA
VSSA
—
VDDA
V
V
VREFL
Reference
voltage low
VSSA
VADIN
CADIN
Input voltage
VREFH
V
Input
capacitance
• 16 bit modes
—
—
8
4
10
5
pF
• 8/10/12 bit
modes
RADIN
RAS
Input resistance
—
—
2
5
5
kΩ
kΩ
Analog source
resistance
13/12 bit modes
fADCK < 4MHz
3
—
fADCK
ADC conversion ≤ 13 bit modes
clock frequency
4
4
1.0
2.0
—
—
18.0
12.0
MHz
MHz
fADCK
ADC conversion 16 bit modes
clock frequency
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
50
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 29. 16-bit ADC operating conditions (continued)
Typ.1
Symbol Description
Conditions
Min.
Max.
Unit
Notes
Crate
ADC conversion ≤ 13 bit modes
5
rate
No ADC hardware
20.000
—
818.330
Ksps
averaging
Continuous
conversions enabled,
subsequent conversion
time
Crate
ADC conversion 16 bit modes
5
rate
No ADC hardware
37.037
—
461.467
Ksps
averaging
Continuous
conversions enabled,
subsequent conversion
time
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
best results. The results in this datasheet were derived from a system which has <8 Ω analog source resistance. The RAS
/
CAS time constant should be kept to <1ns.
4. To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool: http://cache.freescale.com/
files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 21. ADC input impedance equivalency diagram
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
51
Preliminary
Peripheral operating requirements and behaviors
6.6.1.2 16-bit ADC electrical characteristics
Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Conditions1
Typ.2
Symbol Description
Min.
Max.
Unit
Notes
IDDA_ADC Supply current
0.215
—
1.7
mA
3
ADC
asynchronous
clock source
• ADLPC=1, ADHSC=0
1.2
3.0
2.4
4.4
2.4
4.0
5.2
6.2
3.9
7.3
6.1
9.5
tADACK = 1/
fADACK
MHz
MHz
MHz
MHz
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
fADACK
Sample Time
See Reference Manual chapter for sample times
LSB4
LSB4
TUE
DNL
Total unadjusted
error
• 12 bit modes
• <12 bit modes
—
—
4
6.8
2.1
5
5
1.4
Differential non-
linearity
• 12 bit modes
—
0.7
-1.1 to
+1.9
-0.3 to 0.5
• <12 bit modes
• 12 bit modes
—
—
0.2
1.0
LSB4
INL
EFS
Integral non-
linearity
-2.7 to
+1.9
5
-0.7 to
+0.5
• <12 bit modes
—
0.5
LSB4
LSB4
Full-scale error
• 12 bit modes
• <12 bit modes
—
—
-4
-5.4
-1.8
VADIN =
VDDA
-1.4
5
EQ
Quantization
error
• 16 bit modes
• ≤13 bit modes
—
—
-1 to 0
—
—
0.5
ENOB
Effective number 16 bit differential mode
6
of bits
• Avg=32
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg=4
16 bit single-ended mode
• Avg=32
12.2
11.4
13.9
13.1
—
—
bits
bits
• Avg=4
Signal-to-noise
plus distortion
See ENOB
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic
distortion
16 bit differential mode
• Avg=32
7
—
—
–94
-85
—
—
dB
dB
16 bit single-ended mode
• Avg=32
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
52
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
Typ.2
Symbol Description
Min.
Max.
Unit
Notes
SFDR
Spurious free
dynamic range
16 bit differential mode
• Avg=32
7
82
95
—
dB
16 bit single-ended mode
• Avg=32
78
90
—
dB
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
–40°C to 105°C
25°C
—
—
1.715
719
—
—
mV/°C
mV
VTEMP25 Temp sensor
voltage
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock
speed.
1 LSB = (VREFH - VREFL)/2N
4.
5. ADC conversion clock <16MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock <12MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock <12MHz.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
53
Preliminary
Peripheral operating requirements and behaviors
Figure 22. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Figure 23. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
54
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
6.6.1.3 16-bit ADC with PGA operating conditions
Table 31. 16-bit ADC with PGA operating conditions
Typ.1
Symbol Description
VDDA Supply voltage
VREFPGA PGA ref voltage
Conditions
Min.
Max.
Unit
V
Notes
Absolute
1.71
—
3.6
VREF_OU VREF_OU VREF_OU
V
2, 3
T
T
T
VADIN
VCM
Input voltage
VSSA
VSSA
—
—
VDDA
VDDA
V
V
Input Common
Mode range
IN+ to IN-4
RPGAD
Differential input Gain = 1, 2, 4, 8
—
—
—
—
128
64
—
—
—
—
kΩ
impedance
Gain = 16, 32
Gain = 64
32
RAS
TS
Analog source
resistance
100
Ω
µs
5
6
7
ADC sampling
time
1.25
—
—
—
Crate
ADC conversion ≤ 13 bit modes
18.484
450
Ksps
rate
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock = 50
MHz
16 bit modes
37.037
—
250
Ksps
8
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock = 50
MHz
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedance of the driven input is RPGAD/2
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
55
Preliminary
Peripheral operating requirements and behaviors
6.6.1.4 16-bit ADC with PGA characteristics
Table 32. 16-bit ADC with PGA characteristics
Typ.1
Symbol
Description
Conditions
Min.
Max.
Unit
Notes
IDDA_PGA Supply current
Low power
—
420
644
μA
2
(ADC_PGA[PGALPb]=0)
IDC_PGA
Input DC current
A
3
Gain =1, VREFPGA=1.2V,
VCM=0.5V
—
—
1.54
0.57
—
—
μA
μA
Gain =64, VREFPGA=1.2V,
VCM=0.1V
Gain4
G
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
0.95
1.9
1
2
1.05
2.1
R
AS < 100Ω
3.8
4
4.2
7.6
8
8.4
15.2
30.0
58.8
16
31.6
63.3
16.6
33.2
67.8
BW
Input signal
bandwidth
• 16-bit modes
• < 16-bit modes
—
—
—
—
—
4
kHz
kHz
dB
40
—
PSRR
Power supply
rejection ratio
Gain=1
-84
VDDA= 3V
100mV,
fVDDA= 50Hz,
60Hz
CMRR
VOFS
Common mode
rejection ratio
• Gain=1
—
—
-84
-85
—
—
dB
dB
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
• Gain=64
Input offset
voltage
• Chopping disabled
(ADC_PGA[PGACHPb]
=1)
—
—
2.4
0.2
TBD
—
mV
mV
Output offset =
VOFS*(Gain+1)
• Chopping enabled
(ADC_PGA[PGACHPb]
=0)
TGSW
Gain switching
settling time
—
—
10
µs
5
dG/dT
Gain drift over
temperature
• Gain=1
• Gain=64
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
ppm/°C
ppm/°C
0 to 50°C
dVOFS/dT Offset drift over
temperature
Gain=1
ppm/°C 0 to 50°C, ADC
Averaging=32
dG/dVDDA Gain drift over
supply voltage
• Gain=1
• Gain=64
—
—
TBD
TBD
TBD
TBD
%/V
%/V
VDDA from 1.71
to 3.6V
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
56
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 32. 16-bit ADC with PGA characteristics (continued)
Typ.1
Symbol
Description
Conditions
Min.
Max.
Unit
Notes
EIL
Input leakage
error
All modes
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
VPP,DIFF
Maximum
V
6
differential input
signal swing
where VX = VREFPGA × 0.583
SNR
Signal-to-noise
ratio
• Gain=1
80
52
90
66
—
—
dB
dB
16-bit
differential
mode,
• Gain=64
Average=32
THD
Total harmonic
distortion
• Gain=1
85
49
100
95
—
—
dB
dB
16-bit
differential
mode,
• Gain=64
Average=32,
fin=100Hz
SFDR
ENOB
Spurious free
dynamic range
• Gain=1
85
53
105
88
—
—
dB
dB
16-bit
differential
mode,
Average=32,
fin=100Hz
• Gain=64
Effective number
of bits
• Gain=1, Average=4
11.6
TBD
7.2
13.4
12.7
9.6
—
—
—
—
—
—
—
—
—
—
—
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
16-bit
differential
mode,fin=100H
z
• Gain=1, Average=8
• Gain=64, Average=4
• Gain=64, Average=8
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
TBD
12.8
11.0
7.9
8.7
14.5
14.3
13.8
13.1
12.5
11.5
10.6
7.3
6.8
6.8
7.5
SINAD
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to and ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (VCM) and the PGA gain.
Gain = 2PGAG
4.
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
57
Preliminary
Peripheral operating requirements and behaviors
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 33. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
IDDLS
VAIN
VAIO
VH
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
—
—
—
—
—
200
20
μA
μA
V
VSS – 0.3
—
VDD
20
Analog input offset voltage
mV
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
50
—
0.5
200
V
V
—
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
80
250
600
ns
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
—
—
—
7
40
—
μs
IDAC6b
INL
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
58
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
HYSTCTR
Setting
00
01
10
11
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 24. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
59
Preliminary
Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
0.1
HYSTCTR
Setting
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 25. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1 12-bit DAC operating requirements
Table 34. 12-bit DAC operating requirements
Symbol
Desciption
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
VDACR
TA
Reference voltage
Temperature
1.13
−40
—
3.6
105
100
1
V
1
°C
pF
mA
CL
Output load capacitance
Output load current
2
IL
—
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
60
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
6.6.3.2 12-bit DAC operating behaviors
Table 35. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
150
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
μA
P
IDDA_DAC Supply current — high-speed mode
—
—
700
μA
HP
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
—
—
100
15
200
30
1
μs
μs
μs
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
0.7
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
EG
PSRR
TCO
TGE
Gain error
Power supply rejection ratio, VDDA > = 2.4 V
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance load = 3 kΩ
3.7
0.000421
—
—
μV/C
%FSR/C
Ω
6
—
Rop
SR
250
Slew rate -80h→ F7Fh→ 80h
V/μs
• High power (SPHP
• Low power (SPLP
)
1.2
1.7
—
—
0.05
0.12
)
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0+100mV to VDACR−100 mV
3. The DNL is measured for 0+100 mV to VDACR−100 mV
4. The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V
5. Calculated by a best fit curve from VSS+100 mV to VDACR−100 mV
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
61
Peripheral operating requirements and behaviors
6. VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set
to 0x800, Temp range from -40C to 105C
Figure 26. Typical INL error vs. digital code
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
62
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
Figure 27. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 36. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
TA
CL
Temperature
−40
105
°C
nF
Output load capacitance
100
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of
the device.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
63
Preliminary
Peripheral operating requirements and behaviors
Table 37. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1965
1.2
1.2027
V
nominal VDDA and temperature=25C
Voltage reference output with— factory trim
Voltage reference output — user trim
Voltage reference trim step
Vout
Vout
1.1584
1.198
—
—
—
1.2376
1.202
—
V
V
Vstep
Vtdrift
0.5
—
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
—
80
Ibg
Itr
Bandgap only current
—
—
—
—
80
µA
mA
mV
1
1
High-power buffer current
TBD
ΔVLOAD Load regulation
• current = + 1.0 mA
1, 2
—
—
2
5
—
—
• current = - 1.0 mA
Tstup
Buffer startup time
—
—
—
2
100
—
µs
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 38. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
Notes
TA
Temperature
0
50
°C
Table 39. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Vout
Voltage reference output with factory trim
1.173
1.225
V
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
64
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
6.8.1.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Table 40. MII signal switching specifications
Symbol
—
Description
Min.
—
Max.
25
Unit
MHz
RXCLK frequency
RXCLK pulse width high
MII1
35%
65%
RXCLK
period
RXCLK
period
ns
MII2
RXCLK pulse width low
35%
65%
MII3
MII4
—
RXD[3:0], RXDV, RXER to RXCLK setup
RXCLK to RXD[3:0], RXDV, RXER hold
TXCLK frequency
5
5
—
—
ns
—
25
MHz
MII5
TXCLK pulse width high
35%
65%
TXCLK
period
TXCLK
period
ns
MII6
TXCLK pulse width low
35%
65%
MII7
MII8
TXCLK to TXD[3:0], TXEN, TXER invalid
TXCLK to TXD[3:0], TXEN, TXER valid
2
—
—
25
ns
MII6
MII5
MII7
TXCLK (input)
MII8
Valid data
TXD[n:0]
TXEN
Valid data
Valid data
TXER
Figure 28. MII transmit signal timing diagram
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
65
Peripheral operating requirements and behaviors
MII2
MII3
MII1
MII4
RXCLK (input)
RXD[n:0]
RXDV
Valid data
Valid data
Valid data
RXER
Figure 29. MII receive signal timing diagram
6.8.1.2 RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range of
transceiver devices.
Table 41. RMII signal switching specifications
Num
—
Description
Min.
—
Max.
50
Unit
EXTAL frequency (RMII input clock RMII_CLK)
RMII_CLK pulse width high
MHz
RMII1
35%
65%
RMII_CLK
period
RMII2
RMII_CLK pulse width low
35%
65%
RMII_CLK
period
RMII3
RMII4
RMII7
RMII8
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
RMII_CLK to TXD[1:0], TXEN invalid
4
2
—
—
—
15
ns
ns
ns
ns
4
RMII_CLK to TXD[1:0], TXEN valid
—
6.8.2 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit http://www.usb.org.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
66
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
6.8.3 USB DCD electrical specifications
Table 42. USB DCD electrical specifications
Symbol
Description
Min.
0.5
Typ.
Max.
Unit
VDP_SRC
USB_DP source voltage (up to 250 μA)
Threshold voltage for logic high
USB_DP source current
—
0.7
V
VLGC
0.8
7
—
10
2.0
13
V
IDP_SRC
IDM_SINK
μA
μA
kΩ
V
USB_DM sink current
50
100
—
150
24.8
0.4
RDM_DWN D- pulldown resistance for data pin contact detect
VDAT_REF Data detect voltage
14.25
0.25
0.325
6.8.4 USB VREG electrical specifications
Table 43. USB VREG electrical specifications
Typ.1
—
Symbol Description
Min.
2.7
—
Max.
5.5
Unit
Notes
VREGIN Input supply voltage
V
IDDon
IDDstby
IDDoff
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
120
186
μA
Quiescent current — Standby mode, load
current equal zero
—
1.1
1.54
μA
Quiescent current — Shutdown mode
• VREGIN = 5.0 V and temperature=25C
• Across operating voltage and temperature
—
—
650
—
—
4
nA
μA
ILOADrun Maximum load current — Run mode
ILOADstby Maximum load current — Standby mode
—
—
—
—
120
1
mA
mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
3
3.3
2.8
—
3.6
3.6
3.6
V
V
V
• Standby mode
2.1
2.1
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2
COUT
ESR
External output capacitor
1.76
1
2.2
—
8.16
100
μF
External output capacitor equivalent series
resistance
mΩ
ILIM
Short circuit current
—
290
—
mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
67
Preliminary
Peripheral operating requirements and behaviors
6.8.5 ULPI timing specifications
The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin
Interface. Control and data timing requirements for the ULPI pins are given in the
following table. These timings apply to synchronous mode only. All timings are
measured with respect to the clock as seen at the USB_CLKIN pin.
Table 44. ULPI timing specifications
Num
Description
Min.
Typ.
Max.
Unit
USB_CLKIN
operating
—
60
—
MHz
frequency
USB_CLKIN duty
cycle
—
—
5
50
16.67
—
—
—
—
—
9.5
—
%
ns
ns
ns
ns
ns
U1
U2
U3
U4
U5
USB_CLKIN clock
period
Input setup (control
and data)
Input hold (control
and data)
1
—
Output valid
(control and data)
—
1
—
Output hold
—
(control and data)
U1
USB_CLKIN
U2
U3
ULPI_DIR/ULPI_NXT
(control input)
ULPI_DATAn (input)
U5
U4
ULPI_STP
(control output)
ULPI_DATAn (output)
Figure 30. ULPI timing diagram
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
68
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.8.6 CAN switching specifications
See General switching specifications.
6.8.7 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 45. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
30
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
ns
(tBUS x 2) −
2
—
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
−2
15
0
8.5
—
—
—
ns
ns
ns
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 31. DSPI classic SPI timing — master mode
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
69
Preliminary
Peripheral operating requirements and behaviors
Table 46. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
3.6
15
Unit
V
Operating voltage
2.7
Frequency of operation
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
ns
ns
ns
ns
ns
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
10
—
—
—
14
14
2
7
—
—
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 32. DSPI classic SPI timing — slave mode
6.8.8 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 47. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
—
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
1
15
MHz
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
70
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 47. Master mode DSPI timing (full voltage range) (continued)
Num
Description
DSPI_SCK output cycle time
Min.
Max.
Unit
Notes
DS1
4 x tBUS
—
ns
DS2
DS3
DSPI_SCK output high/low time
(tSCK/2) - 4 (tSCK/2) + 4
ns
ns
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-4.5
20.5
0
10
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 33. DSPI classic SPI timing — master mode
Table 48. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
7.5
—
Unit
V
Operating voltage
Frequency of operation
—
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
DS10
DS11
DS12
DS13
DS14
DS15
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
(tSCK/2) - 4
(tSCK/2) + 4
ns
ns
ns
ns
ns
ns
—
0
20
—
—
—
19
2
7
—
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
71
Peripheral operating requirements and behaviors
Table 48. Slave mode DSPI timing (full voltage range) (continued)
Num
Description
Min.
Max.
Unit
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
19
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 34. DSPI classic SPI timing — slave mode
I2C switching specifications
6.8.9
See General switching specifications.
6.8.10 UART switching specifications
See General switching specifications.
6.8.11 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 49. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Card input clock
Table continues on the next page...
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
72
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 49. SDHC switching specifications
(continued)
Num
Symbol
fpp
Description
Min.
Max.
400
25
Unit
kHz
SD1
Clock frequency (low speed)
Clock frequency (SD\SDIO full speed)
Clock frequency (MMC full speed)
Clock frequency (identification mode)
Clock low time
0
0
0
0
fpp
MHz
MHz
kHz
fpp
20
fOD
400
SD2
SD3
SD4
SD5
tWL
tWH
tTLH
tTHL
7
7
—
—
3
ns
ns
ns
ns
Clock high time
Clock rise time
—
—
Clock fall time
3
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid) -5 6.5
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
ns
SD7
SD8
tISU
tIH
SDHC input setup time
SDHC input hold time
5
0
—
—
ns
ns
SD3
SD6
SD2
SD1
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
SD7
SD8
Input SDHC_DAT[3:0]
Figure 35. SDHC timing
6.8.12 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
73
Preliminary
Peripheral operating requirements and behaviors
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
Table 50. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
V
I2S_MCLK cycle time1
S1
S2
S3
ns
I2S_MCLK pulse width high/low
I2S_TX_BCLK cycle time (output)1
I2S_RX_BCLK cycle time (output)1
I2S_TX_BCLK pulse width high/low
45%
80
55%
—
MCLK period
ns
160
—
S4
S5
45%
—
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
15
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
25
S10
S11
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid2
0
—
ns
ns
—
21
1. This parameter is limited in VLPx modes.
2. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 36. I2S/SAI timing — master modes
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
74
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 51. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
80
3.6
—
V
S11
I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK cycle time (input)
ns
160
—
S12
S13
S14
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
10
2
55%
MCLK period
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
29
—
—
—
21
ns
ns
ns
ns
ns
10
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
S12
I2S_RX_BCLK (input)
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S16
S15
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 37. I2S/SAI timing — slave modes
6.9 Human-machine interfaces (HMI)
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
75
Preliminary
Peripheral operating requirements and behaviors
6.9.1 TSI electrical specifications
Table 52. TSI electrical specifications
Symbol Description
VDDTSI Operating voltage
CELE
Min.
Typ.
Max.
Unit
Notes
1.71
—
3.6
V
Target electrode capacitance range
Reference oscillator frequency
Electrode oscillator frequency
Internal reference capacitor
Oscillator delta voltage
1
20
8
500
TBD
TBD
TBD
TBD
pF
MHz
MHz
pF
1
2
2
fREFmax
fELEmax
CREF
—
—
0.5
1
TBD
TBD
VDELTA
IREF
600
mV
μA
2
Reference oscillator current source base current
• 1uA setting (REFCHRG=0)
2, 3
—
—
1.133
36
1.5
50
• 32uA setting (REFCHRG=31)
IELE
Electrode oscillator current source base current
• 1uA setting (EXTCHRG=0)
μA
2, 4
—
—
1.133
36
1.5
50
• 32uA setting (EXTCHRG=31)
Pres5
Electrode capacitance measurement precision
Electrode capacitance measurement precision
—
8.3333
8.3333
8.3333
12.5
—
38.4
38.4
38.4
—
pF/count
pF/count
pF/count
fF/count
bits
5
6
7
8
Pres20
—
Pres100 Electrode capacitance measurement precision
MaxSens Maximum sensitivity
—
0.003
—
Res
Resolution
16
TCon20
Response time @ 20 pF
8
15
25
μs
9
ITSI_RUN Current added in run mode
ITSI_LP Low power mode current adder
—
—
55
—
μA
1.3
TBD
μA
10
1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. Fixed external capacitance of 20 pF.
3. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
4. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.
5. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
6. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
7. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
8. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes, it is equal to (Cref
* Iext)/( Iref * PS * NSCN). Sensitivity depends on the configuration used. The typical value listed is based on the following
configuration: Iext = 5 μA, EXTCHRG = 4, PS = 128, NSCN = 2, Iref = 16 μA, REFCHRG = 15, Cref = 1.0 pF. The minimum
sensitivity describes the smallest possible capacitance that can be measured by a single count (this is the best sensitivity
but is described as a minimum because it’s the smallest number). The minimum sensitivity parameter is based on the
following configuration: Iext = 1 μA, EXTCHRG = 0, PS = 128, NSCN = 32, Iref = 32 μA, REFCHRG = 31, Cref= 0.5 pF
9. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, EXTCHRG = 15.
10. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of
20 pF. Data is captured with an average of 7 periods window.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
76
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
6.9.2 LCDC electrical specifications
Table 53. GLCD_LSCLK Timing
Num
T1
Description
Min.
Max.
2000
—
Unit
ns
GLCD_LSCLK Period
Pixel data setup time
Pixel data up time
TBD
TBD
TBD
T2
ns
T3
—
ns
NOTE
The pixel clock is equal to GLCD_LSCLK / (PCD + 1). When
it is in CSTN, TFT, or monochrome mode with bus width = 1,
GLCD_LSCLK is equal to the pixel clock. When it is in
monochrome with other bus width settings, GLCD_LSCLK is
equal to the pixel clock divided by bus width. The polarity of
GLCD_LSCLK and GLCD_D signals can also be programmed.
T1
GLCD_LSCLK
GLCD_D[17:0]
T2
T3
Figure 38. GLCD_LSCLK to GLCD_D[17:0] Timing
Non-display region
T3
Display region
T1
T4
GLCD_VSYNC
GLCD_HSYNC
GLCD_OE
T2
Line
Y
Line
1
Line
Y
GLCD_D[17:0]
T5
T6
XMAX
T7
GLCD_HSYNC
GLCD_LSCLK
GLCD_OE
(1,1) (1,2)
(1,X)
GLCD_D[15:0]
Figure 39. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
77
Preliminary
Peripheral operating requirements and behaviors
Table 54. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
Num
Description
Min.
Max.
Unit
T1
End of GLCD_OE to beginning of GLCD_VSYNC
T5 + T6 + T7
– 1
(VWAIT1 ×
T2) + T5 + T6
+ T7 – 1
Ts
T2
GLCD_HSYNC period
—
XMAX + T5 +
T6 + T7
Ts
T3
T4
GLCD_VSYNC pulse width
T2
1
VWIDTH × T2
Ts
Ts
End of GLCD_VSYNC to beginning of GLCD_OE
(VWAIT2 ×
T2) + 1
T5
T6
T7
GLCD_HSYNC pulse width
1
3
1
HWIDTH + 1
HWAIT2 + 3
HWAIT1 + 1
Ts
Ts
Ts
End of GLCD_HSYNC to beginning to GLCD_OE
End of GLCD_OE to beginning of GLCD_HSYNC
NOTE
• Ts is the GLCD_LSCLK period. GLCD_VSYNC,
GLCD_HSYNC, and GLCD_OE can be programmed as
active high or active low. In the preceding figure, all 3
signals are active low. GLCD_LSCLK can be programmed
to be deactivated during the GLCD_VSYNC pulse or the
GLCD_OE deasserted period. In the preceding figure,
GLCD_LSCLK is always active.
• XMAX is defined in number of pixels in one line.
T1
T1
GLCD_VSYNC
GLCD_HSYNC
GLCD_LSCLK
GLCD_D[15:0]
T2
T3
XMAX
T4
T2
TS
Figure 40. Non-TFT Mode Panel Timing
Table 55. Non-TFT Mode Panel Timing
Num
Description
Min.
Max.
HWAIT2 + 2
Unit
T1
GLCD_HSYNC to GLCD_VSYNC delay
Table continues on the next page...
2
Tpix
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
78
Freescale Semiconductor, Inc.
Dimensions
Table 55. Non-TFT Mode Panel Timing (continued)
Num
T2
Description
Min.
1
Max.
Unit
Tpix
—
GLCD_HSYNC pulse width
HWIDTH + 1
0 ≤ T3 ≤ Ts
HWAIT1 + 1
T3
GLCD_VSYNC to GLCD_LSCLK
GLCD_LSCLK to GLCD_HSYNC
—
1
T4
Tpix
NOTE
Ts is the GLCD_LSCLK period while Tpix is the pixel clock
period. GLCD_VSYNC, GLCD_HSYNC, and GLCD_LSCLK
can be programmed as active high or active low. In the
preceding figure, all these 3 signals are active high. When it is
in CSTN mode or monochrome mode with bus width = 1, T3 =
Tpix = Ts. When it is in monochrome mode with bus width = 2,
4 and 8, T3 = 1, 2 and 4 Tpix respectively.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
256-pin MAPBGA
Then use this document number
98ASA00346D
8 Pinout
8.1 K70 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
79
Preliminary
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
E2
F2
F3
G2
PTE0
ADC1_SE4a ADC1_SE4a PTE0
ADC1_SE5a ADC1_SE5a PTE1/
LLWU_P0
ADC1_SE6a ADC1_SE6a PTE2/
LLWU_P1
ADC1_SE7a ADC1_SE7a PTE3
SPI1_PCS1
SPI1_SOUT
SPI1_SCK
SPI1_SIN
UART1_TX
UART1_RX
SDHC0_D1
SDHC0_D0
GLCD_D0
GLCD_D1
I2C1_SDA
I2C1_SCL
RTC_CLKO
UT
PTE1/
LLWU_P0
SPI1_SIN
PTE2/
LLWU_P1
UART1_CTS SDHC0_DCL GLCD_D2
_b
K
PTE3
UART1_RTS SDHC0_CM
GLCD_D3
SPI1_SOUT
_b
D
G7
H7
H8
F1
VDD
VDD
VDD
VDDINT
VSS
VDDINT
VSS
VDDINT
VSS
PTF17
PTF18
DISABLED
DISABLED
DISABLED
PTF17
PTF18
SPI2_SCK
SPI2_SOUT
SPI1_PCS0
FTM0_CH4
FTM1_CH0
UART3_TX
UART0_RX
UART0_TX
SDHC0_D3
GLCD_D13
GLCD_D14
GLCD_D4
G1
G3
PTE4/
PTE4/
LLWU_P2
LLWU_P2
G4
H2
PTE5
PTE6
DISABLED
DISABLED
PTE5
PTE6
SPI1_PCS2
SPI1_PCS3
UART3_RX
SDHC0_D2
GLCD_D5
GLCD_D6
FTM3_CH0
FTM3_CH1
UART3_CTS I2S0_MCLK
_b
USB_SOF_
OUT
H1
H5
H3
PTF19
PTF20
PTE7
DISABLED
DISABLED
DISABLED
PTF19
PTF20
PTE7
SPI2_SIN
FTM1_CH1
FTM2_CH0
UART5_RX
UART5_TX
GLCD_D15
GLCD_D16
GLCD_D7
SPI2_PCS1
UART3_RTS I2S0_RXD0
_b
FTM3_CH2
H4
J1
PTE8
PTE9
ADC2_SE16 ADC2_SE16 PTE8
ADC2_SE17 ADC2_SE17 PTE9
I2S0_RXD1
I2S0_TXD1
UART5_TX
UART5_RX
I2S0_RX_FS GLCD_D8
FTM3_CH3
FTM3_CH4
I2S0_RX_BC GLCD_D9
LK
J2
K1
K3
PTE10
PTE11
PTE12
DISABLED
PTE10
UART5_CTS I2S0_TXD0
_b
GLCD_D10
FTM3_CH5
FTM3_CH6
FTM3_CH7
ADC3_SE16 ADC3_SE16 PTE11
ADC3_SE17 ADC3_SE17 PTE12
UART5_RTS I2S0_TX_FS GLCD_D11
_b
I2S0_TX_BC GLCD_D12
LK
G8
H9
J3
VDD
VDD
VSS
VDD
VSS
VSS
PTE16
ADC0_SE4a ADC0_SE4a PTE16
ADC0_SE5a ADC0_SE5a PTE17
ADC0_SE6a ADC0_SE6a PTE18
ADC0_SE7a ADC0_SE7a PTE19
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART2_TX
UART2_RX
FTM_CLKIN
0
FTM0_FLT3
K2
L4
PTE17
PTE18
PTE19
FTM_CLKIN
1
LPTMR0_AL
T3
UART2_CTS I2C0_SDA
_b
M3
UART2_RTS I2C0_SCL
_b
CMP3_OUT
L2
M1
M2
L1
VSS
VSS
VSS
USB0_DP
USB0_DM
VOUT33
USB0_DP
USB0_DM
VOUT33
USB0_DP
USB0_DM
VOUT33
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
80
Freescale Semiconductor, Inc.
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
L3
VREGIN
VREGIN
VREGIN
N1
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
N2
P1
P2
PGA2_DM/
ADC2_DM0/ ADC2_DM0/ ADC2_DM0/
ADC3_DM3/ ADC3_DM3/ ADC3_DM3/
PGA2_DM/
PGA2_DM/
ADC0_DM1
ADC0_DM1
ADC0_DM1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DM/
PGA3_DM/
PGA3_DM/
ADC3_DM0/ ADC3_DM0/ ADC3_DM0/
ADC2_DM3/ ADC2_DM3/ ADC2_DM3/
ADC1_DM1
ADC1_DM1
ADC1_DM1
R1
R2
T1
T2
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/ ADC0_DM0/ ADC0_DM0/
ADC1_DM3
PGA0_DM/
PGA0_DM/
ADC1_DM3
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
PGA1_DM/
PGA1_DM/
ADC1_DM0/ ADC1_DM0/ ADC1_DM0/
ADC0_DM3
ADC0_DM3
ADC0_DM3
N5
P4
M4
N4
P3
VDDA
VDDA
VDDA
VREFH
VREFL
VSSA
VREFH
VREFL
VSSA
VREFH
VREFL
VSSA
ADC1_SE16/ ADC1_SE16/ ADC1_SE16/
CMP2_IN2/ CMP2_IN2/ CMP2_IN2/
ADC0_SE22 ADC0_SE22 ADC0_SE22
N3
T3
ADC0_SE16/ ADC0_SE16/ ADC0_SE16/
CMP1_IN2/
CMP1_IN2/
CMP1_IN2/
ADC0_SE21 ADC0_SE21 ADC0_SE21
VREF_OUT/ VREF_OUT/ VREF_OUT/
CMP1_IN5/
CMP0_IN5/
CMP1_IN5/
CMP0_IN5/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18 ADC1_SE18 ADC1_SE18
R3
R4
DAC0_OUT/ DAC0_OUT/ DAC0_OUT/
CMP1_IN3/
CMP1_IN3/
CMP1_IN3/
ADC0_SE23 ADC0_SE23 ADC0_SE23
DAC1_OUT/ DAC1_OUT/ DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
CMP0_IN4/
CMP2_IN3/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23 ADC1_SE23 ADC1_SE23
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
81
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
M5
TAMPER0/
TAMPER0/
TAMPER0/
RTC_WAKE RTC_WAKE RTC_WAKE
UP_B
UP_B
UP_B
L5
L6
TAMPER1
TAMPER2
TAMPER3
TAMPER4
TAMPER5
XTAL32
TAMPER1
TAMPER2
TAMPER3
TAMPER4
TAMPER5
XTAL32
EXTAL32
VBAT
TAMPER1
TAMPER2
TAMPER3
TAMPER4
TAMPER5
XTAL32
EXTAL32
VBAT
R5
P6
R6
T6
T5
P5
N6
M6
G9
EXTAL32
VBAT
TAMPER6
TAMPER7
VDD
TAMPER6
TAMPER7
VDD
TAMPER6
TAMPER7
VDD
H10 VDDINT
VDDINT
VSS
VDDINT
VSS
J8
VSS
P7
PTE24
ADC0_SE17/ ADC0_SE17/ PTE24
EXTAL1 EXTAL1
CAN1_TX
CAN1_RX
UART4_TX
UART4_RX
I2S1_TX_FS GLCD_D13
EWM_OUT_ I2S1_RXD1
b
R7
M7
K7
PTE25
PTE26
PTE27
ADC0_SE18/ ADC0_SE18/ PTE25
XTAL1 XTAL1
I2S1_TX_BC GLCD_D14
LK
EWM_IN
I2S1_TXD1
ADC3_SE5b ADC3_SE5b PTE26
ADC3_SE4b ADC3_SE4b PTE27
ADC3_SE7a ADC3_SE7a PTE28
ENET_1588
_CLKIN
UART4_CTS I2S1_TXD0
_b
GLCD_D15
GLCD_D16
GLCD_D17
RTC_CLKO
UT
USB_CLKIN
UART4_RTS I2S1_MCLK
_b
L7
T7
PTE28
PTA0
JTAG_TCLK/ TSI0_CH1
SWD_CLK/
PTA0
UART0_CTS FTM0_CH5
_b/
JTAG_TCLK/ EZP_CLK
SWD_CLK
EZP_CLK
UART0_COL
_b
N8
T8
PTA1
PTA2
JTAG_TDI/
EZP_DI
TSI0_CH2
TSI0_CH3
PTA1
PTA2
UART0_RX
FTM0_CH6
FTM0_CH7
JTAG_TDI
EZP_DI
JTAG_TDO/
TRACE_SW
O/EZP_DO
UART0_TX
JTAG_TDO/
TRACE_SW
O
EZP_DO
P8
R8
PTA3
JTAG_TMS/
SWD_DIO
TSI0_CH4
TSI0_CH5
PTA3
UART0_RTS FTM0_CH0
_b
JTAG_TMS/
SWD_DIO
PTA4/
NMI_b/
PTA4/
FTM0_CH1
NMI_b
EZP_CS_b
LLWU_P3
EZP_CS_b
LLWU_P3
T12 PTA5
DISABLED
PTA5
USB_CLKIN FTM0_CH2
RMII0_RXE
R/
CMP2_OUT
I2S0_TX_BC JTAG_TRST
LK
_b
MII0_RXER
G10 VDD
VDD
VSS
VDD
VSS
J9
VSS
P9
PTF21
ADC3_SE6b ADC3_SE6b PTF21
FTM2_CH1
UART5_RTS
_b
GLCD_D17
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
82
Freescale Semiconductor, Inc.
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
N9
PTF22
ADC3_SE7b ADC3_SE7b PTF22
ADC3_SE6a ADC3_SE6a PTA6
ADC0_SE10 ADC0_SE10 PTA7
ADC0_SE11 ADC0_SE11 PTA8
ADC3_SE5a ADC3_SE5a PTA9
ADC3_SE4a ADC3_SE4a PTA10
ADC3_SE15 ADC3_SE15 PTA11
I2C0_SCL
ULPI_CLK
ULPI_DIR
ULPI_NXT
ULPI_STP
FTM1_CH0
FTM0_CH3
FTM0_CH4
FTM1_CH0
FTM1_CH1
FTM2_CH0
FTM2_CH1
FTM1_CH0
FTM1_CH1
UART0_TX
UART5_CTS
_b
GLCD_D18
R12 PTA6
P12 PTA7
N12 PTA8
T13 PTA9
P13 PTA10
R13 PTA11
M10 PTA12
N10 PTA13/
I2S1_RXD0
CLKOUT
TRACE_CLK
OUT
I2S1_RX_BC
LK
TRACE_D3
I2S1_RX_FS
MII0_RXD3
MII0_RXD2
MII0_RXCLK
FTM1_QD_P TRACE_D2
HA
FTM1_QD_P TRACE_D1
HB
ULPI_DATA
0
FTM2_QD_P TRACE_D0
HA
ULPI_DATA
1
FTM2_QD_P
HB
CMP2_IN0
CMP2_IN1
CMP3_IN0
CMP2_IN0
CMP2_IN1
CMP3_IN0
PTA12
CAN0_TX
CAN0_RX
SPI0_PCS0
RMII0_RXD1
/MII0_RXD1
I2S0_TXD0
FTM1_QD_P
HA
PTA13/
LLWU_P4
RMII0_RXD0
/MII0_RXD0
I2S0_TX_FS FTM1_QD_P
HB
LLWU_P4
R11 PTA14
PTA14
RMII0_CRS_
DV/
I2S0_RX_BC I2S0_TXD1
LK
MII0_RXDV
P11 PTA15
CMP3_IN1
CMP3_IN1
PTA15
SPI0_SCK
UART0_RX
RMII0_TXEN
/MII0_TXEN
I2S0_RXD0
T14 VSS
VSS
VSS
N11 PTA16
CMP3_IN2
CMP3_IN2
PTA16
SPI0_SOUT
UART0_CTS RMII0_TXD0
I2S0_RX_FS I2S0_RXD1
_b/
/MII0_TXD0
UART0_COL
_b
T11 PTA17
P10 PTF23
R10 PTF24
ADC1_SE17 ADC1_SE17 PTA17
ADC3_SE10 ADC3_SE10 PTF23
ADC3_SE11 ADC3_SE11 PTF24
ADC3_SE12 ADC3_SE12 PTF25
ADC3_SE13 ADC3_SE13 PTF26
ADC3_SE14 ADC3_SE14 PTF27
SPI0_SIN
I2C0_SDA
CAN1_RX
CAN1_TX
UART0_RTS RMII0_TXD1
I2S0_MCLK
_b
/MII0_TXD1
FTM1_CH1
TRACE_CLK GLCD_D19
OUT
FTM1_QD_P
HA
TRACE_D3
TRACE_D2
TRACE_D1
TRACE_D0
GLCD_D20
GLCD_D21
GLCD_D22
GLCD_D23
R9
T9
PTF25
PTF26
FTM1_QD_P
HB
FTM2_QD_P
HA
T10 PTF27
FTM2_QD_P
HB
J7
VDD
VSS
VDD
VDD
K8
VSS
VSS
T15 PTA18
T16 PTA19
R16 RESET_b
EXTAL0
EXTAL0
PTA18
PTA19
FTM0_FLT2
FTM1_FLT0
FTM_CLKIN
0
XTAL0
XTAL0
FTM_CLKIN
1
LPTMR0_AL
T1
RESET_b
RESET_b
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
83
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
N13 PTA24
R14 PTA25
M13 PTA26
R15 PTA27
P14 PTA28
N14 PTA29
CMP3_IN4
CMP3_IN5
CMP3_IN4
CMP3_IN5
PTA24
ULPI_DATA
2
MII0_TXD2
MII0_TXCLK
MII0_TXD3
MII0_CRS
MII0_TXER
MII0_COL
FB_A29
PTA25
ULPI_DATA
3
FB_A28
FB_A27
FB_A26
FB_A25
FB_A24
ADC2_SE15 ADC2_SE15 PTA26
ADC2_SE14 ADC2_SE14 PTA27
ADC2_SE13 ADC2_SE13 PTA28
ADC2_SE12 ADC2_SE12 PTA29
ULPI_DATA
4
ULPI_DATA
5
ULPI_DATA
6
ULPI_DATA
7
P16 PTF0
L13 PTF1
ADC2_SE11 ADC2_SE11 PTF0
ADC2_SE10 ADC2_SE10 PTF1
CAN0_TX
CAN0_RX
FTM3_CH0
FTM3_CH1
I2S1_RXD1
GLCD_PCLK
GLCD_DE
I2S1_RX_BC
LK
M12 PTB0/
ADC0_SE8/
ADC1_SE8/
ADC2_SE8/
ADC3_SE8/
TSI0_CH0
ADC0_SE8/
ADC1_SE8/
ADC2_SE8/
ADC3_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL
I2C0_SDA
FTM1_CH0
RMII0_MDIO
/MII0_MDIO
FTM1_QD_P
HA
LLWU_P5
M11 PTB1
ADC0_SE9/
ADC1_SE9/
ADC2_SE9/
ADC3_SE9/
TSI0_CH6
ADC0_SE9/
ADC1_SE9/
ADC2_SE9/
ADC3_SE9/
TSI0_CH6
PTB1
FTM1_CH1
RMII0_MDC/
MII0_MDC
FTM1_QD_P
HB
P15 PTB2
M14 PTB3
ADC0_SE12/ ADC0_SE12/ PTB2
TSI0_CH7 TSI0_CH7
I2C0_SCL
I2C0_SDA
UART0_RTS ENET0_158
_b 8_TMR0
FTM0_FLT3
FTM0_FLT0
ADC0_SE13/ ADC0_SE13/ PTB3
TSI0_CH8 TSI0_CH8
UART0_CTS ENET0_158
_b/
8_TMR1
UART0_COL
_b
N15 PTB4
M15 PTB5
ADC1_SE10 ADC1_SE10 PTB4
ADC1_SE11 ADC1_SE11 PTB5
GLCD_CON
TRAST
ENET0_158
8_TMR2
FTM1_FLT0
FTM2_FLT0
ENET0_158
8_TMR3
L14 PTB6
L15 PTB7
K14 PTB8
ADC1_SE12 ADC1_SE12 PTB6
ADC1_SE13 ADC1_SE13 PTB7
FB_AD23
FB_AD22
FB_AD21
DISABLED
PTB8
UART3_RTS
_b
K15 PTB9
J13 PTB10
J14 PTB11
DISABLED
PTB9
SPI1_PCS1
SPI1_PCS0
SPI1_SCK
UART3_CTS
_b
FB_AD20
ADC1_SE14 ADC1_SE14 PTB10
ADC1_SE15 ADC1_SE15 PTB11
UART3_RX
I2S1_TX_BC FB_AD19
LK
FTM0_FLT1
FTM0_FLT2
UART3_TX
I2S1_TX_FS FB_AD18
K9
VSS
VSS
VDD
VSS
VDD
J10 VDD
N16 PTF2
ADC2_SE6a ADC2_SE6a PTF2
I2C1_SCL
FTM3_CH2
I2S1_RX_FS
GLCD_HFS
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
84
Freescale Semiconductor, Inc.
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
M16 PTF3
L16 PTF4
J15 PTB16
H13 PTB17
ADC2_SE7a ADC2_SE7a PTF3
ADC2_SE4b ADC2_SE4b PTF4
I2C1_SDA
FTM3_CH3
FTM3_CH4
UART0_RX
UART0_TX
I2S1_RXD0
I2S1_TXD0
FB_AD17
GLCD_VFS
GLCD_D0
TSI0_CH9
TSI0_CH9
PTB16
PTB17
SPI1_SOUT
SPI1_SIN
I2S1_TXD0
I2S1_TXD1
EWM_IN
TSI0_CH10
TSI0_CH10
FB_AD16
EWM_OUT_
b
H14 PTB18
TSI0_CH11
TSI0_CH11
PTB18
CAN0_TX
FTM2_CH0
I2S0_TX_BC FB_AD15
LK
FTM2_QD_P
HA
K16 PTF5
J16 PTF6
ADC2_SE5b ADC2_SE5b PTF5
ADC2_SE6b ADC2_SE6b PTF6
FTM3_CH5
FTM3_CH6
I2S1_TX_FS
GLCD_D1
GLCD_D2
I2S1_TX_BC
LK
H15 PTB19
G13 PTB20
TSI0_CH12
TSI0_CH12
PTB19
CAN0_RX
FTM2_CH1
I2S0_TX_FS FB_OE_b
FTM2_QD_P
HB
ADC2_SE4a ADC2_SE4a PTB20
ADC2_SE5a ADC2_SE5a PTB21
SPI2_PCS0
FB_AD31/
NFC_DATA1
5
CMP0_OUT
CMP1_OUT
CMP2_OUT
CMP3_OUT
I2S0_TXD1
I2S0_TXD0
I2S0_TX_FS
G14 PTB21
G15 PTB22
H16 PTB23
G16 PTC0
F13 PTC1/
SPI2_SCK
SPI2_SOUT
SPI2_SIN
FB_AD30/
NFC_DATA1
4
DISABLED
DISABLED
PTB22
PTB23
FB_AD29/
NFC_DATA1
3
SPI0_PCS5
FB_AD28/
NFC_DATA1
2
ADC0_SE14/ ADC0_SE14/ PTC0
TSI0_CH13 TSI0_CH13
SPI0_PCS4
SPI0_PCS3
SPI0_PCS2
SPI0_PCS1
PDB0_EXTR
G
FB_AD14/
NFC_DATA1
1
ADC0_SE15/ ADC0_SE15/ PTC1/
TSI0_CH14 TSI0_CH14 LLWU_P6
UART1_RTS FTM0_CH0
_b
FB_AD13/
NFC_DATA1
0
LLWU_P6
F14 PTC2
ADC0_SE4b/ ADC0_SE4b/ PTC2
CMP1_IN0/
TSI0_CH15
UART1_CTS FTM0_CH1
_b
FB_AD12/
NFC_DATA9
CMP1_IN0/
TSI0_CH15
E13 PTC3/
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
UART1_RX
FTM3_CH7
FTM0_CH2
UART3_RX
CLKOUT
I2S0_TX_BC
LK
LLWU_P7
F15 PTF7
L9 VSS
ADC2_SE7b ADC2_SE7b PTF7
I2S1_TXD1
GLCD_D3
GLCD_D4
VSS
VSS
VDD
K10 VDD
F16 PTF8
E14 PTC4/
LLWU_P8
E15 PTC5/
LLWU_P9
F12 PTC6/
LLWU_P10
G12 PTC7
VDD
DISABLED
DISABLED
PTF8
FTM3_FLT0
UART1_TX
UART3_TX
FTM0_CH3
I2S1_MCLK
PTC4/
LLWU_P8
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
FB_AD11/
CMP1_OUT
CMP0_OUT
I2S0_MCLK
I2S1_TX_BC
LK
NFC_DATA8
DISABLED
CMP0_IN0
CMP0_IN1
PTC5/
LLWU_P9
LPTMR0_AL I2S0_RXD0
T2
FB_AD10/
NFC_DATA7
I2S1_TX_FS
CMP0_IN0
CMP0_IN1
PTC6/
LLWU_P10
PDB0_EXTR I2S0_RX_BC FB_AD9/
G
LK
I2S0_RX_FS FB_AD8/
NFC_DATA5
NFC_DATA6
PTC7
USB_SOF_
OUT
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
85
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
H12 PTC8
F11 PTC9
G11 PTC10
H11 PTC11/
ADC1_SE4b/ ADC1_SE4b/ PTC8
CMP0_IN2 CMP0_IN2
FTM3_CH4
FTM3_CH5
FTM3_CH6
FTM3_CH7
I2S0_MCLK
FB_AD7/
NFC_DATA4
ADC1_SE5b/ ADC1_SE5b/ PTC9
CMP0_IN3 CMP0_IN3
I2S0_RX_BC FB_AD6/
LK
FTM2_FLT0
I2S1_MCLK
NFC_DATA3
ADC1_SE6b ADC1_SE6b PTC10
I2C1_SCL
I2C1_SDA
I2S0_RX_FS FB_AD5/
NFC_DATA2
ADC1_SE7b ADC1_SE7b PTC11/
I2S0_RXD1
FB_RW_b/
LLWU_P11
LLWU_P11
PTC12
NFC_WE
FB_AD27
J12 PTC12
K13 PTC13
DISABLED
DISABLED
UART4_RTS
_b
FTM3_FLT0
PTC13
UART4_CTS
_b
FB_AD26
FB_AD25
J11 PTC14
K12 PTF9
DISABLED
CMP2_IN4
PTC14
PTF9
UART4_RX
CMP2_IN4
CMP2_IN5
UART3_RTS
_b
GLCD_D5
GLCD_D6
L12 PTF10
CMP2_IN5
PTF10
PTC15
UART3_CTS
_b
F10 PTC15
DISABLED
VSS
UART4_TX
FB_AD24
N7
VSS
VSS
VDD
L10 VDD
VDD
K11 PTF11
DISABLED
PTF11
PTF12
PTC16
UART2_RTS
_b
GLCD_D7
GLCD_D8
L11 PTF12
DISABLED
DISABLED
UART2_CTS
_b
F9
E9
M9
PTC16
PTC17
PTC18
PTC19
CAN1_RX
CAN1_TX
UART3_RX
UART3_TX
ENET0_158
8_TMR0
FB_CS5_b/
FB_TSIZ1/
FB_BE23_16
_b
NFC_RB
DISABLED
DISABLED
PTC17
PTC18
PTC19
ENET0_158
8_TMR1
FB_CS4_b/
FB_TSIZ0/
FB_BE31_24
_b
NFC_CE0_b
UART3_RTS ENET0_158
_b 8_TMR2
FB_TBST_b/ NFC_CE1_b
FB_CS2_b/
FB_BE15_8_
b
M8
L8
DISABLED
DISABLED
UART3_CTS ENET0_158
_b 8_TMR3
FB_CS3_b/
FB_BE7_0_b
FB_TA_b
PTD0/
PTD0/
LLWU_P12
SPI0_PCS0
UART2_RTS FTM3_CH0
_b
FB_ALE/
FB_CS1_b/
FB_TS_b
I2S1_RXD1
LLWU_P12
F8
K6
J6
PTD1
ADC0_SE5b ADC0_SE5b PTD1
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART2_CTS FTM3_CH1
_b
FB_CS0_b
FB_AD4
FB_AD3
I2S1_RXD0
PTD2/
LLWU_P13
DISABLED
DISABLED
PTD2/
LLWU_P13
UART2_RX
FTM3_CH2
I2S1_RX_FS
PTD3
PTD3
UART2_TX
FTM3_CH3
I2S1_RX_BC
LK
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
86
Freescale Semiconductor, Inc.
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
K5
PTD4/
LLWU_P14
DISABLED
PTD4/
LLWU_P14
SPI0_PCS1
SPI0_PCS2
UART0_RTS FTM0_CH4
_b
FB_AD2/
NFC_DATA1
EWM_IN
J5
PTD5
ADC0_SE6b ADC0_SE6b PTD5
UART0_CTS FTM0_CH5
_b/
FB_AD1/
NFC_DATA0
EWM_OUT_
b
UART0_COL
_b
K4
PTD6/
ADC0_SE7b ADC0_SE7b PTD6/
SPI0_PCS3
UART0_RX
FTM0_CH6
FB_AD0
FTM0_FLT0
LLWU_P15
LLWU_P15
PTF13
H6
G6
T4
E7
J4
PTF13
PTF14
VSS
DISABLED
DISABLED
VSS
UART2_RX
UART2_TX
GLCD_D9
PTF14
GLCD_D10
VSS
PTD7
PTD8
DISABLED
DISABLED
PTD7
PTD8
CMT_IRO
I2C0_SCL
UART0_TX
UART5_RX
FTM0_CH7
FTM0_FLT1
FB_A16/
NFC_CLE
F7
E6
G5
PTD9
DISABLED
DISABLED
DISABLED
PTD9
I2C0_SDA
UART5_TX
FB_A17/
NFC_ALE
PTD10
PTD11
PTD10
PTD11
UART5_RTS
_b
FB_A18/
NFC_RE
SPI2_PCS0
UART5_CTS SDHC0_CLK
_b
FB_A19
GLCD_CON
TRAST
IN
F5
F4
E5
E4
F6
PTD12
PTD13
PTD14
PTD15
PTF15
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTD12
PTD13
PTD14
PTD15
PTF15
SPI2_SCK
SPI2_SOUT
SPI2_SIN
FTM3_FLT0
SDHC0_D4
SDHC0_D5
SDHC0_D6
SDHC0_D7
FB_A20
FB_A21
FB_A22
FB_A23
GLCD_PCLK
GLCD_DE
GLCD_HFS
GLCD_VFS
GLCD_D11
SPI2_PCS1
UART0_RTS
_b
E1
PTF16
DISABLED
PTF16
SPI2_PCS0
FTM0_CH3
UART0_CTS GLCD_D12
_b/
UART0_COL
_b
B1
A1
D3
D1
C1
B5
A5
D5
C2
B2
C3
B8
DDR_VDD
DDR_VSS
DDR_DQS1
DDR_DQ8
DDR_DQ9
DDR_VDD
DDR_VSS
DDR_VSS
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_VDD
DDR_VDD
DDR_VSS
DISABLED
DISABLED
DISABLED
DDR_VDD
DDR_VSS
DDR_VSS
DISABLED
DISABLED
DISABLED
DDR_VDD
DDR_VSS
DISABLED
DDR_VDD
DDR_VSS
DDR_DQS1
DDR_DQ8
DDR_DQ9
DDR_VDD
DDR_VSS
DDR_VSS
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_VDD
DDR_VSS
DDR_DQ13
A12 DDR_VSS
C4 DDR_DQ13
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
Freescale Semiconductor, Inc.
87
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
B3
A2
A3
E8
DDR_DQ14
DDR_DQ15
DDR_DM1
DDR_VSS
DISABLED
DISABLED
DISABLED
DDR_VSS
DDR_VDD
DDR_VSS
DDR_VREF
DISABLED
DISABLED
DISABLED
DDR_VDD
DDR_VSS
DISABLED
DISABLED
DISABLED
DISABLED
DDR_VSS
DDR_VDD
DDR_VSS
DISABLED
DISABLED
DISABLED
DISABLED
DDR_VDD
DDR_VSS
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DDR_VDD
DDR_VSS
DISABLED
DISABLED
DISABLED
DISABLED
DDR_VDD
DDR_VSS
DISABLED
DISABLED
DDR_DQ14
DDR_DQ15
DDR_DM1
DDR_VSS
DDR_VDD
DDR_VSS
DDR_VREF
DDR_DQ0
DDR_DQ1
DDR_DQ2
DDR_VDD
DDR_VSS
DDR_DQ3
DDR_DQ4
DDR_DQ5
DDR_ODT
DDR_VSS
DDR_VDD
DDR_VSS
DDR_DQ6
DDR_DQ7
DDR_DQS0
DDR_DM0
DDR_VDD
DDR_VSS
DDR_BA0
DDR_BA1
DDR_BA2
DDR_CKB
DDR_CK
B12 DDR_VDD
A16 DDR_VSS
C6
C5
B4
A4
DDR_VREF
DDR_DQ0
DDR_DQ1
DDR_DQ2
C16 DDR_VDD
C7
B6
D6
A6
A7
DDR_VSS
DDR_DQ3
DDR_DQ4
DDR_DQ5
DDR_ODT
E11 DDR_VSS
D2
C9
B7
A8
C8
D9
D4
DDR_VDD
DDR_VSS
DDR_DQ6
DDR_DQ7
DDR_DQS0
DDR_DM0
DDR_VDD
C14 DDR_VSS
A9 DDR_BA0
B10 DDR_BA1
B9 DDR_BA2
A10 DDR_CKB
A11 DDR_CK
D7
D8
DDR_VDD
DDR_VSS
DDR_VDD
DDR_VSS
DDR_A0
D10 DDR_A0
C11 DDR_A1
B11 DDR_A2
C12 DDR_A3
E10 DDR_VDD
D12 DDR_VSS
C10 DDR_A4
A13 DDR_A5
DDR_A1
DDR_A2
DDR_A3
DDR_VDD
DDR_VSS
DDR_A4
DDR_A5
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Preliminary
88
Freescale Semiconductor, Inc.
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
A14 DDR_A6
D11 DDR_A7
A15 DDR_A8
E12 DDR_VDD
DISABLED
DISABLED
DISABLED
DDR_VDD
DDR_VSS
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DDR_A6
DDR_A7
DDR_A8
DDR_VDD
DDR_VSS
DDR_CKE
DDR_A9
E3
DDR_VSS
B16 DDR_CKE
B15 DDR_A9
B13 DDR_A10
B14 DDR_A11
C15 DDR_A12
D16 DDR_A13
D15 DDR_A14
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_A14
E16 DDR_RAS_
B
DDR_RAS_
B
C13 DDR_CAS_
B
DISABLED
DDR_CAS_
B
D14 DDR_CS_B
DISABLED
DDR_CS_B
DDR_WE_B
D13 DDR_WE_B DISABLED
8.2 K70 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
89
Preliminary
Revision History
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
F
DDR_VSS DDR_DQ15 DDR_DM1 DDR_DQ2 DDR_VSS DDR_DQ5 DDR_ODT DDR_DQ7 DDR_BA0 DDR_CKB DDR_CK DDR_VSS DDR_A5
DDR_A6
DDR_A8 DDR_VSS
A
B
C
D
E
F
DDR_VDD DDR_DQ11 DDR_DQ14 DDR_DQ1 DDR_VDD DDR_DQ3 DDR_DQ6 DDR_VDD DDR_BA2 DDR_BA1 DDR_A2 DDR_VDD DDR_A10 DDR_A11 DDR_A9 DDR_CKE
DDR_DQ9 DDR_DQ10 DDR_DQ12 DDR_DQ13 DDR_DQ0 DDR_VREF DDR_VSS DDR_DQS0 DDR_VSS DDR_A4
DDR_DQ8 DDR_VDD DDR_DQS1 DDR_VDD DDR_VSS DDR_DQ4 DDR_VDD DDR_VSS DDR_DM0 DDR_A0
DDR_A1
DDR_A3 DDR_CAS_B DDR_VSS DDR_A12 DDR_VDD
DDR_A7 DDR_VSS DDR_WE_B DDR_CS_B DDR_A14 DDR_A13
PTC3/
LLWU_P7
PTC4/
PTC5/
PTF16
PTF17
PTF18
PTF19
PTE9
PTE0
DDR_VSS
PTE2/
PTD15
PTD13
PTE5
PTD14
PTD12
PTD11
PTF20
PTD10
PTF15
PTF14
PTF13
PTD7
PTD9
VDD
DDR_VSS
PTD1
VDD
PTC17
PTC16
VDD
DDR_VDD DDR_VSS DDR_VDD
DDR_RAS_B
PTF8
LLWU_P8 LLWU_P9
PTE1/
PTC6/
PTC1/
PTC15
VDD
PTC9
PTC2
PTB21
PTB18
PTB11
PTB8
PTF7
PTB22
PTB19
PTB16
PTB9
PTB7
PTB5
PTB4
PTB2
PTA27
LLWU_P0 LLWU_P1
LLWU_P10 LLWU_P6
PTE4/
G
H
J
PTE3
PTE6
PTE10
PTE17
VSS
PTC10
PTC7
PTC8
PTC12
PTF9
PTB20
PTB17
PTB10
PTC13
PTF1
PTC0
G
H
J
LLWU_P2
PTE7
PTC11/
PTE8
VDDINT
VDD
VSS
VSS
VDDINT
VDD
PTB23
PTF6
LLWU_P11
PTE16
PTE12
VREGIN
PTE19
PTD8
PTD5
PTD3
VSS
VSS
PTC14
PTF11
PTF12
PTB1
PTD6/
PTD4/
PTD2/
K
L
PTE11
VOUT33
PTE27
PTE28
PTE26
VSS
VSS
VSS
VDD
PTF5
K
L
LLWU_P15 LLWU_P14 LLWU_P13
PTD0/
PTE18
VREFL
VSSA
TAMPER1 TAMPER2
TAMPER0/
RTC_
WAKEUP_B
VSS
VDD
PTF10
PTB6
PTF4
LLWU_P12
PTB0/
M
N
P
R
T
USB0_DP USB0_DM
TAMPER7
TAMPER6
TAMPER4
PTC19
PTA1
PTA3
PTC18
PTF22
PTF21
PTF25
PTA12
PTA26
PTA24
PTA10
PTA11
PTB3
PTF3
M
N
P
R
T
LLWU_P5
PGA2_DP/ PGA2_DM/
ADC2_DP0/ ADC2_DM0/
ADC3_DP3/ ADC3_DM3/
ADC0_DP1 ADC0_DM1
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
PTA13/
VDDA
VBAT
PTA16
PTA15
PTA14
PTA8
PTA7
PTA6
PTA29
PTA28
PTA25
PTF2
LLWU_P4
PGA3_DP/ PGA3_DM/
ADC3_DP0/ ADC3_DM0/
ADC2_DP3/ ADC2_DM3/
ADC1_DP1 ADC1_DM1
ADC1_SE16/
CMP2_IN2/ VREFH
ADC0_SE22
PTE24
PTE25
PTF23
PTF24
PTF0
DAC1_OUT/
PGA0_DP/ PGA0_DM/ DAC0_OUT/
ADC0_DP0/ ADC0_DM0/ CMP1_IN3/
ADC1_DP3 ADC1_DM3 ADC0_SE23
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
PTA4/
TAMPER3 TAMPER5
RESET_b
LLWU_P3
VREF_OUT/
PGA1_DP/ PGA1_DM/
CMP1_IN5/
ADC1_DP0/ ADC1_DM0/
CMP0_IN5/
VSS
4
EXTAL32
5
XTAL32
6
PTA0
7
PTA2
8
PTF26
9
PTF27
10
PTA17
11
PTA5
12
PTA9
13
VSS
14
PTA18
15
PTA19
16
ADC0_DP3 ADC0_DM3
ADC1_SE18
1
2
3
Figure 41. K70 256 MAPBGA Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
90
Freescale Semiconductor, Inc.
Preliminary
Revision History
Table 56. Revision History
Rev. No.
Date
6/2011
11/2011
Substantial Changes
1
2
Initial public revision. Corrected USB conditions.
• Added AC electrical specifications.
• Updated Part identification section for 120 MHz CPU frequency.
• Updated Voltage and current operating ratings section.
• Updated Voltage and current operating requirements section.
• Updated LVD and POR operating requirements section.
• Updated Voltage and current operating behaviors section.
• Updated Power mode transition operating behaviors section.
• Updated Power consumption operating behaviors section.
• In Device clock specifications section, updated flash clock frequency and DDR clock
frequency.
• Updated Thermal attributes.
• In MCG specifications section, updated total deviation of trimmed average DCO output
Frequency, PLL reference frequency range, and lock detector detection time.
• In Oscillator frequency specifications section, updated crystal startup time — 32 kHz.
• Updated NFC specifications section.
• Updated DDR controller specifications section.
• In DryIce Tamper Electrical Specifications section, updated supply current.
• In USB DCD electrical specifications section, updated data detect voltage.
• In TSI electrical specifications, updated reference oscillator frequency.
• In LCDC electrical specifications section, updated signal names as per pinouts.
• Updated Pinouts.
• Updated Pinouts.
K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
91
Preliminary
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Document Number: K70P256M150SF3
Rev. 3, 2/2012
Preliminary
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