DSP56301PW80_技术文档

DSP56301

Rev. 10, 7/2006

Freescale Semiconductor

Technical Data

DSP56301

24-Bit Digital Signal Processor

52

6

3

Memory Expansion Area

The DSP56301 is intended

for general-purpose digital

signal processing,

particularly in multimedia

and telecommunication

applications, such as video

conferencing and cellular

telephony.

Y Data

X Data

Program

RAM

Host

Interface

Triple

Timer

ESSI

SCI

RAM

2048 × 24

bits

RAM

2048 × 24

bits

4096 × 24 bits

(Default)

Peripheral

Expansion Area

24

14

External

Address

Bus

Address

Generator

Unit

Six-Channel

DMA Unit

XAB

PAB

DAB

Switch

External

Bus

24-Bit

DSP56300

Core

Interface

and

Boot-

strap

ROM

I-Cache

Control

DDB

YDB

XDB

PDB

GDB

24

External

Data

Bus

Internal

Data

Bus

What’s New?

Rev. 10 includes the following

changes:

Switch

•

Removes all references to

Motorola. No specifications or

part numbers were changed.

Power

EXTAL

XTAL

Management

Clock

Data ALU

Program

Decode

Program

6

+

→

24 × 24 56 56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

JTAG

Interrupt

Address

PLL

2

Controller

Generator

OnCE™

MODD/IRQD

MODC/IRQC

MODB/IRQB

MODA/IRQA

RESET

PINIT/NMI

Figure 1. DSP56301 Block Diagram

The DSP56301 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors

(DSPs). This family uses a high-performance, single clock cycle per instruction engine. Significant architectural

features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The

DSP56301 offers 80/100 MIPS using an internal 80/100 MHz clock at 3.0–3.6 volts. The DSP56300 core family

offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power, enabling

wireless, telecommunications, and multimedia products.

Table of Contents

DSP56301 Features.............................................................................................................................................iii

Target Applications.............................................................................................................................................iv

Product Documentation ......................................................................................................................................iv

Chapter 1

Signals/Connections

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

1.10

1.11

1.12

Power ................................................................................................................................................................1-4

Ground ..............................................................................................................................................................1-4

Clock.................................................................................................................................................................1-5

Phase Lock Loop (PLL)....................................................................................................................................1-5

External Memory Expansion Port (Port A) ......................................................................................................1-6

Interrupt and Mode Control..............................................................................................................................1-9

Host Interface (HI32)......................................................................................................................................1-10

Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-16

Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-18

Serial Communication Interface (SCI) ...........................................................................................................1-19

Timers .............................................................................................................................................................1-20

JTAG/OnCE Interface.....................................................................................................................................1-21

Chapter 2

Specifications

2.1

2.2

2.3

2.4

2.5

Maximum Ratings.............................................................................................................................................2-1

Absolute Maximum Ratings.............................................................................................................................2-2

Thermal Characteristics....................................................................................................................................2-2

DC Electrical Characteristics............................................................................................................................2-2

AC Electrical Characteristics............................................................................................................................2-4

Chapter 3

Chapter 4

Packaging

3.1

3.2

3.3

3.4

TQFP Package Description...............................................................................................................................3-2

TQFP Package Mechanical Drawing..............................................................................................................3-11

MAP-BGA Package Description....................................................................................................................3-12

MAP-BGA Package Mechanical Drawing.....................................................................................................3-23

Design Considerations

4.1

4.2

4.3

4.4

4.5

Thermal Design Considerations........................................................................................................................4-1

Electrical Design Considerations......................................................................................................................4-2

Power Consumption Considerations.................................................................................................................4-3

PLL Performance Issues...................................................................................................................................4-4

Input (EXTAL) Jitter Requirements .................................................................................................................4-4

Chapter A

Index

Power Consumption Benchmark

Data Sheet Conventions

OVERBAR

Indicates a signal that is active when pulled low (For example, the RESET pin is active when

low.)

“asserted”

“deasserted”

Examples:

Means that a high true (active high) signal is high or that a low true (active low) signal is low

Means that a high true (active high) signal is low or that a low true (active low) signal is high

Signal/Symbol

Logic State

Signal State

Asserted

Voltage

V /V

True

IL OL

V

/V

False

True

False

Deasserted

Asserted

Deasserted

IH OH

/V

IH OH

V /V

IL OL

Note: Values for V_IL, V_OL, V_IH, and V_OHare defined by individual product specifications.

DSP56301 Technical Data, Rev. 10

ii

Freescale Semiconductor

DSP56301 Features

High-Performance DSP56300 Core

• 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V

• Object code compatible with the DSP56000 core with highly parallel instruction set

• Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-

Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream

generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support

under software control

• Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes

optimized for DSP applications (including immediate offsets), internal instruction cache

controller, internal memory-expandable hardware stack, nested hardware DO loops, and fast

auto-return interrupts

• Direct Memory Access (DMA) with six DMA channels supporting internal and external

accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-

block-transfer interrupts; and triggering from interrupt lines and all peripherals

• Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock

and output clock with skew elimination

• Hardware debugging support including On-Chip Emulation (OnCE™) module, Joint Test Action

Group (JTAG) Test Access Port (TAP)

Internal Peripherals

• 32-bit parallel PCI/Universal Host Interface (HI32), PCI Rev. 2.1 compliant with glueless

interface to other DSP563xx buses or ISA interface requiring only 74LS45-style buffers

• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three

transmitters (allows six-channel home theater)

• Serial communications interface (SCI) with baud rate generator

• Triple timer module

• Up to forty-two programmable general-purpose input/output (GPIO) pins, depending on which

peripherals are enabled

Internal Memories

• 3 K × 24-bit bootstrap ROM

• 8 K × 24-bit internal RAM total

• Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:

ProgramRAM Instruction Cache

Instruction

Cache

Switch

Mode

X Data RAM Size Y Data RAM Size

Size

4096 × 24 bits

3072 × 24 bits

2048 × 24 bits

1024 × 24 bits

0

2048 × 24 bits

3072 × 24 bits

2048 × 24 bits

3072 × 24 bits

disabled

enabled

disabled

enabled

disabled

enabled

1024 × 24-bit

0

1024 × 24-bit

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

iii

External Memory Expansion

• Data memory expansion to two 16 M × 24-bit word memory spaces in 24-Bit mode or two 64 K

× 16-bit memory spaces in 16-Bit Compatibility mode

• Program memory expansion to one 16 M × 24-bit words memory space in 24-Bit mode or 64 K ×

16-bit in 16-Bit Compatibility mode

• External memory expansion port

• Chip Select Logic for glueless interface to SRAMs

• Internal DRAM Controller for glueless interface to dynamic random access memory (DRAMs)

Reduced Power Dissipation

• Very low-power CMOS design

• Wait and Stop low-power standby modes

• Fully static design specified to operate down to 0 Hz (dc)

• Optimized power management circuitry (instruction-dependent, peripheral-dependent, and

mode-dependent)

Packaging

The DSP56301 is available in a 208-pin thin quad flat pack (TQFP) or a 252-pin molded array

process-ball grid array (MAP-BGA) package. Both packages are available in lead-bearing and

lead-free versions.

Target Applications

Examples of target applications include:

• Wireless and wireline infrastructure applications

• Multi-channel wireless local loop systems

• DSP resource boards

• High-speed modem banks

• Packet telephony

Product Documentation

The three documents listed in the following table are required for a complete description of the

DSP56301 and are necessary to design properly with the part. Documentation is available from the

following sources. (See the back cover for detailed information.)

• A local Freescale distributor

• A Freescale semiconductor sales office

• A Freescale Literature Distribution Center

• The World Wide Web (WWW)

Table 1. DSP56301 Documentation

Name

Description

Order Number

DSP56300 Family

Manual

Detailed description of the DSP56300 family processor core and

instruction set

DSP56300FM/AD

DSP56301 User’s

Manual

Detailed functional description of the DSP56301 memory

configuration, operation, and register programming

DSP56301UM/D

DSP56301

Technical Data

DSP56301 features list and physical, electrical, timing, and

package specifications

DSP56301 Technical Data, Rev. 10

iv

Freescale Semiconductor

Signals/Connections

1

The DSP56301 input and output signals are organized into functional groups, as shown in Table 1-1 and illustrated

in Figure 1-1. The DSP56301 operates from a 3 V supply; however, some of the inputs can tolerate 5 V. A special

notice for this feature is added to the signal descriptions of those inputs.

Table 1-1. DSP56301 Functional Signal Groupings

Number of

Signals by

Package Type

Functional Group

Detailed Description

MAP-

BGA

TQFP

1

Power (V

)

25

26

2

45

38

2

Table 1-2

Table 1-3

Table 1-4

Table 1-5

Table 1-6

Table 1-7

Table 1-8

Table 1-9

Table 1-11

CC

1

Ground (GND)

Clock

PLL

3

Address Bus

Data Bus

Bus Control

24

15

5

24

15

5

2

Port A

Interrupt and Mode Control

Host Interface (HI32)

3

Port B

52

12

52

12

4

Enhanced Synchronous Serial Interface (ESSI)

Ports C and D

Table 1-12 and

Table 1-13

5

Serial Communication Interface (SCI)

Timer

Port E

3

6

3

6

Table 1-14

Table 1-15

Table 1-16

JTAG/OnCE Port

Notes: 1. The number of available power and ground signals is package-dependent. In the TQFP package specific pins are dedicated

internally to device subsystems. In the MAP-BGA package, power and ground connections (except those providing PLL

power) connect to internal power and ground planes, respectively.

2. Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.

3. Port B signals are the HI32 port signals multiplexed with the GPIO signals.

4. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.

5. Port E signals are the SCI port signals multiplexed with the GPIO signals.

6. Each device also includes several no connect (NC) pins. The number of NC connections is package-dependent: the TQFP

has 9 NCs and the MAP-BGA has 20 NCs. Do not connect any line, component, trace, or via to these pins. See Chapter 3

for details.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

1-1

Signals/Connections

DSP56301

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

RESET

1

Interrupt

/Mode

Control

Power Inputs :

V

PLL

CCP

4

6

4

2

6

2

V

Internal Logic

Address Bus

Data Bus

CCQ

V

CCA

V

CCD

V

Bus Control

HI32

ESSI/SCI/Timer

CCN

V

CCH

Universal

Bus

Port B

GPIO

V

CCS

PCI Bus

Host

52

1

See Figure 1-2 for a listing of the

Host Interface/Port B Signals

Grounds :

PLL

Interface

2

GND

P

(HI32) Port

GND

P1

4

Internal Logic

Address Bus

Data Bus

Bus Control

HI32

Q

6

4

2

6

2

A

D

N

H

ESSI/SCI/Timer

S

Port C GPIO

PC[0-2]

PC3

3

Extended Synchronous

Serial Interface Port 0

SC[00-02]

SCK0

SRD0

EXTAL

XTAL

Clock

3

(ESSI0)

PC4

STD0

PC5

CLKOUT

PCAP

PINIT/NMI

PLL

Port D GPIO

PD[0-2]

PD3

PD4

PD5

3

Extended

Synchronous Serial

Interface Port 1

SC[10-12]

SCK1

SRD1

Port A

External

Address Bus

3

(ESSI1)

STD1

24

A[0-23]

D[0-23]

24

4

External

Data Bus

Port E GPIO

PE0

PE1

Serial

RXD

TXD

SCLK

Communications

3

Interface (SCI) Port

AA[0–3]

RAS[0–3]

RD

PE2

External

Bus

WR

BS

TA

BR

Timer GPIO

TIO0

TIO1

Control

TIO0

TIO1

TIO2

4

Timers

TIO2

BG

BB

BL

TCK

TDI

TDO

TMS

TRST

DE

JTAG/OnC

E Port

CAS

BCLK

Notes: 1. Power and ground connections are shown for the TQFP package. The MAP-BGA package uses one

for the PLL power input and 44 V pins that connect to an internal power plane. The MAP-

V

CCP

CC

BGA package uses two ground connections for the PLL (GND and GND ) and 36 GND pins that

P

P1

connect to an internal ground plane.

2. The HI32 port supports PCI and non-PCI bus configurations. Twenty-four HI32 signals can also be

configured as GPIO signals (PB[0–23]).

3. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D

GPIO signals (PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.

4. TIO[0–2] can be configured as GPIO signals.

Figure 1-1. Signals Identified by Functional Group

DSP56301 Technical Data, Rev. 10

1-2

Freescale Semiconductor

Host Port (HP)

DSP56301

PCI Bus

HAD0

Universal Bus

HA3

Port B GPIO

PB0

Reference

HP0

HAD1

HA4

PB1

HP1

HAD2

HA5

PB2

HP2

HAD3

HA6

PB3

HP3

HAD4

HA7

PB4

HP4

HAD5

HA8

PB5

HP5

HAD6

HA9

PB6

HP6

HAD7

HAD8

HA10

HD0

PB7

PB8

HP7

HP8

HAD9

HD1

PB9

HP9

HAD10

HAD11

HAD12

HAD13

HAD14

HAD15

HC0/HBE0

HC1/HBE1

HC2/HBE2

HC3/HBE3

HD2

HD3

HD4

HD5

HD6

HD7

HA0

HA1

PB10

PB11

PB12

PB13

PB14

PB15

PB16

PB17

PB18

PB19

PB20

PB21

PB22

PB23

Internal disconnect

Leave unconnected

HP10

HP11

HP12

HP13

HP14

HP15

HP16

HP17

HP18

HP19

HP20

HP21

HP22

HP23

HP24

HP25

HP26

HP27

HP28

HP29

HP30

HP31

HP32

HP33

HP34

HP35

HP36

HP37

HP38

HP39

HP40

HP41

HP42

HP43

HP44

HP45

HP46

HP47

HP48

HP49

HP50

PVCL

HA2

Tie to pull-up or V

HDBEN

HDBDR

HSAK

HBS

HDAK

HDRQ

HAEN

HTA

CC

Host Interface (HI32)/ HTRDY

HIRDY

HDEVSEL

HLOCK

HPAR

HPERR

HGNT

Port B Signals

HREQ

HSERR

HSTOP

HIDSEL

HFRAME

HCLK

HIRQ

HWR/HRW

HRD/HDS

Tie to pull-up or V

HD8

HD9

HD10

HD11

HD12

HD13

HD14

HD15

HD16

HD17

HD18

HD19

HD20

CC

HAD16

HAD17

HAD18

HAD19

HAD20

HAD21

HAD22

HAD23

HAD24

HAD25

HAD26

HAD27

HAD28

HAD29

HAD30

HAD31

HRST

HD21

HD22

HD23

HRST

HINTA

Leave unconnected

HINTA

PVCL

Note:

HPxx is a reference only and is not a signal name. GPIO references formerly designated as HIOxx have been

renamed PBxx for consistency with other Freescale DSPs.

Figure 1-2. Host Interface/Port B Detail Signal Diagram

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

1-3

Signals/Connections

1.1 Power

Table 1-2. Power Inputs

Power Name

Description

V

PLL Power

Isolated power for the Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided

CCP

CCQ

CCA

CCD

CCN

CCH

CCS

with an extremely low impedance path to the V power rail.

CC

Quiet Power

Isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. The

user must provide adequate external decoupling capacitors.

Address Bus Power

Isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power

inputs. The user must provide adequate external decoupling capacitors.

Data Bus Power

Isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs.

The user must provide adequate external decoupling capacitors.

Bus Control Power

Isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs. The user

must provide adequate external decoupling capacitors.

Host Power

Isolated power for the HI32 I/O drivers. This input must be tied externally to all other chip power inputs. The user must

provide adequate external decoupling capacitors.

ESSI, SCI, and Timer Power

Isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other chip power inputs.

The user must provide adequate external decoupling capacitors.

Note:

These designations are package-dependent. Some packages connect all V inputs except V

to each other internally. On

CC

CCP

those packages, all power input except V

are labeled V

.

CCP

CC

1.2 Ground

Table 1-3. Grounds

Ground Name

Description

GND

PLL Ground

Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground.

should be bypassed to GND by a 0.47 μF capacitor located as close as possible to the chip package.

P

V

CCP

P

GND

PLL Ground 1

P1

Q

Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground.

Quiet Ground

Isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground

connections. The user must provide adequate external decoupling capacitors.

GND

Address Bus Ground

A

D

Isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip

ground connections. The user must provide adequate external decoupling capacitors.

Data Bus Ground

Isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground

connections. The user must provide adequate external decoupling capacitors.

DSP56301 Technical Data, Rev. 10

1-4

Freescale Semiconductor

Clock

Table 1-3. Grounds

Ground Name

Description

GND

Bus Control Ground

N

H

S

Isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground

connections. The user must provide adequate external decoupling capacitors.

Host Ground

Isolated ground for the HI32 I/O drivers. This connection must be tied externally to all other chip ground connections.

The user must provide adequate external decoupling capacitors.

ESSI, SCI, and Timer Ground

Isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be tied externally to all other chip ground

connections. The user must provide adequate external decoupling capacitors.

Note:

These designations are package-dependent. Some packages connect all GND inputs except GND and GND to each other

P P1

internally. On those packages, all ground connections except GND and GND are labeled GND.

P

P1

1.3 Clock

Table 1-4. Clock Signals

State During

Reset

Signal Name

Type

Signal Description

EXTAL

XTAL

Input

External Clock/Crystal Input

Interfaces the internal crystal oscillator input to an external crystal or an

external clock.

Output

Chip-driven

Crystal Output

Connects the internal crystal oscillator output to an external crystal. If an

external clock is used, leave XTAL unconnected.

1.4 Phase Lock Loop (PLL)

Table 1-5. Phase Lock Loop Signals

State During

Reset

Signal Name

Type

Signal Description

CLKOUT

Output

Chip-driven

Clock Output

Provides an output clock synchronized to the internal core clock phase.

If the PLL is enabled and both the multiplication and division factors equal one,

then CLKOUT is also synchronized to EXTAL.

If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.

PCAP

Input

PLL Capacitor

Connects an off-chip capacitor to the PLL filter. Connect one capacitor

terminal to PCAP and the other terminal to V

.

CCP

If the PLL is not used, PCAP can be tied to V , GND, or left floating.

CC

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

1-5

Signals/Connections

Signal Name

Table 1-5. Phase Lock Loop Signals (Continued)

State During

Type

Signal Description

Reset

PINIT/NMI

Input

PLL Initial/Non-Maskable Interrupt

During assertion of RESET, the value of PINIT/NMI is written into the PLL

Enable (PEN) bit of the PLL control register, determining whether the PLL is

enabled or disabled. After RESET deassertion and during normal instruction

processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered

Non-Maskable Interrupt (NMI) request internally synchronized to CLKOUT.

PINIT/NMI can tolerate 5 V.

1.5 External Memory Expansion Port (Port A)

Note: When the DSP56301 enters a low-power stand-by mode (Stop or Wait), it releases bus mastership and tri-

states the relevant Port A signals: A[0–23], D[0–23], AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS, BCLK, and

BCLK. If hardware refresh of external DRAM is enabled, Port A exits the Wait mode to allow the refresh to

occur and then returns to the Wait mode.

1.5.1 External Address Bus

Table 1-6. External Address Bus Signals

State During

Signal Name

Type

Signal Description

Reset

A[0–23]

Output

Tri-stated

Address Bus

When the DSP is the bus master, A[0–23] specify the address for external

program and data memory accesses. Otherwise, the signals are tri-stated. To

minimize power dissipation, A[0–23] do not change state when external

memory spaces are not being accessed.

1.5.2 External Data Bus

Table 1-7. External Data Bus Signals

State During

Reset

Signal Name

Type

Signal Description

D[0–23]

Input/Output

Tri-stated

Data Bus

When the DSP is the bus master, D[0–23] provide the bidirectional data bus

for external program and data memory accesses. Otherwise, D[0–23] are tri-

stated.

DSP56301 Technical Data, Rev. 10

1-6

Freescale Semiconductor

External Memory Expansion Port (Port A)

1.5.3 External Bus Control

Table 1-8. External Bus Control Signals

State During

Reset

Signal Name

Type

Signal Description

AA0/RAS0–

AA3/RAS3

Output

Tri-stated

Address Attribute or Row Address Strobe

As AA, these signals function as chip selects or additional address lines.

Unlike address lines, however, the AA lines do not hold their state after a read

or write operation. As RAS, these signals can be used for Dynamic Random

Access Memory (DRAM) interface. These signals have programmable

polarity.

RD

WR

TA

Output

Input

Tri-stated

Read Enable

When the DSP is the bus master, RD is asserted to read external memory on

the data bus (D[0–23]). Otherwise, RD is tri-stated.

Tri-stated

Write Enable

When the DSP is the bus master, WR is asserted to write external memory on

the data bus (D[0–23]). Otherwise, WR is tri-stated.

Ignored Input

Transfer Acknowledge

If the DSP56301 is the bus master and there is no external bus activity, or the

DSP56301 is not the bus master, the TA input is ignored. The TA input is a

Data Transfer Acknowledge (DTACK) function that can extend an external bus

cycle indefinitely. Any number of wait states (1, 2,..., infinity) can be added to

the wait states inserted by the BCR by keeping TA deasserted. In typical

operation, TA is deasserted at the start of a bus cycle, asserted to enable

completion of the bus cycle, and deasserted before the next bus cycle. The

current bus cycle completes one clock period after TA is asserted

synchronous to CLKOUT. The number of wait states is determined by the TA

input or by the Bus Control Register (BCR), whichever is longer. The BCR can

set the minimum number of wait states in external bus cycles.

To use the TA functionality, the BCR must be programmed to at least one wait

state. A zero wait state access cannot be extended by TA deassertion;

otherwise improper operation may result. TA can operate synchronously or

asynchronously, depending on the setting of the TAS bit in the Operating

Mode Register (OMR).

TA functionality cannot be used during DRAM-type accesses; otherwise

improper operation may result.

BR

Output

Bus Request

(deasserted)

Asserted when the DSP requests bus mastership and deasserted when the

DSP no longer needs the bus. BR can be asserted or deasserted

independently of whether the DSP56301 is a bus master or a bus slave. Bus

“parking” allows BR to be deasserted even though the DSP56301 is the bus

master (see the description of bus “parking” in the BB signal description). The

Bus Request Hole (BRH) bit in the BCR allows BR to be asserted under

software control, even though the DSP does not need the bus. BR is typically

sent to an external bus arbitrator that controls the priority, parking and tenure

of each master on the same external bus. BR is affected only by DSP requests

for the external bus, never for the internal bus. During hardware reset, BR is

deasserted and the arbitration is reset to the bus slave state.

BG

Input

Ignored Input

Bus Grant

Must be asserted/deasserted synchronous to CLKOUT for proper operation.

An external bus arbitration circuit asserts BG when the DSP56301 becomes

the next bus master. When BG is asserted, the DSP56301 must wait until BB

is deasserted before taking bus mastership. When BG is deasserted, bus

mastership is typically given up at the end of the current bus cycle. This may

occur in the middle of an instruction that requires more than one external bus

cycle for execution.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

1-7

Signals/Connections

Signal Name

Table 1-8. External Bus Control Signals (Continued)

State During

Type

Signal Description

Reset

BB

Input/

Output

Input

Bus Busy

Indicates that the bus is active and must be asserted and deasserted

synchronous to CLKOUT. Only after BB is deasserted can the pending bus

master become the bus master (and then assert the signal again). The bus

master can keep BB asserted after ceasing bus activity, regardless of whether

BR is asserted or deasserted. This is called “bus parking” and allows the

current bus master to reuse the bus without re-arbitration until another device

requires the bus. BB is deasserted by an “active pull-up” method (that is, BB is

driven high and then released and held high by an external pull-up resistor).

BB requires an external pull-up resistor.

BL

Output

Driven high

(deasserted)

Bus Lock—BL is asserted at the start of an external divisible Read-Modify-

Write (RMW) bus cycle, remains asserted between the read and write cycles,

and is deasserted at the end of the write bus cycle. This provides an “early bus

start” signal for the bus controller. BL may be used to “resource lock” an

external multi-port memory for secure semaphore updates. Early deassertion

provides an “early bus end” signal useful for external bus control. If the

external bus is not used during an instruction cycle, BL remains deasserted

until the next external indivisible RMW cycle. The only instructions that assert

BL automatically are the BSET, CLR, and BCHG instructions when they are

used to modify external memory. An operation can also assert BL by setting

the BLH bit in the Bus Control Register.

CAS

Output

Tri-stated

Column Address Strobe

When the DSP is the bus master, DRAM uses CAS to strobe the column

address. Otherwise, if the Bus Mastership Enable (BME) bit in the DRAM

Control Register is cleared, the signal is tri-stated.

BCLK

Bus Clock

When the DSP is the bus master, BCLK is active when the OMR[ATE] is set.

When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK

precedes CLKOUT by one-fourth of a clock cycle.

Bus Clock Not

When the DSP is the bus master, BCLK is the inverse of the BCLK signal.

Otherwise, the signal is tri-stated.

DSP56301 Technical Data, Rev. 10

1-8

Freescale Semiconductor

Interrupt and Mode Control

1.6 Interrupt and Mode Control

The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After

RESET is deasserted, these inputs are hardware interrupt request lines.

Table 1-9. Interrupt and Mode Control

State During

Signal Name

Type

Signal Description

Reset

MODA

Input

Mode Select A

Selects the initial chip operating mode during hardware reset and becomes a

level-sensitive or negative-edge-triggered, maskable interrupt request input

IRQA during normal instruction processing. MODA, MODB, MODC, and

MODD select one of sixteen initial chip operating modes, latched into the OMR

when the RESET signal is deasserted.

IRQA

External Interrupt Request A

Internally synchronized to CLKOUT. If IRQA is asserted synchronous to

CLKOUT, multiple processors can be re-synchronized using the WAIT

instruction and asserting IRQA to exit the Wait state. If the processor is in the

Stop stand-by state and IRQA is asserted, the processor exits the Stop state.

These inputs are 5 V tolerant.

MODB

IRQB

Input

Mode Select B

Selects the initial chip operating mode during hardware reset and becomes a

level-sensitive or negative-edge-triggered, maskable interrupt request input

IRQB during normal instruction processing. MODA, MODB, MODC, and

MODD select one of sixteen initial chip operating modes, latched into the OMR

when the RESET signal is deasserted.

External Interrupt Request B

Internally synchronized to CLKOUT. If IRQB is asserted synchronous to

CLKOUT, multiple processors can be re-synchronized using the WAIT

instruction and asserting IRQB to exit the Wait state. If the processor is in the

Stop stand-by state and IRQC is asserted, the processor will exit the Stop

state.

These inputs are 5 V tolerant.

MODC

IRQC

Input

Mode Select C

Selects the initial chip operating mode during hardware reset and becomes a

level-sensitive or negative-edge-triggered, maskable interrupt request input

IRQC during normal instruction processing. MODA, MODB, MODC, and

MODD select one of sixteen initial chip operating modes, latched into the OMR

when the RESET signal is deasserted.

External Interrupt Request C

Internally synchronized to CLKOUT. If IRQC is asserted synchronous to

CLKOUT, multiple processors can be re-synchronized using the WAIT

instruction and asserting IRQC to exit the Wait state. If the processor is in the

Stop stand-by state and IRQC is asserted, the processor exits the Stop state.

These inputs are 5 V tolerant.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

1-9

Signals/Connections

Signal Name

Table 1-9. Interrupt and Mode Control (Continued)

State During

Type

Signal Description

Reset

MODD

Input

Mode Select D

Selects the initial chip operating mode during hardware reset and becomes a

level-sensitive or negative-edge-triggered, maskable interrupt request input

IRQD during normal instruction processing. MODA, MODB, MODC, and

MODD select one of sixteen initial chip operating modes, latched into the OMR

when the RESET signal is deasserted.

IRQD

Input

External Interrupt Request D

Internally synchronized to CLKOUT. If IRQD is asserted synchronous to

CLKOUT, multiple processors can be re-synchronized using the WAIT

instruction and asserting IRQD to exit the Wait state. If the processor is in the

Stop stand-by state and IRQD is asserted, the processor exits the Stop state.

These inputs are 5 V tolerant.

RESET

Input

Reset

Deassertion of RESET is internally synchronized to the clock out (CLKOUT).

When asserted, the chip is placed in the Reset state and the internal phase

generator is reset. The Schmitt-trigger input allows a slowly rising input (such

as a capacitor charging) to reset the chip reliably. If RESET is deasserted

synchronous to CLKOUT, exact start-up timing is guaranteed, allowing

multiple processors to start synchronously and operate together in “lock-step.”

When the RESET signal is deasserted, the initial chip operating mode is

latched from the MODA, MODB, MODC, and MODD inputs. The RESET

signal must be asserted after power-up.

This input is 5 V tolerant.

1.7 Host Interface (HI32)

The Host Interface (HI32) provides fast parallel data to a 32-bit port directly connected to the host bus. The HI32

supports a variety of standard buses and directly connects to a PCI bus and a number of industry-standard

microcomputers, microprocessors, DSPs, and DMA hardware.

1.7.1 Host Port Usage Considerations

Careful synchronization is required when the system reads multiple-bit registers that are written by another

asynchronous system. This is a common problem when two asynchronous systems are connected (as they are in the

Host port). The considerations for proper operation are discussed in Table 1-10.

Table 1-10. Host Port Usage Considerations

Action

Description

Asynchronous read of

receive byte registers

When reading the receive byte registers, Receive register High (RXH), Receive register Middle (RXM), or

Receive register Low (RXL), use interrupts or poll the Receive register Data Full (RXDF) flag that indicates

data is available. This assures that the data in the receive byte registers is valid.

Asynchronous write to

transmit byte registers

Do not write to the transmit byte registers, Transmit register High (TXH), Transmit register Middle (TXM), or

Transmit register Low (TXL), unless the Transmit register Data Empty (TXDE) bit is set, indicating that the

transmit byte registers are empty. This guarantees that the transmit byte registers transfer valid data to the

Host Receive (HRX) register.

DSP56301 Technical Data, Rev. 10

1-10

Freescale Semiconductor

Host Interface (HI32)

Table 1-10. Host Port Usage Considerations (Continued)

Action

Description

Asynchronous write to host

vector

Change the Host Vector (HV) register only when the Host Command bit (HC) is clear. This practice

guarantees that the DSP interrupt control logic receives a stable vector.

1.7.2 Host Port Configuration

HI32 signal functions vary according to the programmed configuration of the interface as determined by the 24-bit

DSP Control Register (DCTR). Refer to the DSP56301 User’s Manual for details on HI32 configuration registers.

Table 1-11. Host Interface

State During

Signal Name

Type

Signal Description

Reset

HAD[0–7]

Input/Output

Tri-stated

Host Address/Data 0–7

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, these signals are lines 0–7 of the Address/Data bus.

HA[3–10]

PB[0–7]

Input

Host Address 3–10

When HI32 is programmed to interface with a universal, non-PCI bus and the

HI function is selected, these signals are lines 3–10 of the Address bus.

Input or Output

Port B 0–7

When the HI32 is configured as GPIO through the DCTR, these signals are

individually programmed through the HI32 Data Direction Register (DIRH).

These inputs are 5 V tolerant.

HAD[8–15]

HD[0–7]

Input/Output

Input or Output

Tri-stated

Host Address/Data 8–15

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, these signals are lines 8–15 of the Address/Data bus.

Host Data 0–7

When HI32 is programmed to interface with a universal non-PCI bus and the

HI function is selected, these signals are lines 0–7 of the Data bus.

PB[8–15]

Port B 8–15

When the HI32 is configured as GPIO through the DCTR, these signals are

individually programmed through the HI32 DIRH.

These inputs are 5 V tolerant.

HC[0–3]/

HBE[0–3]

Input/Output

Input

Tri-stated

Command 0–3/Byte Enable 0–3

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, these signals are lines 0–7 of the Address/Data bus.

HA[0–2]

Host Address 0–2

When HI32 is programmed to interface with a universal, non-PCI bus and the

HI function is selected, these signals are lines 0–2 of the Address bus.

The fourth signal in this set should connect to a pull-up resistor or directly to

V

when a non-PCI bus is used.

CC

PB[16–19]

Input or Output

Port B 16–19

When the HI32 is configured as GPIO through the DCTR, these signals are

individually programmed through the HI32 DIRH.

These inputs are 5 V tolerant.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

1-11

Signals/Connections

Signal Name

Table 1-11. Host Interface (Continued)

State During

Type

Signal Description

Reset

HTRDY

HDBEN

PB20

Input/

Output

Tri-stated

Host Target Ready

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, this is the Host Target Ready signal.

Output

Host Data Bus Enable

When HI32 is programmed to interface with a universal, non-PCI bus and the

HI function is selected, this is the Host Data Bus Enable signal.

Input or Output

Port B 20

When the HI32 is configured as GPIO through the DCTR, this signal is

individually programmed through the HI32 DIRH.

This input is 5 V tolerant.

HIRDY

HDBDR

PB21

Input/

Output

Tri-stated

Host Initiator Ready

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, this is the Host Initiator Ready signal.

Output

Host Data Bus Direction

When HI32 is programmed to interface with a universal, non-PCI bus and the

HI function is selected, this is the Host Data Bus Direction signal.

Input or Output

Port B 21

When the HI32 is configured as GPIO through the DCTR, this signal is

individually programmed through the HI32 DIRH.

This input is 5 V tolerant.

HDEVSEL

HSAK

Input/

Output

Host Device Select

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, this is the Host Device Select signal.

Output

Host Select Acknowledge

When HI32 is programmed to interface with a universal, non-PCI bus and the

HI function is selected, this is the Host Select Acknowledge signal.

PB22

Input or Output

Port B 22

When the HI32 is configured as GPIO through the DCTR, this signal is

individually programmed through the HI32 DIRH.

This input is 5 V tolerant.

HLOCK

HBS

Input

Host Lock

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, this is the Host Lock signal.

Input

Host Bus Strobe

When HI32 is programmed to interface with a universal, non-PCI bus and the

HI function is selected, this is the Host Bus Strobe Schmitt-trigger signal.

PB23

Input or Output

Port B 23

When the HI32 is configured as GPIO through the DCTR, this signal is

individually programmed through the HI32 DIRH.

This input is 5 V tolerant.

DSP56301 Technical Data, Rev. 10

1-12

Freescale Semiconductor

Host Interface (HI32)

Table 1-11. Host Interface (Continued)

State During

Signal Name

Type

Signal Description

Reset

HPAR

Input/

Tri-stated

Host Parity

Output

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, this is the Host Parity signal.

HDAK

Input

Host DMA Acknowledge

When HI32 is programmed to interface with a universal, non-PCI bus and the

HI function is selected, this is the Host DMA Acknowledge Schmitt-trigger

signal.

Port B

When the HI32 is configured as GPIO through the DCTR, this signal is

internally disconnected.

This input is 5 V tolerant.

HPERR

HDRQ

Input/

Output

Tri-stated

Host Parity Error

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, this is the Host Parity Error signal.

Output

Host DMA Request

When HI32 is programmed to interface with a universal, non-PCI bus and the

HI function is selected, this is the Host DMA Request output.

Port B

When the HI32 is configured as GPIO through the DCTR, this signal is

internally disconnected.

This input is 5 V tolerant.

HGNT

HAEN

Input

Host Bus Grant

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, this is the Host Bus Grant signal.

Host Address Enable

When HI32 is programmed to interface with a universal, non-PCI bus and the

HI function is selected, this is the Host Address Enable output signal.

Port B

When the HI32 is configured as GPIO through the DCTR, this signal is

internally disconnected.

This input is 5 V tolerant.

HREQ

HTA

Output

Tri-stated

Host Bus Request

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, this is the Host Bus Request signal.

Host Transfer Acknowledge—When HI32 is programmed to interface with a

universal, non-PCI bus and the HI function is selected, this is the Host Data

Bus Enable signal. HTA can be programmed as active high or active low.

Port B

When the HI32 is configured as GPIO through the DCTR, this signal is

internally disconnected.

This input is 5 V tolerant.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

1-13

Signals/Connections

Signal Name

Table 1-11. Host Interface (Continued)

State During

Type

Signal Description

Reset

HSERR

HIRQ

Output, open

drain

Tri-stated

Host System Error

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, this is the Host System Error signal.

Output, open

drain

Host Interrupt Request

When HI32 is programmed to interface with a universal, non-PCI bus and the

HI function is selected, this is the Host Interrupt Request signal.

Port B

When the HI32 is configured as GPIO through the DCTR, this signal is

internally disconnected.

This input is 5 V tolerant.

HSTOP

Input/

Tri-stated

Host Stop

Output

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, this is the Host Stop signal.

HWR/HRW

Input

Host Write/Host Read-Write

When HI32 is programmed to interface with a universal, non-PCI bus and the

HI function is selected, this is the Host Write/Host Read-Write Schmitt-trigger

signal.

Port B

When the HI32 is configured as GPIO through the DCTR, this signal is

internally disconnected.

This input is 5 V tolerant.

HIDSEL

Input

Host Initialization Device Select

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, this is the Host Initialization Device Select signal.

HRD/HDS

Host Read/Host Data Strobe

When HI32 is programmed to interface with a universal, non-PCI bus and the

HI function is selected, this is the Host Data Read/Host Data Strobe Schmitt-

trigger signal.

Port B

When the HI32 is configured as GPIO through the DCTR, this signal is

internally disconnected.

This input is 5 V tolerant.

HFRAME

Input/

Tri-stated

Host Frame

Output

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, this is the Host cycle Frame signal.

Non-PCI bus

When HI32 is programmed to interface with a universal, non-PCI bus and the

HI function is selected, this signal must be connected to a pull-up resistor or

directly to V

.

CC

Port B

When the HI32 is configured as GPIO through the DCTR, this signal is

internally disconnected.

This input is 5 V tolerant.

DSP56301 Technical Data, Rev. 10

1-14

Freescale Semiconductor

Host Interface (HI32)

Table 1-11. Host Interface (Continued)

State During

Signal Name

Type

Signal Description

Reset

HCLK

Input

Host Clock

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, this is the Host Bus Clock input.

Non-PCI bus

When HI32 is programmed to interface a universal non-PCI bus and the HI

function is selected, this signal must be connected to a pull-up resistor or

directly to V

.

CC

Port B

When the HI32 is configured as GPIO through the DCTR, this signal is

internally disconnected.

This input is 5 V tolerant.

HAD[16–31]

HD[8–23]

Input/Output

Tri-stated

Host Address/Data 16–31

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, these signals are lines 16–31 of the Address/Data bus.

Host Data 8–23

When HI32 is programmed to interface with a universal, non-PCI bus and the

HI function is selected, these signals are lines 8–23 of the Data bus.

Port B

When the HI32 is configured as GPIO through the DCTR, these signals are

internally disconnected.

These inputs are 5 V tolerant.

HRST

Input

Tri-stated

Hardware Reset

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected, this is the Hardware Reset input.

Hardware Reset

When HI32 is programmed to interface with a universal, non-PCI bus and the

HI function is selected, this is the Hardware Reset Schmitt-trigger signal.

Port B

When the HI32 is configured as GPIO through the DCTR, this signal is

internally disconnected.

This input is 5 V tolerant.

HINTA

Output, open

drain

Tri-stated

Host Interrupt A

When the HI function is selected, this signal is the Interrupt A open-drain

output.

Port B

When the HI32 is configured as GPIO through the DCTR, this signal is

internally disconnected.

This input is 5 V tolerant.

PVCL

Input

PCI Voltage Clamp

When the HI32 is programmed to interface with a PCI bus and the HI function

is selected and the PCI bus uses a 3 V signal environment, connect this pin to

V

(3.3 V) to enable the high voltage clamping required by the PCI

CC

specifications. In all other cases, including a 5 V PCI signal environment, leave

the input unconnected.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

1-15

Signals/Connections

1.8 Enhanced Synchronous Serial Interface 0 (ESSI0)

Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication

with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and

peripherals that implement the Serial Peripheral Interface (SPI).

Table 1-12. Enhanced Synchronous Serial Interface 0 (ESSI0)

State During

Signal Name

Type

Signal Description

Reset

SC00

Input or Output

Input

Serial Control 0

Functions in either Synchronous or Asynchronous mode. For Asynchronous

mode, this signal is the receive clock I/O (Schmitt-trigger input). For

Synchronous mode, this signal is either for Transmitter 1 output or Serial I/O

Flag 0.

PC0

Port C 0

The default configuration following reset is GPIO. For PC0, signal direction is

controlled through the Port Directions Register (PRR0). The signal can be

configured as ESSI signal SC00 through the Port Control Register (PCR0).

This input is 5 V tolerant.

SC01

PC1

Input/Output

Input

Serial Control 1

Functions in either Synchronous or Asynchronous mode. For Asynchronous

mode, this signal is the receiver frame sync I/O. For Synchronous mode, this

signal is either Transmitter 2 output or Serial I/O Flag 1.

Input or Output

Port C 1

The default configuration following reset is GPIO. For PC1, signal direction is

controlled through PRR0. The signal can be configured as an ESSI signal

SC01 through PCR0.

This input is 5 V tolerant.

SC02

Input/Output

Input

Serial Control Signal 2

The frame sync for both the transmitter and receiver in Synchronous mode,

and for the transmitter only in Asynchronous mode. When configured as an

output, this signal is the internally generated frame sync signal. When

configured as an input, this signal receives an external frame sync signal for

the transmitter (and the receiver in synchronous operation).

PC2

Input or Output

Port C 2

The default configuration following reset is GPIO. For PC2, signal direction is

controlled through PRR0. The signal can be configured as an ESSI signal

SC02 through PCR0.

This input is 5 V tolerant.

DSP56301 Technical Data, Rev. 10

1-16

Freescale Semiconductor

Enhanced Synchronous Serial Interface 0 (ESSI0)

Table 1-12. Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)

State During

Reset

Signal Name

Type

Signal Description

SCK0

Input/Output

Input

Serial Clock

Provides the serial bit rate clock for the ESSI interface for both the transmitter

and receiver in Synchronous modes, or the transmitter only in Asynchronous

modes.

Although an external serial clock can be independent of and asynchronous to

the DSP system clock, it must exceed the minimum clock cycle time of 6 T

(that is, the system clock frequency must be at least three times the external

ESSI clock frequency). The ESSI needs at least three DSP phases inside

each half of the serial clock.

PC3

Input or Output

Port C 3

The default configuration following reset is GPIO. For PC3, signal direction is

controlled through PRR0. The signal can be configured as an ESSI signal

SCK0 through PCR0.

This input is 5 V tolerant.

SRD0

PC4

Input/Output

Input

Serial Receive Data

Receives serial data and transfers the data to the ESSI receive shift register.

SRD0 is an input when data is being received.

Input or Output

Port C 4

The default configuration following reset is GPIO. For PC4, signal direction is

controlled through PRR0. The signal can be configured as an ESSI signal

SRD0 through PCR0.

This input is 5 V tolerant.

STD0

PC5

Input/Output

Input

Serial Transmit Data

Transmits data from the serial transmit shift register. STD0 is an output when

data is being transmitted.

Input or Output

Port C 5

The default configuration following reset is GPIO. For PC5, signal direction is

controlled through PRR0. The signal can be configured as an ESSI signal

STD0 through PCR0.

This input is 5 V tolerant.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

1-17

Signals/Connections

1.9 Enhanced Synchronous Serial Interface 1 (ESSI1)

Table 1-13. Enhanced Synchronous Serial Interface 1 (ESSI1)

State During

Signal Name

Type

Signal Description

Reset

SC10

Input or Output

Input

Serial Control 0

Selection of Synchronous or Asynchronous mode determines function. For

Asynchronous mode, this signal is the receive clock I/O (Schmitt-trigger input).

For Synchronous mode, this signal is either Transmitter 1 output or Serial I/O

Flag 0.

PD0

Port D 0

The default configuration following reset is GPIO. For PD0, signal direction is

controlled through the Port Directions Register (PRR1). The signal can be

configured as an ESSI signal SC10 through the Port Control Register (PCR1).

This input is 5 V tolerant.

SC11

PD1

Input/Output

Serial Control 1

Selection of Synchronous or Asynchronous mode determines function. For

Asynchronous mode, this signal is the receiver frame sync I/O. For

Synchronous mode, this signal is either Transmitter 2 output or Serial I/O Flag

1.

Input or Output

Port D 1

The default configuration following reset is GPIO. For PD1, signal direction is

controlled through PRR1. The signal can be configured as an ESSI signal

SC11 through PCR1.

This input is 5 V tolerant.

SC12

Input/Output

Input or Output

Input/Output

Serial Control Signal 2

Frame sync for both the transmitter and receiver in Synchronous mode, for the

transmitter only in Asynchronous mode. When configured as an output, this

signal is the internally generated frame sync signal. When configured as an

input, this signal receives an external frame sync signal for the transmitter (and

the receiver in Synchronous operation).

PD2

Port D 2

The default configuration following reset is GPIO. For PD2, signal direction is

controlled through PRR1. The signal can be configured as an ESSI signal

SC12 through PCR1.

This input is 5 V tolerant.

SCK1

Input

Serial Clock

Provides the serial bit rate clock for the ESSI interface. Clock input or output

can be used by the transmitter and receiver in Synchronous modes, by the

transmitter only in Asynchronous modes.

Although an external serial clock can be independent of and asynchronous to

the DSP system clock, it must exceed the minimum clock cycle time of 6T (that

is, the system clock frequency must be at least three times the external ESSI

clock frequency). The ESSI needs at least three DSP phases inside each half

of the serial clock.

PD3

Input or Output

Port D 3

The default configuration following reset is GPIO. For PD3, signal direction is

controlled through PRR1. The signal can be configured as an ESSI signal

SCK1 through PCR1.

This input is 5 V tolerant.

DSP56301 Technical Data, Rev. 10

1-18

Freescale Semiconductor

Serial Communication Interface (SCI)

Table 1-13. Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued)

State During

Reset

Signal Name

Type

Signal Description

SRD1

Input/Output

Input

Serial Receive Data

Receives serial data and transfers it to the ESSI receive shift register. SRD1 is

an input when data is being received.

PD4

Input or Output

Port D 4

The default configuration following reset is GPIO. For PD4, signal direction is

controlled through PRR1. The signal can be configured as an ESSI signal

SRD1 through PCR1.

This input is 5 V tolerant.

STD1

PD5

Input/Output

Input

Serial Transmit Data

Transmits data from the serial transmit shift register. STD1 is an output when

data is being transmitted.

Input or Output

Port D 5

The default configuration following reset is GPIO. For PD5, signal direction is

controlled through PRR1. The signal can be configured as an ESSI signal

STD1 through PCR1.

This input is 5 V tolerant.

1.10 Serial Communication Interface (SCI)

The Serial Communication interface (SCI) provides a full duplex port for serial communication with other DSPs,

microprocessors, or peripherals such as modems.

Table 1-14. Serial Communication Interface (SCI)

State During

Signal Name

Type

Signal Description

Reset

RXD

Input

Serial Receive Data

Receives byte-oriented serial data and transfers it to the SCI receive shift

register.

PE0

Input or Output

Port E 0

The default configuration following reset is GPIO. When configured as PE0,

signal direction is controlled through the SCI Port Directions Register (PRR).

The signal can be configured as an SCI signal RXD through the SCI Port

Control Register (PCR).

This input is 5 V tolerant.

TXD

PE1

Output

Input

Serial Transmit Data

Transmits data from SCI transmit data register.

Input or Output

Port E 1

The default configuration following reset is GPIO. When configured as PE1,

signal direction is controlled through the SCI PRR. The signal can be

configured as an SCI signal TXD through the SCI PCR.

This input is 5 V tolerant.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

1-19

Signals/Connections

Signal Name

Table 1-14. Serial Communication Interface (SCI) (Continued)

State During

Type

Signal Description

Reset

SCLK

PE2

Input/Output

Input

Serial Clock

Provides the input or output clock used by the transmitter and/or the receiver.

Input or Output

Port E 2

The default configuration following reset is GPIO. For PE2, signal direction is

controlled through the SCI PRR. The signal can be configured as an SCI

signal SCLK through the SCI PCR.

This input is 5 V tolerant.

1.11 Timers

The DSP56301 has three identical and independent timers. Each can use internal or external clocking, interrupt the

DSP56301 after a specified number of events (clocks), or signal an external device after counting a specific number

of internal events.

Table 1-15. Triple Timer Signals

State During

Signal Name

Type

Signal Description

Reset

TIO0

Input or Output

Input

Timer 0 Schmitt-Trigger Input/Output

As an external event counter or in Measurement mode, TIO0 is input. In

Watchdog, Timer, or Pulse Modulation mode, TIO0 is output.

The default mode after reset is GPIO input. This can be changed to output or

configured as a Timer Input/Output through the Timer 0 Control/Status

Register (TCSR0).

This input is 5 V tolerant.

TIO1

Input or Output

Timer 1 Schmitt-Trigger Input/Output

As an external event counter or in Measurement mode, TIO1 is input. In

Watchdog, Timer, or Pulse Modulation mode, TIO1 is output.

The default mode after reset is GPIO input. This can be changed to output or

configured as a Timer Input/Output through the Timer 1 Control/Status

Register (TCSR1).

This input is 5 V tolerant.

TIO2

Input or Output

Timer 2 Schmitt-Trigger Input/Output

As an external event counter or in Measurement mode, TIO2 is input. In

Watchdog, Timer, or Pulse Modulation mode, TIO2 is output.

The default mode after reset is GPIO input. This can be changed to output or

configured as a Timer Input/Output through the Timer 2 Control/Status

Register (TCSR2).

This input is 5 V tolerant.

DSP56301 Technical Data, Rev. 10

1-20

Freescale Semiconductor

JTAG/OnCE Interface

1.12 JTAG/OnCE Interface

Table 1-16. JTAG/OnCE Interface

State During

Reset

Signal Name

Type

Signal Description

TCK

Input

Test Clock

A test clock signal for synchronizing JTAG test logic.

This input is 5 V tolerant.

TDI

Test Data Input

A test data serial signal for test instructions and data. TDI is sampled on the

rising edge of TCK and has an internal pull-up resistor.

This input is 5 V tolerant.

TDO

Output

Tri-stated

Test Data Output

A test data serial signal for test instructions and data. TDO can be tri-stated.

The signal is actively driven in the shift-IR and shift-DR controller states and

changes on the falling edge of TCK.

This input is 5 V tolerant.

TMS

TRST

DE

Input

Test Mode Select

Sequences the test controller’s state machine, is sampled on the rising edge of

TCK, and has an internal pull-up resistor.

This input is 5 V tolerant.

Input

Test Reset

Asynchronously initializes the test controller, has an internal pull-up resistor,

and must be asserted after power up.

This input is 5 V tolerant.

Input/Output

Debug Event

Provides a way to enter Debug mode from an external command controller (as

input) or to acknowledge that the chip has entered Debug mode (as output).

When asserted as an input, DE causes the DSP56300 core to finish the

current instruction, save the instruction pipeline information, enter Debug

mode, and wait for commands from the debug serial input line. When a debug

request or a breakpoint condition causes the chip to enter Debug mode, DE is

asserted as an output for three clock cycles. DE has an internal pull-up

resistor.

DE is not a standard part of the JTAG Test Access Port (TAP) Controller. It

connects to the OnCE module to initiate Debug mode directly or to provide a

direct external indication that the chip has entered the Debug mode. All other

interface with the OnCE module must occur through the JTAG port.

This input is 5 V tolerant.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

1-21

Signals/Connections

DSP56301 Technical Data, Rev. 10

1-22

Freescale Semiconductor

Specifications

2

The DSP56301 is fabricated in high-density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs.

2.1 Maximum Ratings

CAUTION

This device contains circuitry protecting

against damage due to high static voltage or

electrical fields; however, normal precautions

should be taken to avoid exceeding maximum

voltage ratings. Reliability is enhanced if

unused inputs are tied to an appropriate logic

voltage level (for example, either GND or V ).

CC

Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum

value of another specification does not yield a reasonable sum. A maximum specification is calculated

using a worst case variation of process parameter values in one direction. The minimum specification is

calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum”

value for a specification never occurs in the same device that has a “minimum” value for another

specification; adding a maximum to a minimum represents a condition that can never exist.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-1

Specifications

2.2 Absolute Maximum Ratings

Table 2-1. Maximum Ratings

Rating¹

Symbol

Value^{1, 2}

Unit

Supply Voltage

V

–0.3 to +4.0

V

CC

3

All input voltages excluding “5 V tolerant” inputs

V

GND – 0.3 to V + 0.3

CC

IN

3

All “5 V tolerant” input voltages

GND – 0.3 to V + 3.95

V

IN5

CC

Current drain per pin excluding V and GND

I

10

mA

°C

CC

Operating temperature range

Storage temperature

T

–40 to +100

–55 to +150

J

T

STG

Notes: 1. GND = 0 V, V = 3.3 V 0.3 V, T = –40°C to +100°C, CL = 50 pF

CC

J

2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress

beyond the maximum rating may affect device reliability or cause permanent damage to the device.

3. CAUTION: All “5 V Tolerant” input voltages cannot be more than 3.95 V greater than the supply voltage; this restriction

applies to “power on,” as well as during normal operation. In any case, the input voltages must not be higher than 5.75 V. “5

V Tolerant” inputs are inputs that tolerate 5 V.

2.3 Thermal Characteristics

Table 2-2. Thermal Characteristics

TQFP

Value

PBGA³

Value

PBGA⁴

Value

Characteristic

Symbol

Unit

1

Junction-to-ambient thermal resistance

R

or θ

49.5

7.2

48.4

9

25.2

—

°C/W

θJA

JA

JC

2

Junction-to-case thermal resistance

R

θJC

Thermal characterization parameter

Ψ

4.7

5

—

JT

Notes: 1. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per

JEDEC Specification JESD51-3.

2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that

the cold plate temperature is used for the case temperature.

3. These are simulated values. See note 1 for test board conditions.

4. These are simulated values. The test board has two 2-ounce signal layers and two 1-ounce solid ground planes internal to

the test board.

2.4 DC Electrical Characteristics

Table 2-3. DC Electrical Characteristics⁶

Characteristics

Symbol

Min

Typ

Max

Unit

Supply voltage

V

3.0

3.3

3.6

V

CC

DSP56301 Technical Data, Rev. 10

2-2

Freescale Semiconductor

DC Electrical Characteristics

Table 2-3. DC Electrical Characteristics⁶(Continued)

Characteristics

Symbol

Min

Typ

Max

Unit

Input high voltage

•

D[0–23], BG, BB, TA

V

2.0

—

V

5.25

V

IH

CC

1

MOD /IRQ , RESET, PINIT/NMI and all

JTAG/ESSI/SCI/Timer/HI32 pins

V

IHP

8

•

EXTAL

V

0.8 × V

—

V

IHX

CC

Input low voltage

1

•

D[0–23], BG, BB, TA, MOD /IRQ , RESET, PINIT

V

–0.3

—

0.8

0.2 × V

V

IL

All JTAG/ESSI/SCI/Timer/HI32 pins

V

ILP

ILX

8

EXTAL

CC

Input leakage current

I

–10

—

10

μA

IN

High impedance (off-state) input current (@ 2.4 V / 0.4 V)

TSI

Output high voltage

V

OH

5,7

•

TTL (I

CMOS (I = –10 μA)

= –0.4 mA)

2.4

– 0.01

CC

—

V

OH

5

V

OH

Output low voltage

V

OL

5,7

•

TTL (I = 1.6 mA, open-drain pins I = 6.7 mA)

—

0.4

0.01

V

OL

5

CMOS (I = 10 μA)

OL

2

Internal supply current :

80 MHz

102

6

100

100 MHz

127

7.5

•

In Normal mode

I

—

mA

μA

CCI

3

In Wait mode

I

CCW

4

In Stop mode

I

100

CCS

PLL supply current

—

1

2.5

10

mA

pF

5

Input capacitance

C

—

IN

Notes: 1. Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins.

2. Power Consumption Considerations on page 4-3 provides a formula to compute the estimated current requirements in

Normal mode. To obtain these results, all inputs must be terminated (that is, not allowed to float). Measurements are based on

synthetic intensive DSP benchmarks (see Appendix A). The power consumption numbers in this specification are 90 percent

of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured

with V = 3.0 V at T = 100°C.

CC

J

3. To obtain these results, all inputs must be terminated (that is, not allowed to float).

4. To obtain these results, all inputs that are not disconnected at Stop mode must be terminated (that is, not allowed to float). PLL

and XTAL signals are disabled during Stop state.

5. Periodically sampled and not 100 percent tested.

6.

7. This characteristic does not apply to XTAL and PCAP.

8. Driving EXTAL to the low V or the high V value may cause additional power consumption (DC current). To minimize

V

= 3.3 V 0.3 V; T = –40°C to +100 °C, C = 50 pF

CC J L

IHX

ILX

power consumption, the minimum V

should be no lower than

IHX

0.9 × V and the maximum V

should be no higher than 0.1 × V

.

CC

ILX

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-3

Specifications

2.5 AC Electrical Characteristics

The timing waveforms shown in the AC electrical characteristics section are tested with a V maximum of 0.3 V

IL

and a V minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of

IH

Table 2-3. AC timing specifications, which are referenced to a device input signal, are measured in production with

respect to the 50 percent point of the respective input signal’s transition.

Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15

MHz and rated speed.

All specifications for the high impedance state are guaranteed by design.

2.5.1 Internal Clocks

Table 2-4. Internal Clocks, CLKOUT

Expression^{1, 2}

Characteristics

Symbol

Min

Typ

Max

Internal operation frequency and CLKOUT with PLL enabled

f

—

(Ef × MF)/

(PDF × DF)

—

Internal operation frequency and CLKOUT with PLL disabled

Internal clock and CLKOUT high period

—

Ef/2

—

•

With PLL disabled

With PLL enabled and MF ≤ 4

T

—

ET

—

H

C

0.49 × ET

×

0.51 × ET ×

C

PDF × DF/MF

0.53 × ET

•

With PLL enabled and MF > 4

0.47 × ET

×

—

×

C

PDF × DF/MF

Internal clock and CLKOUT low period

•

With PLL disabled

With PLL enabled and MF ≤ 4

T

—

ET

—

L

C

0.49 × ET

×

0.51 × ET ×

C

PDF × DF/MF

0.53 × ET

•

With PLL enabled and MF > 4

0.47 × ET

×

—

×

C

PDF × DF/MF

Internal clock and CLKOUT cycle time with PLL enabled

T

—

ET

PDF ×

DF/MF

×

C

—

C

Internal clock and CLKOUT cycle time with PLL disabled

Instruction cycle time

T

—

2 × ET

—

C

I

—

T

—

CYC

C

Notes: 1. DF = Division Factor; Ef = External frequency; ET = External clock cycle = 1/Ef;

C

MF = Multiplication Factor; PDF = Predivision Factor; T = Internal clock cycle

C

2. See the PLL and Clock Generator section in the DSP56300 Family Manual for details on the PLL.

DSP56301 Technical Data, Rev. 10

2-4

Freescale Semiconductor

AC Electrical Characteristics

2.5.2 External Clock Operation

The DSP56301 system clock is derived from the on-chip oscillator or it is externally supplied. To use the on-chip

oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; examples are

shown in Figure 2-1.

EXTAL

XTAL

Suggested Component Values:

f = 4 MHz

OSC

R

f

= 20 MHz

OSC

R = 680 kΩ 10%

C = 56 pF 20%

Note: Make sure that in

the PCTL Register:

R = 680 kΩ 10%

C = 22 pF 20%

•

XTLD (bit 16) = 0

If f > 200 kHz,

XTLR (bit 15) = 0

Calculations were done for a 4/20 MHz crystal

with the following parameters:

OSC

C

XTAL1

C

•

C of 30/20 pF,

L

Fundamental Frequency

Crystal Oscillator

C of 7/6 pF,

0

series resistance of 100/20 Ω, and

drive level of 2 mW.

Figure 2-1. Crystal Oscillator Circuits

If an externally supplied square wave voltage source is used, disable the internal oscillator circuit during boot-up

by setting XTLD (PCTL Register bit 16 = 1—see the DSP56301 User’s Manual). The external square wave source

connects to EXTAL; XTAL is not physically connected to the board or socket. Figure 2-2 shows the relationship

between the EXTAL input and the internal clock and CLKOUT.

V

Midpoint

IHX

EXTAL

ET

H

V

L

Note:

The midpoint is

0.5 (V + V ).

ILX

2

3

IHX

ILX

4

ET

C

5

CLKOUT with

PLL disabled

7

CLKOUT with

PLL enabled

7

6a

6b

Figure 2-2. External Clock Timing

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-5

Specifications

Table 2-5. Clock Operation

80 MHz

100 MHz

No.

Characteristics

Symbol

Min

Max

Min

Max

1

2

Frequency of EXTAL (EXTAL Pin Frequency)

The rise and fall time of this external clock should be 3 ns maximum.

Ef

0

80.0 MHz

0

100.0 MHz

1, 2

EXTAL input high

6

•

With PLL disabled (46.7%–53.3% duty cycle )

With PLL enabled (42.5%–57.5% duty cycle )

ET

5.84 ns

5.31 ns

∞

4.67 ns

4.25 ns

∞

H

6

157.0 μs

1, 2

3

4

EXTAL input low

•

6

With PLL disabled (46.7%–53.3% duty cycle )

With PLL enabled (42.5%–57.5% duty cycle )

ET

5.84 ns

5.31 ns

∞

4.67 ns

4.25 ns

∞

L

6

157.0 μs

2

EXTAL cycle time

•

With PLL disabled

With PLL enabled

ET

12.50 ns

∞

10.00 ns

∞

C

273.1 μs

5

6

CLKOUT change from EXTAL fall with PLL disabled

4.3 ns

0.0 ns

11.0 ns

1.8 ns

4.3 ns

0.0 ns

11.0 ns

1.8 ns

a. CLKOUT rising edge from EXTAL rising edge with PLL enabled (MF

3,5

= 1 or 2 or 4, PDF = 1, Ef > 15 MHz)

b. CLKOUT falling edge from EXTAL falling edge with PLL enabled (MF

≤ 4, PDF ≠ 1, Ef / PDF > 15 MHz)

0.0 ns

1.8 ns

0.0 ns

1.8 ns

3,5

4

7

Instruction cycle time = I

= T

CYC C

(see Table 2-4) (46.7%–53.3% duty cycle)

•

With PLL disabled

With PLL enabled

I

25.0 ns

12.50 ns

∞

20.0 ns

10.00 ns

∞

CYC

8.53 μs

Notes: 1. Measured at 50 percent of the input transition

2. The maximum value for PLL enabled is given for minimum VCO frequency (see Table 2-6) and maximum MF.

3. Periodically sampled and not 100 percent tested

4. The maximum value for PLL enabled is given for minimum VCO frequency and maximum DF.

5. The skew is not guaranteed for any other MF value.

6. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time

required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock

frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time

requirements are met.

2.5.3 Phase Lock Loop (PLL) Characteristics

Table 2-6. PLL Characteristics

80 MHz

100 MHz

Characteristics

Unit

Min

Max

Min

Max

Voltage Controlled Oscillator (VCO) frequency when PLL

30

160

30

200

MHz

enabled (MF × E × 2/PDF)

f

)

PLL external capacitor (PCAP pin to V

) (C

PCAP

CCP

•

@ MF ≤ 4

(MF × 580) −

100

MF × 830

(MF × 780) −

140

MF × 1470

(MF × 580) − 100 (MF × 780) − 140

pF

•

@ MF > 4

MF × 830

MF × 1470

Note:

C

is the value of the PLL capacitor (connected between the PCAP pin and V ). The recommended value in pF for C

PCAP CCP

PCAP

can be computed from one of the following equations:

(680 × MF) – 120, for MF ≤ 4, or

1100 × MF, for MF > 4.

DSP56301 Technical Data, Rev. 10

2-6

Freescale Semiconductor

AC Electrical Characteristics

2.5.4 Reset, Stop, Mode Select, and Interrupt Timing

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing⁶

80 MHz

100 MHz

No.

Characteristics

Expression

Unit

Min

Max

Min

Max

3

8

9

Delay from RESET assertion to all pins at reset value

—

26.0

—

26.0

ns

4

Required RESET duration

•

Power on, external clock generator, PLL disabled

Power on, external clock generator, PLL enabled

Power on, internal oscillator

During STOP, XTAL disabled (PCTL Bit 16 = 0)

During STOP, XTAL enabled (PCTL Bit 16 = 1)

During normal operation

50 × ET

1000 × ET

75000 × ET

625.0

12.5

1.0

31.3

—

500.0

10.0

0.75

25.0

—

ns

μs

ms

ns

C

2.5 × T

C

2.5 × T

ns

C

10 Delay from asynchronous RESET deassertion to first

5

external address output (internal reset deassertion)

•

Minimum

Maximum

3.25 × T + 2.0

42.6

—

263.1

34.5

—

212.5

ns

C

20.25 T + 10.0

C

11 Synchronous reset setup time from RESET deassertion to

CLKOUT Transition 1

T

C

•

Minimum

Maximum

7.4

—

12.5

5.9

—

10.0

ns

12 Synchronous reset deasserted, delay time from the

CLKOUT Transition 1 to the first external address output

•

Minimum

Maximum

3.25 × T + 1.0

41.6

—

258.1

33.5

—

207.5

ns

C

20.25 × T + 1.0

C

13 Mode select setup time

30.0

0.0

—

30.0

0.0

—

ns

14

Mode select hold time

15

16

Minimum edge-triggered interrupt request assertion width

8.25

—

6.6

—

ns

Minimum edge-triggered interrupt request deassertion

width

8.25

—

7.1

—

ns

17

Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

external memory access address out valid

•

Caused by first interrupt instruction fetch

Caused by first interrupt instruction execution

4.25 × T + 2.0

55.1

92.6

—

44.5

74.5

—

ns

C

7.25 × T + 2.0

C

18

19

Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

general-purpose transfer output valid caused by first

interrupt instruction execution

10 × T + 5.0

130.0

—

105.0

—

ns

C

Delay from address output valid caused by first interrupt 80 MHz:

—

Note 8

ns

instruction execute to interrupt request deassertion for

level sensitive fast interrupts

3.75 × T + WS × T – 12.4

100 MHz:

C

1

—

Note 8 ns

ns

3.75 × T + WS × T – 10.94

C

20

Delay from RD assertion to interrupt request deassertion 80 MHz:

—

Note 8

1

for level sensitive fast interrupts

3.25 × T + WS × T – 12.4

C

100 MHz:

3.25 × T + WS × T – 10.94

—

Note 8 ns

C

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-7

Specifications

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing⁶(Continued)

80 MHz

100 MHz

No.

Characteristics

Expression

Unit

Min

Max

Min

Max

21 Delay from WR assertion to interrupt request deassertion

1

for level sensitive fast interrupts

7

•

DRAM for all WS

SRAM WS = 1

SRAM WS = 2, 3

SRAM WS ≥ 4

80 MHz:

—

Note 8

ns

(WS + 3.5) × T – 12.4

C

100 MHz:

—

Note 8

(WS + 3.5) × T – 10.94

C

80 MHz:

—

Note 8

(WS + 3.5) × T – 12.4

C

100 MHz:

(WS + 3.5) × T – 10.94

C

80 MHz:

(WS + 3) × T – 12.4

C

100 MHz:

(WS + 3) × T – 10.94

C

80 MHz:

(WS + 2.5) × T – 12.4

C

100 MHz:

—

(WS + 2.5) × T – 10.94

C

22 Synchronous interrupt setup time from IRQA, IRQB,

IRQC, IRQD, NMI assertion to the CLKOUT Transition 2

7.4

T

5.9

T

ns

C

23 Synchronous interrupt delay time from the CLKOUT

Transition 2 to the first external address output valid

caused by the first instruction fetch after coming out of

Wait Processing state

8.25 × T + 1.0

116.6

—

314.4

83.5

—

252.5

ns

C

•

Minimum

Maximum

24.75 × T + 5.0

C

24 Duration for IRQA assertion to recover from Stop state

7.4

1.6

—

5.9

1.3

—

ns

25 Delay from IRQA assertion to fetch of first instruction

2, 3

(when exiting Stop)

•

PLL is not active during Stop (PCTL Bit 17 = 0) and

Stop delay is enabled (Operating Mode Register Bit 6

= 0)

PLC × ET × PDF + (128 K −

17.0

13.6

ms

C

PLC/2) × T

C

PLC × ET × PDF + (23.75

290.6 ns 15.4 ms 232.5

ns

12.3

ms

C

PLL is not active during Stop (PCTL Bit 17 = 0) and

Stop delay is not enabled (Operating Mode Register

Bit 6 = 1)

0.5) × T

C

(9.25 ± 0.5) × TC

109.4

121.9

87.5

97.5

ns

PLL is active during Stop (PCTL Bit 17 = 1) (Implies

No Stop Delay)

26 Duration of level sensitive IRQA assertion to ensure

2, 3

interrupt service (when exiting Stop)

•

PLL is not active during Stop (PCTL Bit 17 = 0) and

Stop delay is enabled (Operating Mode Register Bit 6

= 0)

PLC × ET × PDF + (128K −

17.0

15.4

68.8

—

13.6

12.3

55.0

—

ms

ns

C

PLC/2) × T

C

PLC × ET × PDF +

C

PLL is not active during Stop (PCTL Bit 17 = 0) and

Stop delay is not enabled (Operating Mode Register

Bit 6 = 1)

(20.5 0.5) × T

C

5.5 × T

C

PLL is active during Stop (PCTL Bit 17 = 1) (implies no

Stop delay)

27 Interrupt Request Rate

•

HI32, ESSI, SCI, Timer

DMA

IRQ, NMI (edge trigger)

IRQ, NMI (level trigger)

12 × T

—

150.0

100.0

150.0

—

120.0

80.0

ns

C

8 × T

C

8 × T

C

12 × T

120.0

C

DSP56301 Technical Data, Rev. 10

2-8

Freescale Semiconductor

AC Electrical Characteristics

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing⁶(Continued)

80 MHz

100 MHz

No.

Characteristics

Expression

Unit

Min

Max

Min

Max

28 DMA Request Rate

•

Data read from HI32, ESSI, SCI

Data write to HI32, ESSI, SCI

Timer

6 × T

—

75.0

87.5

25.0

37.5

—

60.0

70.0

20.0

30.0

ns

C

7 × T

C

2 × T

C

IRQ, NMI (edge trigger)

3 × T

C

29 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

external memory (DMA source) access address out valid

4.25 × T + 2.0

55.1

—

44.5

—

ns

C

Notes: 1. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to

prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended

when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.

2. This timing depends on several settings:

• For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL

Bit 17 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. Resetting the

Stop delay (Operating Mode Register Bit 6 = 0) provides the proper delay. While Operating Mode Register Bit 6 = 1 can be set,

it is not recommended, and these specifications do not guarantee timings for that case.

• For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no

stabilization delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored).

• For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time is defined by the

PCTL Bit 17 and Operating Mode Register Bit 6 settings.

• For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked.

The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in

parallel with the stop delay counter, and stop recovery ends when the last of these two events occurs. The stop delay counter

completes count or PLL lock procedure completion.

• PLC value for PLL disable is 0.

• The maximum value for ET is 4096 (maximum MF) divided by the desired internal frequency (that is, for 66 MHz it is

C

4096/66 MHz = 62 μs). During the stabilization period, T , T and T is not constant, and their width may vary, so timing may

C

H,

L

vary as well.

3. Periodically sampled and not 100 percent tested.

4. Value depends on clock source:

• For an external clock generator, RESET duration is measured while RESET is asserted, V is valid, and the EXTAL input is

CC

active and valid.

• For an internal oscillator, RESET duration is measured while RESET is asserted and V is valid. The specified timing

CC

reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal

and other components connected to the oscillator and reflects worst case conditions.

• When the V is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the

CC

device circuitry is in an uninitialized state that can result in significant power consumption and heat-up. Designs should

minimize this state to the shortest possible duration.

5. If PLL does not lose lock.

6.

V

= 3.3 V 0.3 V; T = –40°C to +100°C, C = 50 pF.

CC J L

7. WS = number of wait states (measured in clock cycles, number of T ).

C

8. Use the expression to compute a maximum value.

RESET

V

IH

9

10

8

All Pins

Reset Value

First Fetch

A[0–23]

Figure 2-3. Reset Timing

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-9

Specifications

CLKOUT

RESET

11

12

A[0–23]

Figure 2-4. Synchronous Reset Timing

First Interrupt Instruction

Execution/Fetch

A[0–23]

RD

20

21

WR

17

19

IRQA, IRQB,

IRQC, IRQD,

NMI

a) First Interrupt Instruction Execution

General

Purpose

I/O

18

IRQA, IRQB,

IRQC, IRQD,

NMI

b) General-Purpose I/O

Figure 2-5. External Fast Interrupt Timing

DSP56301 Technical Data, Rev. 10

2-10

Freescale Semiconductor

AC Electrical Characteristics

IRQA, IRQB,

IRQC, IRQD, NMI

15

16

IRQA, IRQB,

IRQC, IRQD, NMI

Figure 2-6. External Interrupt Timing (Negative Edge-Triggered)

CLKOUT

IRQA, IRQB,

IRQC, IRQD,

NMI

22

23

A[0–23]

Figure 2-7. Synchronous Interrupt from Wait State Timing

V

IH

RESET

13

14

V

IH

MODA, MODB,

MODC, MODD,

PINIT

IRQA, IRQB,

IRQC, IRQD, NMI

V

IL

Figure 2-8. Operating Mode Select Timing

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-11

Specifications

24

IRQA

25

First Instruction Fetch

A[0–23]

Figure 2-9. Recovery from Stop State Using IRQA

26

IRQA

25

First IRQA Interrupt

Instruction Fetch

A[0–23]

Figure 2-10. Recovery from Stop State Using IRQA Interrupt Service

DMA Source Address

A[0–23]

RD

WR

29

IRQA, IRQB,

IRQC, IRQD,

NMI

First Interrupt Instruction Execution

Figure 2-11. External Memory Access (DMA Source) Timing

2.5.5 External Memory Expansion Port (Port A)

DSP56301 Technical Data, Rev. 10

2-12

Freescale Semiconductor

AC Electrical Characteristics

2.5.5.1 SRAM Timing

Table 2-8. SRAM Read and Write Accesses^3,6

80 MHz

100 MHz

Unit

No.

Characteristics

Symbol

Expression¹

Min

Max

Min

Max

100 Address valid and AA

t

, t

(WS + 1) × T − 4.0 [1 ≤ WS ≤ 3]

21.0

71.0

133.5

—

16.0

56.0

106.0

—

ns

RC WC

C

2

assertion pulse width

(WS + 2) × T − 4.0 [4 ≤ WS ≤ 7]

C

(WS + 3) × T − 4.0 [WS ≥ 8]

C

101 Address and AA valid to

WR assertion

t

0.25 × T − 2.0 [WS = 1]

1.1

7.4

13.6

—

0.5

5.5

10.5

—

ns

AS

C

0.75 × T − 2.0 [2 ≤ WS ≤ 3]

C

1.25 × T − 2.0 [WS ≥ 4]

C

102 WR assertion pulse width

t

1.5 × T − 4.0 [WS = 1]

14.8

21.0

39.8

—

11.0

16.0

31.0

—

ns

WP

C

WS × T − 4.0 [2 ≤ WS ≤ 3]

C

(WS − 0.5) × T − 4.0 [WS ≥ 4]

C

103 WR deassertion to

address not valid

t

0.25 × T − 2.0 [1 ≤ WS ≤ 3]

1.1

11.6

24.1

—

0.5

8.5

18.5

—

ns

WR

C

1.25 × T − 4.0 [4 ≤ WS ≤ 7]

C

2.25 × T − 4.0 [WS ≥ 8]

C

104 Address and AA valid to

input data valid

t

, t

(WS + 0.75) × T − 5.0 [WS ≥ 1]

—

16.9

10.6

—

12.5

7.5

—

ns

AA AC

C

105 RD assertion to input data

valid

t

(WS + 0.25) × T − 5.0 [WS ≥ 1]

OE

C

106 RD deassertion to data not

valid (data hold time)

t

0.0

17.9

6.4

0.0

13.5

4.5

OHZ

107 Address valid to WR

t

(WS + 0.75) × T − 4.0 [WS ≥ 1]

—

AW

C

2

deassertion

108 Data valid to WR

deassertion (data setup

time)

t

(t

)

(WS − 0.25) × T − 3.0 [WS ≥ 1]

—

DS DW

C

109 Data hold time from WR

deassertion

t

0.25 × T − 2.0 [1 ≤ WS ≤ 3]

1.1

13.6

26.1

—

0.5

10.5

20.5

—

ns

DH

C

1.25 × T − 2.0 [4 ≤ WS ≤ 7]

C

2.25 × T − 2.0 [WS ≥ 8]

C

110 WR assertion to data

active

0.75 × T − 3.7 [WS = 1]

5.7

–0.6

–6.8

—

3.8

–1.2

–6.2

—

ns

C

0.25 × T − 3.7 [2 ≤ WS ≤ 3]

C

−0.25 × T − 3.7 [WS ≥ 4]

C

111 WR deassertion to data

high impedance

0.25 × T + 0.2 [1 ≤ WS ≤ 3]

—

3.3

15.8

28.3

—

2.7

12.7

22.7

ns

C

1.25 × T + 0.2 [4 ≤ WS ≤ 7]

C

2.25 × T + 0.2 [WS ≥ 8]

C

112 Previous RD deassertion

to data active (write)

1.25 × T − 4.0 [1 ≤ WS ≤ 3]

11.6

24.1

36.6

—

8.5

18.5

28.5

—

ns

C

2.25 × T − 4.0 [4 ≤ WS ≤ 7]

C

3.25 × T − 4.0 [WS ≥ 8]

C

113 RD deassertion time

114 WR deassertion time

0.75 × T − 4.0 [1 ≤ WS ≤ 3]

5.4

17.9

30.4

—

3.5

13.5

23.5

—

ns

C

1.75 × T − 4.0 [4 ≤ WS ≤ 7]

C

2.75 × T − 4.0 [WS ≥ 8]

C

0.5 × T − 4.0 [WS = 1]

2.3

8.5

27.3

39.8

—

1.0

6.0

21.0

31.0

—

ns

C

T

− 4.0 [2 ≤ WS ≤ 3]

C

2.5 × T − 4.0 [4 ≤ WS ≤ 7]

C

3.5 × T − 4.0 [WS ≥ 8]

C

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-13

Specifications

Table 2-8. SRAM Read and Write Accesses^3,6(Continued)

80 MHz

100 MHz

No.

Characteristics

Symbol

Expression¹

Unit

Min

Max

Min

Max

115 Address valid to RD

assertion

0.5 × T − 4.0

2.3

—

1.0

8.5

—

ns

C

116 RD assertion pulse width

(WS + 0.25) × T −4.0

11.6

—

C

117 RD deassertion to address

not valid

0.25 × T − 2.0 [1 ≤ WS ≤ 3]

1.1

13.6

26.1

—

0.5

10.5

20.5

—

ns

C

1.25 × T − 2.0 [4 ≤ WS ≤ 7]

C

2.25 × T − 2.0 [WS ≥ 8]

C

118 TA setup before RD or WR

0.25 × T + 2.0

5.1

0

—

4.5

0

—

ns

C

4

deassertion

119 TA hold after RD or WR

deassertion

Notes: 1. WS is the number of wait states specified in the BCR.

2. Timings 100, 107 are guaranteed by design, not tested.

3. All timings for 100 MHz are measured from 0.5 · Vcc to 0.5 · Vcc

4. Timing 118 is relative to the deassertion edge of RD or WR even if TA remains active.

5. Timings 110, 111, and 112, are not helpful and are not specified for 100 MHz.

6.

V

= 3.3 V 0.3 V; T = –40°C to +100°C, C = 50 pF

CC J L

100

A[0–23]

AA[0–3]

117

113

116

RD

105

106

119

WR

104

118

TA

Data

In

D[0–23]

Note: Address lines A[0–23] hold their state after a

read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-12. SRAM Read Access

DSP56301 Technical Data, Rev. 10

2-14

Freescale Semiconductor

AC Electrical Characteristics

100

A[0–23]

AA[0–3]

107

101

102

103

WR

RD

114

119

109

118

TA

108

Data

Out

D[0–23]

Note: Address lines A[0–23] hold their state after a

read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-13. SRAM Write Access

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-15

Specifications

2.5.5.2 DRAM Timing

The selection guides in Figure 2-14 and Figure 2-17 are for primary selection only. Final selection should be based

on the timing in the following tables. For example, the selection guide suggests that four wait states must be used

for 100 MHz operation in Page Mode DRAM. However, using the information in the appropriate table, a designer

could choose to evaluate whether fewer wait states might be used by determining which timing prevents operation

at 100 MHz, by running the chip at a slightly lower frequency (for example, 95 MHz), by using faster DRAM (if it

becomes available), and by manipulating control factors such as capacitive and resistive load to improve overall

system performance.

Note:

This figure should be used for primary selection. For exact

and detailed timings see the following tables.

DRAM type

(t_RACns)

100

80

70

60

50

Chip frequency

(MHz)

120

40

66

80

100

1 Wait state

2 Wait states

3 Wait states

4 Wait states

Figure 2-14. DRAM Page Mode Wait States Selection Guide

DSP56301 Technical Data, Rev. 10

2-16

Freescale Semiconductor

AC Electrical Characteristics

Table 2-9. DRAM Page Mode Timings, Two Wait States^{1, 2, 3, 7}

80 MHz

No.

Characteristics

Symbol

Expression

Unit

Min

Max

131 Page mode cycle time for two consecutive accesses of the same

direction

3 × T

37.5

—

ns

C

Page mode cycle time for mixed (read and write) accesses

132 CAS assertion to data valid (read)

t

2.75 × T

34.4

—

12.3

24.8

—

ns

PC

C

t

1.5 × T − 6.5

CAC

C

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

t

2.5 × T − 6.5

—

AA

C

t

0.0

OFF

1.75 × T − 4.0

17.9

36.6

14.8

—

RSH

C

t

3.25 × T − 4.0

—

RHCP

C

t

1.5 × T − 4.0

—

CAS

C

5

138 Last CAS deassertion to RAS deassertion

t

CRP

BRW[1–0] = 00

BRW[1–0] = 01

BRW[1–0] = 10

BRW[1–0] = 11

Not supported

—

ns

3.5 × T − 6.0

37.8

50.3

75.3

C

4.5 × T − 6.0

C

6.5 × T − 6.0

C

139 CAS deassertion pulse width

t

1.25 × T − 4.0

11.6

8.5

—

ns

CP

C

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

t

T − 4.0

C

ASC

CAH

t

1.75 × T − 4.0

17.9

33.5

11.6

2.6

—

C

t

3 × T − 4.0

—

RAL

C

t

1.25 × T − 4

—

RCS

C

0.5 × T − 3.7

—

RCH

C

t

1.5 × T − 4.2

14.6

26.8

30.1

27.0

0.1

—

WCH

C

t

2.5 × T − 4.5

—

WP

C

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t

2.75 × T − 4.3

—

RWL

CWL

C

2.5 × T − 4.3

—

C

t

0.25 × T − 3.0

—

DS

C

t

1.75 × T − 4.0

17.9

8.2

—

DH

C

t

T

− 4.3

—

WCS

C

t

2.5 × T − 4.0

27.3

—

ROH

C

t

1.75 × T − 6.5

15.4

—

GA

C

6

154 RD deassertion to data not valid

t

0.0

GZ

155 WR assertion to data active

0.75 × T − 1.5

7.9

—

C

156 WR deassertion to data high impedance

0.25 × T

—

3.1

C

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for the DSP56301.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, t equals 3 ×

PC

T

for read-after-read or write-after-write sequences).

C

5. BRW[1–0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page

access.

6. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

and not t

GZ.

OFF

7. At this time, there are no DRAMs fast enough to fit with two wait states Page mode @ 100MHz (see Table 2-14). However,

DRAM speeds are approaching two-wait-state compatibility.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-17

Specifications

Table 2-10. DRAM Page Mode Timings, Three Wait States^{1, 2, 3}

80 MHz

100 MHz

No.

Characteristics

Symbol

Expression

Unit

Min Max

131 Page mode cycle time for two consecutive accesses of the

same direction

4 × T

50.0

—

40.0

—

ns

C

Page mode cycle time for mixed (read and write) accesses

132 CAS assertion to data valid (read)

t

3.5 × T

43.7

—

19.3

31.8

—

35.0

—

14.3

24.3

—

ns

PC

C

t

2 × T − 5.7

CAC

C

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

t

3 × T − 5.7

—

AA

C

t

0.0

OFF

2.5 × T − 4.0

27.3

52.3

21.0

—

21.0

41.0

16.0

—

RSH

C

t

4.5 × T − 4.0

—

RHCP

C

t

2 × T − 4.0

—

CAS

C

5

138 Last CAS deassertion to RAS assertion

t

CRP

•

BRW[1–0] = 00

BRW[1–0] = 01

BRW[1–0] = 10

BRW[1–0] = 11

Not supported

—

ns

3.75 × T − 6.0

40.9

53.4

78.4

31.5

41.5

61.5

C

4.75 × T − 6.0

C

6.75 × T − 6.0

C

139 CAS deassertion pulse width

t

1.5 × T − 4.0

14.8

8.5

—

11.0

6.0

—

ns

CP

C

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

t

T − 4.0

C

ASC

2.5 × T − 4.0

27.3

46.0

11.6

5.4

—

21.0

36.0

8.5

—

CAH

C

t

4 × T − 4.0

—

RAL

RCS

C

t

1.25 × T − 4.0

—

C

0.75 × TC − 4.0

—

3.5

—

RCH

WCH

t

2.25 × T − 4.2

23.9

39.3

42.6

36.3

2.0

—

18.3

30.5

33.2

28.2

0.2

—

C

t

3.5 × T − 4.5

—

WP

C

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

t

3.75 × T − 4.3

—

RWL

CWL

C

t

3.25 × T − 4.3

—

C

t

0.5 × T – 4.8

—

DS

C

t

2.5 × T − 4.0

27.3

11.3

39.8

—

21.0

8.2

—

DH

C

t

1.25 × T − 4.3

—

WCS

C

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t

3.5 × T − 4.0

—

31.0

—

ROH

C

t

2.5 × T − 5.7

25.6

—

19.3

—

GA

C

6

154 RD deassertion to data not valid

t

0.0

GZ

155 WR assertion to data active

0.75 × T – 1.5

7.9

—

6.0

—

C

156 WR deassertion to data high impedance

0.25 × T

—

3.1

—

2.5

C

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56301.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, t equals 4 ×

PC

T

for read-after-read or write-after-write sequences).

C

5. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-

access.

6. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

and not t

.

GZ

OFF

DSP56301 Technical Data, Rev. 10

2-18

Freescale Semiconductor

AC Electrical Characteristics

Table 2-11. DRAM Page Mode Timings, Four Wait States^{1, 2, 3}

80 MHz

100 MHz

No.

Characteristics

Symbol

Expression

Unit

Min Max

131 Page mode cycle time for two consecutive accesses of the

same direction

5 × T

62.5

—

50.0

—

ns

C

Page mode cycle time for mixed (read and write) accesses

132 CAS assertion to data valid (read)

t

4.5 × T

56.2

—

28.7

41.2

—

45.0

—

21.8

31.8

—

ns

PC

C

t

2.75 × T − 5.7

CAC

C

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

t

3.75 × T − 5.7

—

AA

C

t

0.0

OFF

3.5 × T − 4.0

39.8

71.0

27.3

—

31.0

56.0

21.0

—

RSH

C

t

6 × T − 4.0

—

RHCP

C

t

2.5 × T − 4.0

—

CAS

C

5

138 Last CAS deassertion to RAS assertion

t

CRP

•

BRW[1–0] = 00

BRW[1–0] = 01

BRW[1–0] = 10

BRW[1–0] = 11

Not supported

—

ns

4.25 × T − 6.0

47.2

59.6

84.6

36.5

46.5

66.5

C

5.25 × T − 6.0

C

7.25 × T − 6.0

C

139 CAS deassertion pulse width

t

2 × T − 4.0

21.0

8.5

—

16.0

6.0

—

ns

CP

C

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

t

T − 4.0

C

ASC

CAH

3.5 × T − 4.0

39.8

58.5

11.8

11.9

36.4

51.8

55.1

42.6

1.5

—

31.0

46.0

8.5

—

C

t

5 × T − 4.0

—

RAL

RCS

RCH

C

t

1.25 × T − 4.0

—

C

1.25 × T – 3.7

—

8.8

—

C

t

3.25 × T − 4.2

—

28.3

40.5

43.2

33.2

0.2

—

WCH

C

t

4.5 × T − 4.5

—

WP

C

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

t

4.75 × T − 4.3

—

RWL

CWL

C

t

3.75 × T − 4.3

—

C

t

0.5 × T – 4.8

—

DS

C

t

3.5 × T − 4.0

39.8

11.3

52.3

—

31.0

8.2

—

DH

C

t

1.25 × T − 4.3

—

WCS

C

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t

4.5 × T − 4.0

—

41.0

—

ROH

C

t

3.25 × T − 5.7

34.9

—

26.8

—

GA

C

6

154 RD deassertion to data not valid

t

0.0

GZ

155 WR assertion to data active

0.75 × T – 1.5

7.9

—

6.0

—

C

156 WR deassertion to data high impedance

0.25 × T

—

3.1

—

2.5

C

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56301.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, t equals

PC

3 × T for read-after-read or write-after-write sequences).

C

5. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page

access. N/A = does not apply because 100 MHz requires a minimum of three wait states.

6. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

and not t

.

GZ

OFF

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-19

Specifications

RAS

CAS

136

131

135

137

139

138

142

140

151

141

Column

Address

Last Column

Address

Column

Address

Row

Add

A[0–23]

144

145

147

148

WR

RD

146

155

156

150

149

D[0–23]

Data Out

Figure 2-15. DRAM Page Mode Write Accesses

RAS

CAS

136

131

135

137

140

139

138

142

141

Row

Add

Last Column

Address

Column

Address

Column

Address

A[0–23]

WR

143

132

133

153

152

RD

134

154

D[0–23]

Data In

Figure 2-16. DRAM Page Mode Read Accesses

DSP56301 Technical Data, Rev. 10

2-20

Freescale Semiconductor

AC Electrical Characteristics

DRAM Type

(t_RACns)

Note: This figure should be used for primary selection. For

exact and detailed timings, see the following tables.

100

80

70

60

Chip Frequency

(MHz)

50

120

40 66

80

100

4 Wait States

8 Wait States

11 Wait States

15 Wait States

Figure 2-17. DRAM Out-of-Page Wait States Selection Guide

Table 2-12. DRAM Out-of-Page and Refresh Timings, Eight Wait States^{1, 2}

80 MHz

Characteristics³

No.

Symbol

Expression

Unit

Min

Max

157 Random read or write cycle time

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

160 Column address valid to data valid (read)

161 CAS deassertion to data not valid (read hold time)

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t

9 × T

112.5

—

52.9

21.6

31.0

—

ns

RC

C

t

4.75 × T − 6.5

RAC

C

t

2.25 × T − 6.5

—

CAC

C

t

3 × T − 6.5

—

AA

C

t

0.0

OFF

t

3.25 × T − 4.0

36.6

67.9

36.6

55.4

24.1

29.3

19.9

49.1

28.4

36.6

—

RP

C

t

5.75 × T − 4.0

—

RAS

C

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

3.25 × T − 4.0

—

RSH

CSH

C

t

4.75 × T − 4.0

—

C

t

2.25 × T − 4.0

—

CAS

C

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

2.5 × T

2

33.3

23.9

—

RCD

C

t

1.75 × T

2

RAD

CRP

C

t

4.25 × T − 4.0

C

t

2.75 × T − 6.0

—

CP

C

171 Row address valid to RAS assertion

t

3.25 × T − 4.0

—

ASR

C

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-21

Specifications

Table 2-12. DRAM Out-of-Page and Refresh Timings, Eight Wait States^{1, 2}(Continued)

80 MHz

Characteristics³

No.

Symbol

Expression

Unit

Min

Max

172 RAS assertion to row address not valid

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

t

1.75 × T − 4.0

17.9

5.4

—

87.3

—

3.1

ns

RAH

C

t

0.75 × T − 4.0

ASC

C

t

3.25 × T − 4.0

36.6

67.9

46.0

21.2

11.9

0.5

CAH

C

t

5.75 × T − 4.0

AR

C

t

4 × T − 4.0

RAL

C

t

2 × T − 3.8

RCS

C

4

178 CAS deassertion to WR assertion

t

1.25 × T − 3.7

RCH

C

4

179 RAS deassertion to WR assertion

t

0.25 × T − 2.6

RRH

C

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t

3 × T − 4.2

33.3

64.6

101.8

105.1

92.6

55.4

36.6

67.9

64.5

14.8

17.9

102.3

—

WCH

C

t

5.5 × T − 4.2

WCR

C

t

8.5 × T − 4.5

WP

C

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

192 RD assertion to data valid

t

8.75 × T − 4.3

RWL

C

t

7.75 × T − 4.3

CWL

C

t

4.75 × T − 4.0

DS

C

t

3.25 × T − 4.0

DH

C

t

5.75 × T − 4.0

DHR

C

t

5.5 × T − 4.3

WCS

C

t

1.5 × T − 4.0

CSR

C

t

1.75 × T − 4.0

RPC

C

t

8.5 × T − 4.0

ROH

C

t

7.5 × T − 6.5

GA

C

3

193 RD deassertion to data not valid

t

0.0

GZ

194 WR assertion to data active

0.75 × T − 1.5

7.9

C

195 WR deassertion to data high impedance

0.25 × T

—

C

Notes: 1. The number of wait states for an out-of-page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

and not t

.

GZ

OFF

4. Either t

or t

must be satisfied for read cycles.

RCH

RRH

DSP56301 Technical Data, Rev. 10

2-22

Freescale Semiconductor

AC Electrical Characteristics

Table 2-13. DRAM Out-of-Page and Refresh Timings, Eleven Wait States^{1, 2}

80 MHz

100 MHz

No.

Characteristics³

Symbol

Expression

Unit

Min Max

157 Random read or write cycle time

158 RAS assertion to data valid (read)

t

12 × T

150.0

—

120.0

—

ns

RC

C

t

80 MHz:

RAC

6.25 × T − 6.5

100 MHz:

—

71.6

—

ns

C

6.25 × T − 7.0

55.5

C

159 CAS assertion to data valid (read)

t

80 MHz:

CAC

3.75 × T − 6.5

100 MHz:

—

40.4

—

ns

C

3.75 × T − 7.0

30.5

C

160 Column address valid to data valid (read)

t

80 MHz:

AA

4.5 × T − 6.5

—

49.8

—

ns

C

100 MHz:

4.5 × T − 7.0

—

38.0

—

ns

C

161 CAS deassertion to data not valid (read hold time)

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t

0.0

OFF

t

4.25 × T − 4.0

49.1

92.9

61.6

74.1

42.9

27.3

17.9

67.9

49.1

17.9

5.4

—

38.5

73.5

48.5

58.5

33.5

21.0

13.5

53.5

36.5

38.5

13.5

3.5

—

RP

C

t

7.75 × T − 4.0

—

RAS

C

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

5.25 × T − 4.0

—

RSH

CSH

C

t

6.25 × T − 4.0

—

C

t

3.75 × T − 4.0

—

CAS

C

167 RAS assertion to CAS assertion

2.5 × T

4.0

35.3

25.9

—

29.0

21.5

—

RCD

C

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

t

1.75 × T

C

RAD

CRP

t

5.75 × T − 4.0

C

t

4.25 × T – 6.0

—

CP

C

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

t

4.25 × T − 4.0

—

ASR

C

1.75 × T − 4.0

—

RAH

C

t

0.75 × T − 4.0

—

ASC

CAH

C

t

5.25 × T − 4.0

61.6

92.9

71.0

33.5

17.9

—

48.5

73.5

56.0

26.0

13.8

—

C

t

7.75 × T − 4.0

—

AR

C

t

6 × T − 4.0

—

RAL

C

3.0 × T − 4.0

—

RCS

RCH

RRH

C

4

178 CAS deassertion to WR assertion

t

1.75 × T – 3.7

—

C

4

179 RAS deassertion to WR assertion

80 MHz:

0.25 × T − 2.6

0.5

—

ns

C

100 MHz:

0.25 × T − 2.0

—

0.5

45.8

70.8

110.5

113.2

98.2

53.5

48.5

—

ns

C

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t

5 × T − 4.2

58.3

89.6

139.3

142.7

123.8

67.9

61.6

WCH

WCR

C

7.5 × T − 4.2

C

t

11.5 × T − 4.5

WP

C

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

t

11.75 × T − 4.3

RWL

CWL

C

t

10.25 × T − 4.3

C

t

5.75 × T − 4.0

DS

C

t

5.25 × T − 4.0

DH

C

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-23

Specifications

Table 2-13. DRAM Out-of-Page and Refresh Timings, Eleven Wait States^{1, 2}(Continued)

80 MHz

100 MHz

No.

Characteristics³

Symbol

Expression

Unit

Min Max

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

t

7.75 × T − 4.0

92.9

77.0

14.8

30.4

139.8

—

73.5

60.7

11.0

23.5

111.0

—

ns

DHR

C

t

6.5 × T − 4.3

WCS

C

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

192 RD assertion to data valid

t

1.5 × T − 4.0

CSR

C

t

2.75 × T − 4.0

RPC

C

t

11.5 × T − 4.0

ROH

C

t

80 MHz:

GA

10 × T − 6.5

—

118.5

—

ns

C

100 MHz:

10 × T − 7.0

—

0.0

9.1

—

0.0

6.0

—

93.0

—

ns

C

3

193 RD deassertion to data not valid

t

GZ

194 WR assertion to data active

0.75 × T – 1.5

—

C

195 WR deassertion to data high impedance

0.25 × T

3.1

2.5

C

Notes: 1. The number of wait states for an out-of-page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

and not t

.

GZ

OFF

4. Either t

or t

must be satisfied for read cycles.

RCH

RRH

Table 2-14. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States^{1, 2}

80 MHz

100 MHz

Min Max

No.

Characteristics³

Symbol

Expression

Unit

Min Max

157 Random read or write cycle time

158 RAS assertion to data valid (read)

t

16 × T

200.0

—

160.0

—

ns

RC

C

t

80 MHz:

RAC

8.25 × T − 6.5

100 MHz:

—

96.6

—

ns

C

8.25 × T − 5.7

76.8

C

159 CAS assertion to data valid (read)

t

80 MHz:

CAC

4.75 × T − 6.5

100 MHz:

—

52.9

—

ns

C

4.75 × T − 5.7

41.8

C

160 Column address valid to data valid (read)

t

80 MHz:

AA

5.5 × T − 6.5

—

62.3

—

ns

C

100 MHz:

5.5 × T − 5.7

—

49.3

—

ns

C

161 CAS deassertion to data not valid (read hold time)

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t

0.0

OFF

t

6.25 × T − 4.0

74.1

117.9

74.1

99.1

55.4

41.8

32.4

92.9

—

58.5

93.5

58.5

78.5

43.5

33.0

25.5

73.5

—

RP

C

t

9.75 × T − 4.0

—

RAS

C

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

6.25 × T − 4.0

—

RSH

CSH

C

t

8.25 × T − 4.0

—

C

t

4.75 × T − 4.0

—

CAS

C

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

t

3.5 × T

2

45.8

36.4

—

37.0

29.5

—

RCD

C

t

2.75 × T

2.0

RAD

CRP

C

t

7.75 × T − 4.0

C

DSP56301 Technical Data, Rev. 10

2-24

Freescale Semiconductor

AC Electrical Characteristics

Table 2-14. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States^{1, 2}(Continued)

80 MHz

100 MHz

No.

Characteristics³

Symbol

Expression

Unit

Min Max

170 CAS deassertion pulse width

t

6.25 × T – 6.0

74.1

30.4

5.4

—

56.5

58.5

23.5

3.5

—

ns

CP

C

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

t

6.25 × T − 4.0

ASR

C

t

2.75 × T − 4.0

RAH

C

t

0.75 × T − 4.0

ASC

C

t

6.25 × T − 4.0

74.1

117.9

83.5

58.7

18.2

58.5

93.5

66.0

46.2

13.8

CAH

C

t

9.75 × T − 4.0

AR

C

t

7 × T − 4.0

RAL

C

t

5 × T − 3.8

RCS

C

4

178 CAS deassertion to WR assertion

t

1.75 × T – 3.7

RCH

C

4

179 RAS deassertion to WR assertion

t

80 MHz:

RRH

0.25 × T − 2.6

0.5

—

ns

C

100 MHz:

0.25 × T − 2.0

—

0.5

55.8

90.8

150.5

153.2

138.2

83.5

58.5

93.5

90.7

11.0

43.5

151.0

—

ns

C

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t

6 × T − 4.2

70.8

WCH

WCR

C

9.5 × T − 4.2

114.6

189.3

192.6

173.8

105.4

74.1

C

t

15.5 × T − 4.5

WP

C

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

192 RD assertion to data valid

t

15.75 × T − 4.3

RWL

CWL

C

t

14.25 × T − 4.3

C

t

8.75 × T − 4.0

DS

C

t

6.25 × T − 4.0

DH

C

t

9.75 × T − 4.0

117.9

114.5

14.8

DHR

C

9.5 × T − 4.3

WCS

C

t

1.5 × T − 4.0

CSR

C

t

4.75 × T − 4.0

55.4

RPC

C

15.5 × T − 4.0

189.8

ROH

C

t

80 MHz:

GA

14 × T − 6.5

—

168.5

—

ns

C

100 MHz:

14 × T − 5.7

—

0.0

9.1

—

0.0

6.0

—

134.3

—

ns

C

3

193 RD deassertion to data not valid

t

GZ

194 WR assertion to data active

0.75 × T – 1.5

—

C

195 WR deassertion to data high impedance

0.25 × T

3.1

2.5

C

Notes: 1. The number of wait states for an out-of-page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

and not t

.

GZ

OFF

4. Either t

or t

must be satisfied for read cycles.

RCH

RRH

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-25

Specifications

157

163

162

165

RAS

167

168

164

169

170

166

CAS

171

173

174

175

Row Address

172

Column Address

176

A[0–23]

177

179

191

WR

RD

178

160

159

158

193

192

161

Data

In

D[0–23]

Figure 2-18. DRAM Out-of-Page Read Access

DSP56301 Technical Data, Rev. 10

2-26

Freescale Semiconductor

AC Electrical Characteristics

157

162

163

162

165

RAS

167

164

169

168

166

170

CAS

173

172

171

174

176

Row Address

Column Address

A[0–23]

181

175

188

180

182

WR

184

183

187

RD

186

195

185

194

Data Out

D[0–23]

Figure 2-19. DRAM Out-of-Page Write Access

157

162

163

RAS

190

170

177

165

189

CAS

WR

Figure 2-20. DRAM Refresh Access

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-27

Specifications

2.5.5.3 Synchronous Timings (SRAM)

Table 2-15. External Bus Synchronous Timings (SRAM Access)³

80 MHz

100 MHz

No.

Characteristics

Expression^1,2

Unit

Min

Max

Min

Max

196

197

198

199

200

201

202

203

CLKOUT high to BS assertion

0.25 × T +5.2/–0.5

2.6

8.4

—

8.3

13.6

5.6

—

2.0

6.5

—

7.7

11.7

5.0

—

ns

C

CLKOUT high to BS deassertion

CLKOUT high to address, and AA valid

0.75 × T +4.2/–1.0

C

4

0.25 × T + 2.5

C

4

CLKOUT high to address, and AA invalid

TA valid to CLKOUT high (setup time)

CLKOUT high to TA invalid (hold time)

CLKOUT high to data out active

0.25 × T – 0.7

2.4

5.8

0.0

3.1

1.8

4.0

0.0

2.5

C

—

0.25 × T

—

C

CLKOUT high to data out valid

80 MHz:

0.25 × T + 4.5

—

7.6

—

ns

C

100 MHz:

0.25 × T + 4.0

—

6.5

—

ns

C

204

205

CLKOUT high to data out invalid

0.25 × T

3.1

2.5

C

CLKOUT high to data out high impedance

80 MHz:

0.25 × T + 0.5

—

3.6

—

ns

C

100 MHz:

0.25 × T

—

5.0

—

2.5

—

ns

C

206

207

208

Data in valid to CLKOUT high (setup)

CLKOUT high to data in invalid (hold)

CLKOUT high to RD assertion

4.0

0.0

6.7

0.0

—

maximum:

10.4

ns

0.75 × T + 2.5

11.9

4.5

10.0

4.0

C

209

210

CLKOUT high to RD deassertion

0.0

7.6

0.0

4.5

ns

2

CLKOUT high to WR assertion

0.5 × T + 4.3

10.6

9.3

C

[WS = 1 or WS ≥ 4]

[2 ≤ WS ≤ 3]

1.3

0.0

4.8

4.3

0.0

4.3

3.8

ns

211

CLKOUT high to WR deassertion

Notes: 1. WS is the number of wait states specified in the BCR.

2. If WS > 1, WR assertion refers to the next rising edge of CLKOUT.

3. External bus synchronous timings should be used only for reference to the clock and not for relative timings.

4. T198 and T199 are valid for Address Trace mode if the ATE bit in the Operating Mode Register is set. Use the status of BR

(See T212) to determine whether the access referenced by A[0–23] is internal or external in this mode.

DSP56301 Technical Data, Rev. 10

2-28

Freescale Semiconductor

AC Electrical Characteristics

198

CLKOUT

A[0–23]

AA[0–3]

199

201

200

TA

211

WR

205

210

203

204

D[0–23]

RD

Data Out

208

202

209

207

206

D[0–23]

Data In

Note: Address lines A[0–23] hold their state after a read or write operation. AA[0–3] do not hold their state

after a read or write operation.

Figure 2-21. Synchronous Bus Timings 1 WS (BCR Controlled)

CLKOUT

A[0–23]

AA[0–3]

199

201

198

201

200

211

TA

200

WR

210

205

203

202

204

Data Out

D[0–23]

208

209

RD

207

206

Data In

D[0–23]

Note: Address lines A[0–23] hold their state after a read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-22. Synchronous Bus Timings 2 WS (TA Controlled)

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-29

Specifications

2.5.5.4 Arbitration Timings

Table 2-16. Arbitration Bus Timings¹.

80 MHz

100 MHz

No.

Characteristics

Expression²

Unit

Min

Max

Min

Max

3

212

213

CLKOUT high to BR assertion/deassertion

1.0

5.0

4.5

—

0.0

4.0

—

ns

BG asserted/deasserted to CLKOUT high

(setup)

214

CLKOUT high to BG deasserted/asserted

(hold)

0.0

—

0.0

—

ns

215

216

217

218

219

220

221

BB deassertion to CLKOUT high (input setup)

CLKOUT high to BB assertion (input hold)

CLKOUT high to BB assertion (output)

CLKOUT high to BB deassertion (output)

BB high to BB high impedance (output)

CLKOUT high to address and controls active

5.0

0.0

1.0

—

4.0

0.0

—

ns

4.5

5.6

—

4.0

4.5

—

0.25 × T

3.1

—

2.5

—

C

CLKOUT high to address and controls high

impedance

0.75 × T

9.4

7.5

C

222

223

224

CLKOUT high to AA active

0.25 × T

3.1

4.1

—

2.5

2.0

—

ns

C

CLKOUT high to AA deassertion

CLKOUT high to AA high impedance

maximum: 0.25 × T + 4.0

7.1

9.4

6.5

7.5

C

0.75 × T

C

Notes: 1. Synchronous Bus Arbitration is not recommended. Use Asynchronous mode whenever possible.

2. An expression is used to compute the maximum or minimum value listed, as appropriate. For timing 223, the minimum is an

absolute value.

3. T212 is valid for Address Trace mode when the ATE bit in the Operating Mode Register is set. BR is deasserted for internal

accesses and asserted for external accesses.

DSP56301 Technical Data, Rev. 10

2-30

Freescale Semiconductor

AC Electrical Characteristics

CLKOUT

BR

214

216

212

213

215

BG

BB

217

220

A[0–23]

RD, WR

222

AA[0–3]

Note: Address lines A[0–23] hold their state after a read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-23. Bus Acquisition Timings

CLKOUT

BR

214

213

212

BG

219

218

BB

221

A[0–23]

RD, WR

224

223

AA[0–3]

Note: Address lines A[0–23] hold their state after a read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-24. Bus Release Timings Case 1 (BRT Bit in Operating Mode Register Cleared)

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-31

Specifications

CLKOUT

BR

212

214

213

BG

BB

219

218

221

A[0–23]

RD, WR

224

223

AA[0–3]

Note: Address lines A[0–23] hold their state after a read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-25. Bus Release Timings Case 2 (BRT Bit in Operating Mode Register Set)

2.5.5.5 Asynchronous Bus Arbitrations Timings

Table 2-17. Asynchronous Bus Arbitration Timing^1,3

80 MHz

100 MHz²

Min Max

No.

Characteristics

Expression

Unit

Min

Max

4

250

251

BB assertion window from BG input deassertion

2.5 × Tc + 5

2 × Tc + 5

—

25

—

30

ns

4

Delay from BB assertion to BG assertion

25

—

Notes: 1. Bit 13 in the Operating Mode Register must be set to enter Asynchronous Arbitration mode.

2. Asynchronous Arbitration mode is recommended for operation at 100 MHz.

3. If Asynchronous Arbitration mode is active, none of the timings in Table 2-16 is required.

4. In order to guarantee timings 250, and 251, BG inputs must be asserted to different DSP56300 devices on the same bus in

the non-overlap manner shown in Figure 2-26.

DSP56301 Technical Data, Rev. 10

2-32

Freescale Semiconductor

AC Electrical Characteristics

BG1

BB

250

BG2

251

250+251

Figure 2-26. Asynchronous Bus Arbitration Timing

The asynchronous bus arbitration is enabled by internal BB inputs and synchronization circuits on BG. These

synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this

delay, a DSP56300 part can assume mastership and assert BB, for some time after BG is deasserted. Timing 250

defines when BB can be asserted.

Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other

DSP56300 components which are potential masters on the same bus. If BG input is asserted before that time, a

situation of BG asserted, and BB deasserted, can cause another DSP56300 component to assume mastership at the

same time. Therefore, a non-overlap period between one BG input active to another BG input active is required.

Timing 251 ensures that such a situation is avoided.

2.5.6 Host Interface Timing

Table 2-18. Universal Bus Mode Timing Parameters

80 MHz

100 MHz

No.

Characteristic

Expression

Unit

Min Max

300 Access Cycle Time

3 × T

37.5

5.8

—

30.0

4.6

0.0

4.6

0.0

3.3

—

ns

C

1

301 HA[10–0], HAEN Setup to Data Strobe Assertion

1

302 HA[10–0], HAEN Valid Hold from Data Strobe Deassertion

0.0

2

303 HRW Setup to HDS Assertion

5.8

2

304 HRW Valid Hold from HDS Deassertion

0.0

1

305 Data Strobe Deasserted Width

4.1

1

306 Data Strobe Asserted Pulse Width

80 MHz: 2.5 × T + 1.7

100 MHz: 2.5 × T + 1.3

32.9

ns

C

26.3

2.0

—

C

307 HBS Asserted Pulse Width

2.5

—

ns

1

308 HBS Assertion to Data Strobe Assertion

80 MHz: T − 4.9

7.6

ns

C

100 MHz: T − 4.0

—

6.0

—

C

1

309 HBS Assertion to Data Strobe Deassertion

80 MHz: 2.5 × T + 2.9

100 MHz: 2.5 × T + 2.3

34.1

22.1

13.4

1.7

—

ns

C

27.3

17.6

C

1

310 HBS Deassertion to Data Strobe Deassertion

80 MHz: 1.5 × T + 3.3

100 MHz: 1.5 × T + 2.6

ns

C

—

C

2

311 Data Out Valid to TA Assertion (HBS Not Used—Tied to V

)

80 MHz: 2 × T − 11.6

100 MHz: 2 × T − 9.2

ns

CC

C

10.8

1.3

—

C

3

312 Data Out Active from Read Data Strobe Assertion

ns

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-33

Specifications

Table 2-18. Universal Bus Mode Timing Parameters (Continued)

80 MHz

100 MHz

No.

Characteristic

Expression

Unit

Min Max

313 Data Out Valid from Read Data Strobe Assertion

—

18.9

—

16.9

ns

3

(No Wait States Inserted—HTA Asserted)

314 Data Out Valid Hold from Read Data Strobe Deassertion

1.7

—

12.0

—

1.3

—

9.6

—

ns

3

315 Data Out High Impedance from Read Data Strobe Deassertion

4

316 Data In Valid Setup to Write Data Strobe Deassertion

8.3

0.0

—

6.6

0.0

—

4

317 Data In Valid Hold from Write Data Strobe Deassertion

—

1

318 HSAK Assertion from Data Strobe Assertion

30.0

—

30.0

—

1

319 HSAK Asserted Hold from Data Strobe Deassertion

2.0

3.1

38.0

2.0

2.5

1,2,5

320 HTA Active from Data Strobe Assertion

—

321 HTA Assertion from Data Strobe Assertion

80 MHz: 2.0 × T + 13.0

—

ns

C

1,2,5

(HBS Not Used—Tied to V

)

100 MHz: 2.0 × T + 12.2

32.2

—

CC

C

2,5

322 HTA Assertion from HBS Assertion

80 MHz: 2.0 × T + 13.0

38.0

—

ns

C

100 MHz: 2.0 × T + 12.2

32.2

—

15.0

—

C

1,2,5

323 HTA Deasserted from Data Strobe Assertion

—

0.0

—

17.1

—

ns

1,2

324 HTA Assertion to Data Strobe Deassertion

0.0

—

1,2

325 HTA High Impedance from Data Strobe Deassertion

326 HIRQ Asserted Pulse Width (HIRH = 0, HIRD = 1)

15.3

—

12.2

—

7

(LT + 1) × T − 6.0

19.0

0.0

14.0

0.0

C

327 Data Strobe Deasserted Hold from HIRQ Deassertion

—

1

(HIRH = 0)

1

328 HIRQ Asserted Hold from Data Strobe Assertion (HIRH = 1)

1.5 × T

18.8

—

15.0

—

ns

C

329 HIRQ Deassertion from Data Strobe Assertion

80 MHz: 2.5 × T + 24.7

100 MHz: 2.5 × T + 21.5

55.9

ns

C

1

(HIRH = 1, HIRD = 1)

46.5

C

330 HIRQ High Impedance from Data Strobe Assertion

80 MHz: 2.5 × T + 24.7

—

55.9

—

ns

C

1,6

(HIRH = 1, HIRD = 0)

100 MHz: 2.5 × T + 21.5

—

46.5

—

C

331 HIRQ Active from Data Strobe Deassertion

2.5 × T

31.3

25.0

ns

C

1

(HIRH = 1, HIRD = 0)

1

332 HIRQ Deasserted Hold from Data Strobe Deassertion

2.5 × T

31.3

18.8

—

25.0

15.0

—

ns

C

2

1

333 HDRQ Asserted Hold from Data Strobe Assertion

1.5 × T

C

2

1

334 HDRQ Deassertion from Data Strobe Assertion

80 MHz: 2.5 × T + 24.7

100 MHz: 2.5 × T + 21.5

55.9

ns

C

—

46.5

C

2

1

335 HDRQ Deasserted Hold from Data Strobe Deassertion

80 MHz: 2.5 × T + 3.7

35.0

—

ns

C

100 MHz: 2.5 × T + 3.0

28.0

4.6

0.0

2.0

—

C

1

336 HDAK Assertion to Data Strobe Assertion

5.8

0.0

2.5

—

ns

1

337 HDAK Asserted Hold from Data Strobe Deassertion

—

1

338 HDBEN Deasserted Hold from Data Strobe Assertion

—

1

339 HDBEN Assertion from Data Strobe Assertion

22.2

—

19.6

—

1

340 HDBEN Asserted Hold from Data Strobe Deassertion

2.5

—

2.0

—

1

341 HDBEN Deassertion from Data Strobe Deassertion

22.2

—

19.6

—

3

342 HDBDR High Hold from Read Data Strobe Assertion

2.5

—

2.0

—

3

343 HDBDR Low from Read Data Strobe Assertion

22.2

—

19.6

—

3

344 HDBDR Low Hold from Read Data Strobe Deassertion

2.5

2.0

DSP56301 Technical Data, Rev. 10

2-34

Freescale Semiconductor

AC Electrical Characteristics

Table 2-18. Universal Bus Mode Timing Parameters (Continued)

80 MHz

100 MHz

No.

Characteristic

Expression

Unit

Min Max

3

345 HDBDR High from Read Data Strobe Deassertion

—

22.2

—

19.6

ns

2

346 HRST Assertion to Host Port Pins High Impedance

Notes: 1. The Data Strobe is HRD or HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

2. HTA, HDRQ, and HRST may be programmed as active-high or active-low. In the example timing diagrams, HDRQ and HRST

are shown as active-high and HTA is shown as active low.

3. The Read Data Strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

4. The Write Data Strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

5. HTA requires an external pull-down resistor if programmed as active high (HTAP = 0); or an external pull-up resistor if

programmed as active low (HTAP = 1). The resistor value should be consistent with the DC specifications.

6. HIRQ requires an external pull-up resistor if programmed as open drain (HIRD = 0). The resistor value should be consistent

with the DC specifications.

7. “LT” is the value of the latency timer register (CLAT) as programmed by the user during self configuration.

LT ≥ 1.

8. Values are valid for V = 3.3 0.3V

CC

Table 2-19. Universal Bus Mode, Synchronous Port A Type Host Timing

80 MHz

100 MHz

No.

Characteristic

Expression

Unit

Min Max

300 Access Cycle Time

3 × T

37.5

5.8

0.0

4.1

2.5

—

7.6

30.0

4.6

0.0

3.3

2.0

—

ns

C

1

301 HA[10–0], HAEN Setup to Data Strobe Assertion

1

302 HA[10–0], HAEN Valid Hold from Data Strobe Deassertion

1

305 Data Strobe Deasserted Width

307 HBS Asserted Pulse Width

1

308 HBS Assertion to Data Strobe Assertion

80 MHz: T − 4.9

ns

C

100 MHz: T − 4.0

—

6.0

—

C

1

309 HBS Assertion to Data Strobe Deassertion

80 MHz: 2.5 × T + 2.9

100 MHz: 2.5 × T + 2.3

34.1

22.1

—

ns

C

27.3

C

1

310 HBS Deassertion to Data Strobe Deassertion

80 MHz: 1.5 × T + 3.3

100 MHz: 1.5 × T + 2.6

ns

C

17.6

1.3

—

C

3

312 Data Out Active from Read Data Strobe Assertion

1.7

—

ns

313 Data Out Valid from Read Data Strobe Assertion

18.9

16.9

3

(No Wait States Inserted—HTA Asserted)

314 Data Out Valid Hold from Read Data Strobe Deassertion

1.7

—

12.0

—

1.3

—

9.6

—

ns

3

315 Data Out High Impedance from Read Data Strobe Deassertion

4

316 Data In Valid Setup to Write Data Strobe Deassertion

8.3

0.0

—

6.6

0.0

—

4

317 Data In Valid Hold from Write Data Strobe Deassertion

—

1,2

324 HTA Assertion to Data Strobe Deassertion

—

1,2

325 HTA High Impedance from Data Strobe Deassertion

15.3

—

12.2

—

7

326 HIRQ Asserted Pulse Width (HIRH = 0, HIRD = 1)

327 Data Strobe Deasserted Hold from HIRQ Deassertion

(LT + 1) × T − 6.0

6.5

0.0

4.0

0.0

C

—

1

(HIRH = 0)

1

328 HIRQ Asserted Hold from Data Strobe Assertion (HIRH = 1)

1.5 × T

18.8

—

15.0

—

ns

C

329 HIRQ Deassertion from Data Strobe Assertion

80 MHz: 2.5 × T + 24.7

100 MHz: 2.5 × T + 21.5

55.9

ns

C

1

(HIRH = 1, HIRD = 1)

46.5

C

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-35

Specifications

Table 2-19. Universal Bus Mode, Synchronous Port A Type Host Timing (Continued)

80 MHz

100 MHz

Min Max

No.

Characteristic

Expression

Unit

Min Max

330 HIRQ High Impedance from Data Strobe Assertion

80 MHz: 2.5 × T + 24.7

—

55.9

ns

C

1,6

(HIRH = 1, HIRD = 0)

100 MHz: 2.5 × T + 21.5

—

46.5

—

C

331 HIRQ Active from Data Strobe Deassertion

2.5 × T

31.3

—

25.0

ns

C

1

(HIRH = 1, HIRD = 0)

1

332 HIRQ Deasserted Hold from Data Strobe Deassertion

2.5 × T

31.3

—

22.2

—

25.0

—

19.6

—

ns

C

2

346 HRST Assertion to Host Port Pins High Impedance

347 HBS Assertion to CLKOUT Rising Edge

4.3

7.4

3.4

5.9

1

348 Data Strobe Deassertion to CLKOUT Rising Edge

—

Notes: 1. The Data Strobe is HRD or HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

2. HTA, HDRQ, and HRST may be programmed as active-high or active-low. In the example timing diagrams, HDRQ and HRST

are shown as active-high and HTA is shown as active low.

3. The Read Data Strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

4. The Write Data Strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

5. HTA requires an external pull-down resistor if programmed as active high (HTAP = 0); or an external pull-up resistor if

programmed as active low (HTAP = 1). The resistor value should be consistent with the DC specifications.

6. HIRQ requires an external pull-up resistor if programmed as open drain (HIRD = 0). The resistor value should be consistent

with the DC specifications.

7. “LT” is the value of the latency timer register (CLAT) as programmed by the user during self configuration.

8. Values are valid for V = 3.3 0.3V

CC

HA[10–0]

301

302

HDS

HRD

HWR

305

307

308

HBS

310

309

332

329

HIRQ

(HIRD = 1,

HIRH = 1)

328

331

330

HIRQ

(HIRD = 0,

HIRH = 1)

Figure 2-27. Universal Bus Mode I/O Access Timing

DSP56301 Technical Data, Rev. 10

2-36

Freescale Semiconductor

AC Electrical Characteristics

336

337

HDAK

HDS

HRD

HWR

305

334

335

HDRQ

333

Figure 2-28. Universal Bus Mode DMA Access Timing

HRW

303

304

HDS

Figure 2-29. HRW to HDS Timing

326

HIRQ

332

327

HDS

HRD

HWR

Figure 2-30. HIRQ Pulse Width (HIRH = 0)

HRST

346

HI32

Outputs

Figure 2-31. HRST Timing

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-37

Specifications

306

HDS

HRD

309

307

HBS

310

322

324

321

325

315

320

HTA

323

311

Valid (Output)

HD[23–0]

312

313

314

318

319

HSAK

343

345

342

344

HDBDR

339

341

HDBEN

338

340

Figure 2-32. Read Timing

DSP56301 Technical Data, Rev. 10

2-38

Freescale Semiconductor

AC Electrical Characteristics

306

HDS

HRD

309

307

HBS

310

322

321

325

320

HTA

323

324

317

HD[23–0]

Valid (Input)

316

318

319

HSAK

HDBDR

HDBEN

339

340

338

341

Figure 2-33. Write Timing

CLKOUT

347

HBS

Figure 2-34. HBS Synchronous Timing

CLKOUT

348

HDS

HRD

HWR

Figure 2-35. Data Strobe Synchronous Timing

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-39

Specifications

Table 2-20. PCI Mode Timing Parameters¹

80 MHz

100 MHz

No.

Characteristic¹⁰

Symbol

Unit

Min

Max

Min

Max

349 HCLK to Signal Valid Delay—Bussed Signals

350 HCLK to Signal Valid Delay—Point to Point

351 Float to Active Delay

t

2.0

11.0

12.0

—

2.0

11.0

12.0

—

ns

ms

μs

ns

VAL

t

VAL(ptp)

t

2.0

ON

352 Active to Float Delay

t

—

28.0

—

28.0

—

OFF

353 Input Set Up Time to HCLK—Bussed Signals

354 Input Set Up Time to HCLK—Point to Point

355 Input Hold Time from HCLK

t

7.0

SU

t

10.0, 12.0

0.0

—

10.0, 12.0

0.0

—

SU(ptp)

t

—

H

356 Reset Active Time After Power Stable

357 Reset Active Time After HCLK Stable

358 Reset Active to Output Float Delay

359 HCLK Cycle Time

t

1.0

—

1.0

—

RST

t

100.0

—

100.0

—

RST-CLK

RST-OFF

t

40.0

—

40.0

—

t

30.0

11.0

30.0

11.0

CYC

360 HCLK High Time

t

—

HIGH

361 HCLK Low Time

t

—

LOW

Notes: 1. For standard PCI timing, see the PCI Local Bus Specification, Rev. 2.0, especially Chapters 3 and 4.

2. The HI32 supports these timings for a PCI bus operating at 33 MHz for a DSP clock frequency of 56 MHz and above. The DSP

core operating frequency should be greater than 5/3 of the PCI bus frequency to maintain proper PCI operation.

3. HGNT has a setup time of 10 ns. HREQ has a setup time of 12 ns.

359

361

HCLK

360

349

350

OUTPUT

DELAY

351

High

Impedance

OUTPUT

352

INPUT

353

355

354

Figure 2-36. PCI Timing

DSP56301 Technical Data, Rev. 10

2-40

Freescale Semiconductor

AC Electrical Characteristics

POWER

HCLK

357

356

HRST

358

PCI Signals

Figure 2-37. PCI Reset Timing

Table 2-21. SCI Timing

2.5.7 SCI Timing

80 MHz

100 MHz

No.

Characteristics¹

Symbol

Expression

Unit

Min Max Min Max

2

400 Synchronous clock cycle

401 Clock low period

t

8 × T

100.0

40.0

14.3

—

80.0

30.0

8.0

—

ns

SCC

C

t

/2 − 10.0

SCC

402 Clock high period

SCC

403 Output data setup to clock falling edge (internal

clock)

t

/4 + 0.5 × T −17.0

SCC

C

404 Output data hold after clock rising edge (internal

clock)

t

/4 − 0.5 × T

18.8

56.3

—

15.0

50.0

—

ns

SCC

C

405 Input data setup time before clock rising edge

(internal clock)

t

/4 + 0.5 × T + 25.0

SCC

C

406 Input data not valid before clock rising edge

(internal clock)

t

/4 + 0.5 × T − 5.5

25.8

32.0

—

19.5

32.0

—

SCC

C

407 Clock falling edge to output data valid (external

clock)

—

408 Output data hold after clock rising edge (external

clock)

T

+ 8.0

20.5

0.0

9.0

18.0

0.0

9.0

C

409 Input data setup time before clock rising edge

(external clock)

—

410 Input data hold time after clock rising edge (external

clock)

—

3

411 Asynchronous clock cycle

412 Clock low period

t

64 × T

800.0

390.0

370.0

—

640.0

310.0

290.0

—

ns

ACC

C

t

/2 − 10.0

/2 − 30.0

ACC

413 Clock high period

414 Output data setup to clock rising edge (internal

clock)

415

Output data hold after clock rising edge (internal

clock)

t

/2 − 30.0

370.0

—

290.0

—

ns

ACC

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-41

Specifications

Table 2-21. SCI Timing (Continued)

80 MHz

100 MHz

No.

Characteristics¹

Symbol

Expression

Unit

Min Max Min Max

Notes: 1.

V

t

= 3.3 V 0.3 V; T = −40°C to +100 °C, C = 50 pF

J L

= synchronous clock cycle time (For internal clock, t

= asynchronous clock cycle time; value given for 1X Clock mode (For internal clock, t

CC

SCC

ACC

2.

3.

is determined by the SCI clock control register and T )

SCC C.

is determined by the SCI clock

ACC

control register and T

)

C.

400

402

404

401

SCLK

(Output)

403

Data Valid

405

TXD

406

Data

Valid

RXD

a) Internal Clock

400

402

401

SCLK

(Input)

407

408

TXD

RXD

Data Valid

409

410

Data Valid

b) External Clock

Figure 2-38. SCI Synchronous Mode Timing

DSP56301 Technical Data, Rev. 10

2-42

Freescale Semiconductor

AC Electrical Characteristics

411

413

415

412

414

1X SCLK

(Output)

TXD

Data Valid

Figure 2-39. SCI Asynchronous Mode Timing

2.5.8 ESSI0/ESSI1 Timing

Table 2-22. ESSI Timings

80 MHz

100 MHz

Cond-

Unit

No.

Characteristics^{4, 5, 7}

Symbol

Expression

ition⁶

Min

Max

Min

Max

1

430 Clock cycle

t

3 × T

50.0

37.5

—

30.0

40.0

—

x ck

i ck

ns

SSICC

C

4 × T

C

431 Clock high period

For internal clock

2 × T − 10.0

15.0

18.8

—

10.0

15.0

—

ns

C

For external clock

1.5 × T

C

432 Clock low period

For internal clock

2 × T − 10.0

15.0

18.8

—

10.0

15.0

—

ns

C

For external clock

1.5 × T

C

433 RXC rising edge to FSR out (bl) high

434 RXC rising edge to FSR out (bl) low

435 RXC rising edge to FSR out (wr) high

—

37.0

22.0

—

37.0

22.0

x ck

i ck a

ns

—

37.0

22.0

—

37.0

22.0

x ck

i ck a

2

—

39.0

24.0

—

39.0

24.0

x ck

i ck a

2

436 RXC rising edge to FSR out (wr) low

—

39.0

24.0

—

39.0

24.0

x ck

i ck a

437 RXC rising edge to FSR out (wl) high

438 RXC rising edge to FSR out (wl) low

—

36.0

21.0

—

36.0

21.0

x ck

i ck a

—

37.0

22.0

—

37.0

22.0

x ck

i ck a

439 Data in setup time before RXC (SCK in

Synchronous mode) falling edge

10.0

19.0

—

10.0

19.0

—

x ck

i ck

440 Data in hold time after RXC falling edge

441 FSR input (bl, wr) high before RXC falling edge

442 FSR input (wl) high before RXC falling edge

443 FSR input hold time after RXC falling edge

444 Flags input setup before RXC falling edge

5.0

3.0

—

5.0

3.0

—

x ck

i ck

2

1.0

23.0

—

1.0

23.0

—

x ck

i ck a

3.5

23.0

—

3.5

23.0

—

x ck

i ck a

3.0

0.0

—

3.0

0.0

—

x ck

i ck a

5.5

19.0

—

5.5

19.0

—

x ck

i ck s

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-43

Specifications

Table 2-22. ESSI Timings (Continued)

80 MHz

100 MHz

Min Max

Cond-

ition⁶

No.

Characteristics^{4, 5, 7}

Symbol

Expression

Unit

Min

Max

445 Flags input hold time after RXC falling edge

446 TXC rising edge to FST out (bl) high

447 TXC rising edge to FST out (bl) low

6.0

0.0

—

6.0

0.0

—

x ck

i ck s

ns

—

29.0

15.0

—

29.0

15.0

x ck

i ck

—

31.0

17.0

—

31.0

17.0

x ck

i ck

2

448 TXC rising edge to FST out (wr) high

—

31.0

17.0

—

31.0

17.0

x ck

i ck

2

449 TXC rising edge to FST out (wr) low

—

33.0

19.0

—

33.0

19.0

x ck

i ck

450 TXC rising edge to FST out (wl) high

451 TXC rising edge to FST out (wl) low

—

30.0

16.0

—

30.0

16.0

x ck

i ck

—

31.0

17.0

—

31.0

17.0

x ck

i ck

452 TXC rising edge to data out enable from high

impedance

—

31.0

17.0

—

31.0

17.0

x ck

i ck

453 TXC rising edge to Transmitter #0 drive enable

assertion

—

34.0

20.0

—

34.0

20.0

x ck

i ck

8

454 TXC rising edge to data out valid

—

20.0

10.0

—

20.0

10.0

x ck

i ck

3

455 TXC rising edge to data out high impedance

—

31.0

16.0

—

31.0

16.0

x ck

i ck

456 TXC rising edge to Transmitter #0 drive enable

—

34.0

20.0

—

34.0

20.0

x ck

i ck

3

deassertion

457 FST input (bl, wr) setup time before TXC falling

2.0

21.0

—

2.0

21.0

—

x ck

i ck

2

edge

458 FST input (wl) to data out enable from high

impedance

—

27.0

—

27.0

—

459 FST input (wl) to Transmitter #0 drive enable

assertion

31.0

—

460 FST input (wl) setup time before TXC falling edge

461 FST input hold time after TXC falling edge

462 Flag output valid after TXC rising edge

2.5

21.0

—

2.5

21.0

—

x ck

i ck

4.0

0.0

—

4.0

0.0

—

x ck

i ck

—

32.0

18.0

—

32.0

18.0

x ck

i ck

DSP56301 Technical Data, Rev. 10

2-44

Freescale Semiconductor

AC Electrical Characteristics

Table 2-22. ESSI Timings (Continued)

80 MHz

Min Max

100 MHz

Cond-

Unit

No.

Characteristics^{4, 5, 7}

Symbol

Expression

ition⁶

Min

Max

Notes: 1. For the internal clock, the external clock cycle is defined by the instruction cycle time (timing 7 in Table 2-5 on page 2-6) and

the ESSI control register.

2. The word-relative frame sync signal waveform relative to the clock operates the same way as the bit-length frame sync signal

waveform, but spreads from one serial clock before the first bit clock (same as Bit Length Frame Sync signal), until the one

before the last bit clock of the first word in frame.

3. Periodically sampled and not 100 percent tested

4.

V

= 3.3 V 0.3 V; T = −40°C to +100 °C, C = 50 pF

CC J L

5. TXC (SCK Pin) = Transmit Clock

RXC (SC0 or SCK Pin) = Receive Clock

FST (SC2 Pin) = Transmit Frame Sync

FSR (SC1 or SC2 Pin) Receive Frame Sync

6. i ck = Internal Clock

x ck = External Clock

i ck a = Internal Clock, Asynchronous Mode

(Asynchronous implies that TXC and RXC are two different clocks)

i ck s = Internal Clock, Synchronous Mode

(Synchronous implies that TXC and RXC are the same clock)

7. bl = bit length

wl = word length

wr = word length relative

8. If the DSP core writes to the transmit register during the last cycle before causing an underrun error, the delay is 20 ns + (0.5 ×

T ).

C

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-45

Specifications

430

431

432

TXC

(Input/

Output)

446

447

FST (Bit)

Out

450

451

FST (Word)

Out

454

452

454

455

First Bit

Last Bit

Data Out

459

Transmitter

#0 Drive

Enable

457

453

456

461

FST (Bit) In

458

461

460

FST (Word)

In

462

See Note

Flags Out

Note:

In Network mode, output flag transitions can occur at the start of each time slot within the frame. In

Normal mode, the output flag state is asserted for the entire frame period.

Figure 2-40. ESSI Transmitter Timing

DSP56301 Technical Data, Rev. 10

2-46

Freescale Semiconductor

AC Electrical Characteristics

430

431

RXC

(Input/

432

Output)

433

434

FSR (Bit)

Out

437

438

FSR

(Word)

Out

440

439

Last Bit

First Bit

Data In

443

441

FSR (Bit)

In

443

442

FSR

(Word)

In

444

445

Flags In

Figure 2-41. ESSI Receiver Timing

Table 2-23. Timer Timing

2.5.9 Timer Timing

80 MHz

100 MHz

No.

Characteristics

Expression

Unit

Min

Max

Min

Max

480

481

482

2 × T + 2.0

27.0

9.0

—

22.0

9.0

—

ns

TIO Low

TIO High

C

2 × T + 2.0

C

Timer setup time from TIO (Input) assertion to CLKOUT rising

edge

12.5

10.0

483

484

Synchronous timer delay time from CLKOUT rising edge to the

external memory access address out valid caused by first interrupt

instruction execution

10.25 × T + 1.0

129.1

—

103.5

—

ns

C

CLKOUT rising edge to TIO (Output) assertion

•

Minimum

Maximum

0.5 × T + 0.5

9.8

—

26.1

5.5

—

24.8

ns

C

0.5 × T + 19.8

C

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-47

Specifications

Table 2-23. Timer Timing (Continued)

80 MHz

100 MHz

No.

Characteristics

Expression

Unit

Min

Max

Min

Max

485

CLKOUT rising edge to TIO (Output) deassertion

•

Minimum

Maximum

0.5 × T + 0.5

9.8

—

26.1

5.5

—

24.8

ns

C

0.5 × T + 19.8

C

Note:

V

= 3.3 V 0.3 V; T = −40°C to +100 °C, C = 50 pF

CC J L

TIO

480

481

Figure 2-42. TIO Timer Event Input Restrictions

CLKOUT

TIO (Input)

Address

482

483

First Interrupt Instruction Execution

Figure 2-43. Timer Interrupt Generation

CLKOUT

TIO (Output)

484

485

Figure 2-44. External Pulse Generation

2.5.10 GPIO Timing

Table 2-24. GPIO Timing

80 MHz

100 MHz

No.

Characteristics

Expression

Unit

Min

Max

Min

Max

490

—

0.0

8.5

0.0

84.4

31.0

—

0.0

8.5

0.0

67.5

8.5

—

ns

CLKOUT edge to GPIO out valid (GPIO out delay time)

491 CLKOUT edge to GPIO out not valid (GPIO out hold time)

492 GPIO In valid to CLKOUT edge (GPIO in set-up time)

493 CLKOUT edge to GPIO in not valid (GPIO in hold time)

494 Fetch to CLKOUT edge before GPIO change

—

6.75 × T

—

C

Note:

V

= 3.3 V 0.3 V; T = −40°C to +100 °C, C = 50 pF

CC J L

DSP56301 Technical Data, Rev. 10

2-48

Freescale Semiconductor

AC Electrical Characteristics

CLKOUT

(Output)

490

491

GPIO

(Output)

492

493

GPIO

(Input)

Valid

A[0–23]

494

Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO

and R0 contains the address of GPIO data register.

Figure 2-45. GPIO Timing

2.5.11 JTAG Timing

Table 2-25. JTAG Timing

Characteristics^1,2

All frequencies

Min Max

No.

Unit

500 TCK frequency of operation (1/(T × 3); maximum 22 MHz)

0.0

45.0

20.0

0.0

22.0

—

MHz

ns

C

501 TCK cycle time in Crystal mode

502 TCK clock pulse width measured at 1.5 V

503 TCK rise and fall times

—

3.0

—

504 Boundary scan input data setup time

505 Boundary scan input data hold time

506 TCK low to output data valid

507 TCK low to output high impedance

508 TMS, TDI data setup time

5.0

24.0

0.0

—

40.0

—

0.0

5.0

509 TMS, TDI data hold time

25.0

0.0

—

510 TCK low to TDO data valid

511 TCK low to TDO high impedance

512 TRST assert time

44.0

—

0.0

100.0

40.0

513 TRST setup time to TCK low

—

Notes: 1.

V

= 3.3 V 0.3 V; T = −40°C to +100 °C, C = 50 pF

CC J L

2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-49

Specifications

501

502

V

M

V

M

TCK

(Input)

IH

V

IL

503

Figure 2-46. Test Clock Input Timing Diagram

V

TCK

(Input)

IH

V

IL

504

505

Data

Inputs

Input Data Valid

506

507

506

Data

Outputs

Output Data Valid

Data

Outputs

Data

Outputs

Output Data Valid

Figure 2-47. Boundary Scan (JTAG) Timing Diagram

V

IH

TCK

(Input)

V

IL

509

508

Input Data Valid

TDI

TMS

(Input)

510

TDO

(Output)

Output Data Valid

511

TDO

(Output)

510

TDO

(Output)

Output Data Valid

Figure 2-48. Test Access Port Timing Diagram

DSP56301 Technical Data, Rev. 10

2-50

Freescale Semiconductor

AC Electrical Characteristics

TCK

(Input)

513

TRST

(Input)

512

Figure 2-49. TRST Timing Diagram

2.5.12 OnCE Module TimIng

Table 2-26. OnCE Module Timing

80 MHz

100 MHz

Unit

No.

Characteristics

Expression

Min

Max

Min

Max

500

1/(T × 3),

max: 22.0 MHz

0.0

22.0

0.0

22.0

MHz

TCK frequency of operation

C

514 DE assertion time in order to enter Debug mode

1.5 × T + 10.0

28.8

—

25.0

—

ns

C

515 Response time when DSP56301 is executing NOP

instructions from internal memory

5.5 × T + 30.0

98.8

85.0

C

516 Debug acknowledge assertion time

3 × T – 5.0

47.5

—

25.0

—

ns

C

Note:

V

= 3.3 V 0.3 V; T = −40°C to +100 °C, C = 50 pF

CC J L

DE

514

515

516

Figure 2-50. OnCE—Debug Request

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

2-51

Specifications

DSP56301 Technical Data, Rev. 10

2-52

Freescale Semiconductor

Packaging

3

This section provides information on the available packages for the DSP56301, including diagrams of the package

pinouts and tables showing how the signals discussed in Section 1 are allocated for each package. The DSP56301

is available in two package types:

•

208-pin Thin Quad Flat Pack (TQFP)

252-pin Molded Array Process-Ball Grid Array (MAP-BGA)

Note: Both packages are available in lead-bearing and lead-free versions. Switching a design from a lead-bearing

package device to a lead-free package device may require a change in the board manufacturing process.

The lead-free package requires a higher solder flow temperature than the lead-bearing device. Refer to

Lead-Free BGA Solder Joint Assembly Evaluation (EB635) for manufacturing considerations when

incorporating lead-free package devices into a design.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

3-1

Packaging

3.1 TQFP Package Description

Top and bottom views of the TQFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs.

NC

157

MODB

MODA

D23

D22

D21

V_CCD

GND_D

D20

D19

D18

D17

D16

D15

V_CCD

GND_D

D14

D13

D12

D11

D10

D9

HAD11

HAD10

HAD9

HAD8

HC0

HAD7

HAD6

HAD5

HAD4

GND_H

V_CCH

HAD3

HAD2

HAD1

HAD0

TIO2

TIO1

TIO0

RXD

SCLK

V_CCS

GND_S

HINTA

V_CCQ

GND_Q

TXD

V_CCD

GND_D

V_CCQ

GND_Q

D8

SC12

SC11

SC10

STD1

SCK1

SRD1

SRD0

SCK0

V_CCS

GND_S

STD0

SC00

SC01

SC02

DE

TMS

TCK

TDI

TDO

TRST

BS

BL

D7

D6

D5

D4

D3

V_CCD

GND_D

D2

D1

D0

A23

A22

V_CCA

GND_A

A21

A20

A19

A18

V_CCA

GND_A

A17

A16

NC

Orientation Mark

(Top View)

NC

53

Figure 3-1. DSP56301 Thin Quad Flat Pack (TQFP), Top View

DSP56301 Technical Data, Rev. 10

3-2

Freescale Semiconductor

TQFP Package Description

NC

157

MODB

MODA

D23

D22

D21

V_CCD

GND_D

D20

D19

D18

D17

D16

D15

V_CCD

GND_D

D14

D13

D12

D11

D10

D9

HAD11

HAD10

HAD9

HAD8

HC0

HAD7

HAD6

HAD5

HAD4

GND_H

V_CCH

HAD3

HAD2

HAD1

HAD0

TIO2

TIO1

TIO0

RXD

SCLK

V_CCS

GND_S

HINTA

V_CCQ

GND_Q

TXD

V_CCD

GND_D

V_CCQ

GND_Q

D8

D7

SC12

SC11

SC10

STD1

SCK1

SRD1

SRD0

SCK0

V_CCS

GND_S

STD0

SC00

SC01

SC02

DE

D6

D5

D4

D3

V_CCD

GND_D

D2

D1

D0

A23

A22

V_CCA

GND_A

A21

A20

A19

A18

TMS

Orientation Mark

(On Top Side)

TCK

TDI

TDO

TRST

BS

BL

NC

V_CCA

GND_A

A17

A16

NC

(Bottom View)

NC

53

Figure 3-2. DSP56301 Thin Quad Flat Pack (TQFP), Bottom View

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

3-3

Packaging

Table 3-1. DSP56301 TQFP Signal Identification by Pin Number

No.

Signal Name

1

AA0/RAS0

AA1/RAS1

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

EXTAL

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

A14

A15

NC

2

GND

Q

3

V

BCLK

A0

CCN

4

GND

NC

N

5

CLKOUT

BCLK

A1

A16

A17

6

GND

A

7

CAS

V

GND

A

CCA

8

TA

A2

A3

V

CCA

9

PINIT/NMI

RESET

A18

A19

A20

A21

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

A4

V

A5

CCP

PCAP

GND

A

GND

V

GND

A

P

CCA

GND

BB

A6

A7

V

CCA

P1

A22

A23

D0

BG

BR

A8

A9

V

GND

D1

CCN

A

GND

V

D2

N

CCA

AA2/RAS2

AA3/RAS3

WR

A10

A11

A12

A13

GND

D

V

CCD

D3

D4

D5

D6

RD

XTAL

GND

A

V

CCA

CCQ

DSP56301 Technical Data, Rev. 10

3-4

Freescale Semiconductor

TQFP Package Description

Signal Name

Table 3-1. DSP56301 TQFP Signal Identification by Pin Number (Continued)

No.

Signal Name

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

D7

D8

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

MODA/IRQA

MODB/IRQB

NC

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

HAD17 or HD9

HAD16 or HD8

GND

HC2/HBE2, HA2, or PB18

HIDSEL or HRD/HDS

HFRAME

Q

D

V

NC

CCQ

GND

MODC/IRQC

MODD/IRQD

HAD31 or HD23

HAD30 or HD22

HAD29 or HD21

HAD28 or HD20

V

CCQ

CCD

D9

GND

Q

D10

D11

D12

D13

D14

HIRDY, HDBDR, or PB21

HTRDY, HDBEN, or PB20

V

CCH

V

GND

H

CCH

GND

PVCL

H

GND

HAD27 or HD19

HAD26 or HD18

HAD25 or HD17

HAD24 or HD16

HC3/HBE3 or PB19

HAD23 or HD15

HAD22 or HD14

HAD21 or HD13

HAD20 or HD12

HDEVSEL, HSAK, or PB22

HSTOP or HWR/HRW

HLOCK, HBS, or PB23

HPERR or HDRQ

D

V

CCD

D15

D16

D17

D18

D19

D20

HSERR or HIRQ

GND

H

V

CCH

HPAR or HDAK

HREQ or HTA

GND

D

V

HRST or HRST

HCLK

CCD

CCH

D21

D22

D23

GND

H

HAD19 or HD11

HAD18 or HD10

HGNT or HAEN

HC1/HBE1, HA1, or PB17

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

3-5

Packaging

Table 3-1. DSP56301 TQFP Signal Identification by Pin Number (Continued)

No.

Signal Name

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

HAD15, HD7, or PB15

HAD14, HD6, or PB14

HAD13, HD5, or PB13

HAD12, HD4, or PB12

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

HAD2, HA5, or PB2

HAD1, HA4, or PB1

HAD0, HA3, or PB0

TIO2

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

SRD0 or PC4

SCK0 or PC3

V

CCS

GND

S

GND

TIO1

STD0 or PC5

H

V

TIO0

SC00 or PC0

CCH

NC

RXD or PE0

SCLK or PE2

SC01 or PC1

NC

SC02 or PC2

DE

HAD11, HD3, or PB11

HAD10, HD2, or PB10

HAD9, HD1, or PB9

HAD8, HD0, or PB8

HC0/HBE0, HA0, or PB16

HAD7, HA10, or PB7

HAD6, HA9, or PB6

HAD5, HA8, or PB5

HAD4, HA7, or PB4

V

CCS

GND

TMS

TCK

TDI

S

HINTA

V

CCQ

GND

TDO

TRST

BS

Q

TXD or PE1

SC12 or PD2

SC11 or PD1

SC10 or PD0

STD1 or PD5

SCK1 or PD3

SRD1 or PD4

BL

NC

GND

NC

H

V

CCH

HAD3, HA6, or PB3

Notes: 1. Signal names are based on configured functionality. Most pins supply a single signal. Some pins provide a signal with dual

functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted, but act as interrupt lines

during operation. Some pins have two or more configurable functions; names assigned to these pins indicate the function for a

specific configuration. For example, Pin 165 is address/data line HAD6 in PCI bus mode, address line HA9 in non-PCI bus

mode, or GPIO line PB6 when the GPIO function is enabled for this pin.

2. NC stands for Not Connected. These pins are reserved for future development. Do not connect any line, component, trace, or

via to these pins.

DSP56301 Technical Data, Rev. 10

3-6

Freescale Semiconductor

TQFP Package Description

Table 3-2. DSP56301 TQFP Signal Identification by Name

No.

Signal Name

No.

A0

A1

29

30

45

46

47

48

51

52

55

56

59

60

33

61

62

65

66

34

35

36

39

40

41

42

1

AA3

BB

21

15

6

D3

D4

72

73

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A2

BCLK

BG

D5

74

28

16

206

17

205

7

D6

75

D7

76

BL

D8

77

BR

D9

82

BS

DE

199

26

CAS

CLKOUT

D0

EXTAL

5

GND

14

P1

67

68

83

84

85

86

87

90

91

92

93

94

69

95

98

99

100

GND

31

A

D

H

N

D1

37

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D2

43

A20

A21

A22

A23

A3

49

57

63

70

80

A4

88

A5

96

A6

112

123

136

143

155

168

4

A7

A8

A9

D20

D21

D22

D23

AA0

AA1

AA2

2

20

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

3-7

Packaging

Table 3-2. DSP56301 TQFP Signal Identification by Name (Continued)

No.

Signal Name

GND

19

HAD14

HAD15

HAD16

HAD17

HAD18

HAD19

HAD2

152

151

127

126

125

124

171

121

120

119

118

116

115

114

113

110

109

170

108

107

167

166

165

164

162

161

HAEN

HBE0

HBE1

HBE2

HBE3

HBS

149

163

150

128

117

140

163

150

128

117

148

162

161

125

124

121

120

119

118

116

115

114

113

160

110

109

N

13

P

GND

27

Q

78

132

183

180

194

163

150

164

128

173

172

171

170

167

166

165

173

172

160

159

154

153

HC0

GND

HAD20

HAD21

HAD22

HAD23

HAD24

HAD25

HAD26

HAD27

HAD28

HAD29

HAD3

HC1

S

HC2

HA0

HA1

HC3

HCLK

HD0

HA10

HA2

HD1

HA3

HD10

HD11

HD12

HD13

HD14

HD15

HD16

HD17

HD18

HD19

HD2

HA4

HA5

HA6

HA7

HA8

HAD30

HAD31

HAD4

HA9

HAD0

HAD1

HAD10

HAD11

HAD12

HAD13

HAD5

HAD6

HAD7

HAD8

HD20

HD21

HAD9

DSP56301 Technical Data, Rev. 10

3-8

Freescale Semiconductor

TQFP Package Description

Table 3-2. DSP56301 TQFP Signal Identification by Name (Continued)

No.

Signal Name

HD22

HD23

108

107

159

154

153

152

151

127

126

145

133

134

138

141

129

130

149

129

181

133

142

140

145

141

129

146

HRST/HRST

HRW

HSAK

HSERR

HSTOP

HTA

147

139

138

142

139

146

134

139

101

102

105

106

101

102

105

106

28

PB0

PB1

173

172

160

159

154

153

152

151

163

150

128

117

171

134

133

138

140

170

167

166

165

164

162

161

196

197

HD3

PB10

PB11

PB12

PB13

PB14

PB15

PB16

PB17

PB18

PB19

PB2

HD4

HD5

HD6

HD7

HTRDY

HWR

IRQA

IRQB

IRQC

IRQD

MODA

MODB

MODC

MODD

NC

HD8

HD9

HDAK

HDBDR

HDBEN

HDEVSEL

HDRQ

HDS

PB20

PB21

PB22

PB23

PB3

HFRAME

HGNT

HIDSEL

HINTA

HIRDY

HIRQ

NC

53

NC

54

PB4

NC

103

104

157

158

207

208

9

PB5

NC

PB6

HLOCK

HPAR

HPERR

HRD

NC

PB7

NC

PB8

NC

PB9

NC

PC0

HREQ

NMI

PC1

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

3-9

Packaging

Table 3-2. DSP56301 TQFP Signal Identification by Name (Continued)

No.

Signal Name

PC2

PC3

198

192

191

195

12

SC02

SC10

SC11

SC12

SCK0

SCK1

SCLK

SRD0

SRD1

STD0

STD1

TA

198

187

186

185

192

189

178

191

190

195

188

8

V

58

64

CCA

CCD

CCH

PC4

71

PC5

81

PCAP

PD0

89

187

186

185

189

190

188

177

184

178

9

97

PD1

111

122

135

144

156

169

3

PD2

PD3

PD4

PD5

PE0

PE1

TCK

201

202

203

176

175

174

200

204

184

32

CCN

CCP

PE2

TDI

18

PINIT

PVCL

RAS0

RAS1

RAS2

RAS3

RD

TDO

11

TIO0

TIO1

TIO2

TMS

TRST

TXD

25

137

1

CCQ

V

79

131

182

179

193

2

20

V

21

CCS

23

RESET

RXD

SC00

SC01

V

WR

10

22

24

CCA

V

XTAL

177

196

197

38

CCA

V

44

CCA

V

50

CCA

Note:

NC stands for Not Connected. These pins are reserved for future development. Do not connect any line, component, or trace to

these pins.

DSP56301 Technical Data, Rev. 10

3-10

Freescale Semiconductor

TQFP Package Mechanical Drawing

3.2 TQFP Package Mechanical Drawing

G

P

4X

4X 52 TIPS

157

0.2 T L-M N

208

Pin 1

ident

C

L

AB

1

156

X

X= L, M or N

View Y

Plating

F

Base metal

J

M

3X view Y

U

D

B

V

M

0.08 T L-M N

L

Section AB-AB

0

rotated 90 clockwise

208 places

B1

Notes:

1.Dimensioning and tolerancing per ANSI

Y14.5M, 1982.

V1

2.Controlling dimension: millimeter.

3. Datum plane-H- is located at bottom of

lead and is coincident with the lead

52

105

where the lead exits the plastic body at

the bottom of the parting line.

4. Datums -L-, -M-, and -N- to be

104

53

determined at datum plane -H-.

N

5. Dimensions S and V to be determined

at seating place -T-.

A1

S1

6. Dimensions A and B do not include

mold protrusion. Allowable protrusion

is 0.25 per side. Dimensions A and B

do include mold mismatch and are

determined at datum plane -H-.

A

S

7. Dimension d does not include dambar

protrusion. Dambar protrusion shall

not cause the lead width to exceed

0.35 minimum space between

View AA

protrusion and adjacent lead 0.07.

C

Millimeters

DIM MIN

MAX

28.00 BSC

14.00 BSC

Seating

plane

A

A1

B

B1

C

^4X(q2)

28.00 BSC

14.00 BSC

208X

0.08 T

T

---

0.05

1.35

0.17

0.45

0.17

1.60

C1

C2

D

---

1.45

0.27

0.75

0.23

0.05

(W)

q1

2X R R1

0.25

E

F

G

J

0.50 BSC

0.09

0.20

C2

K

P

R1

S

S1

U

0.50 REF

0.25 BSC

0.10 0.20

30.00 BSC

15.00 BSC

Gage

plane

(K)

0.09

0.16

q

C1

V

30.00 REF

15.00 REF

0.20 REF

1.00 REF

E

V1

W

Z

(Z)

View AA

q

q1

q2

0

7

---

CASE 998-01

12 REF

Figure 3-3. DSP56301 Mechanical Information, 208-pin TQFP Package

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

3-11

Packaging

3.3 MAP-BGA Package Description

Top and bottom views of the MAP-BGA package are shown in Figure 3-4 and Figure 3-5 with their pin-outs.

Top View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A

B

NC

HAD15 HCLK HPAR HPERR HIRDY HAD16 HAD17 HAD20 HAD23 HAD24 HAD27 HAD30

NC

HDEV

SEL

NC

HAD14 HGNT HRST HSERR

HIDSEL HC2 HAD19 HAD22 HAD25 HAD29 HAD31

H

NC

C

D

E

F

HAD8 HAD11 HAD12 HAD13 HC1

HAD5 HAD7 HAD9 HAD10 V_CC

HREQ HLOCK

HAD18 HAD21 HC3 HAD26 MODD

NC

D23

D21

D17

FRAME

PVCL HSTOP HTRDY V_CC

V_CC

V_CCHAD28 MODC

NC

MODB

HAD2 HAD4 HAD6

HAD1 HAD0 HAD3

HC0

V_CC

D18

MODA D22

V_CC

GND

V_CC

D19

D20

G

H

TI01

RXD

TI02

V_CC

GND

V_CC

D12

D11

D15

D9

D16

D13

D14

D8

SCLK HINTA TI00

V_CC

J

SC11 SC12

TXD

SC10

V_CC

GND

V_CC

D5

D10

D7

K

L

STD1 SCK1 SCK0 SRD0

SRD1 STD0 SC02 SC01

V_CC

GND

V_CC

D3

D0

D6

D2

D4

D1

V_CC

M

N

P

R

T

SC00

TCK

TRST

NC

DE

TDI

BS

TDO

NC

TMS

BL

V_CC

TA

V_CC

BG

V_CC

AA3

V_CC

A1

V_CC

A2

V_CC

A8

V_CC

A12

A9

A19

A16

NC

A21

A17

A15

A14

A13

A22

A20

NC

A23

NC

V_CC

CLK

OUT

AA0

AA1

PINIT GND_P

EXTAL

A5

A18

NC

CAS

V_CCP

BB

AA2

BR

XTAL BCLK

A3

A6

A11

A10

BCLK RESET PCAP GND_P1

WR

RD

A0

A4

A7

Figure 3-4. DSP56301 Molded Array Process-Ball Grid Array (MAP-BGA), Top View

DSP56301 Technical Data, Rev. 10

3-12

Freescale Semiconductor

MAP-BGA Package Description

Bottom View

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A

B

NC

HAD30 HAD27 HAD24 HAD23 HAD20 HAD17 HAD16 HIRDY HPERR HPAR HCLK HAD15

NC

HDEV

SEL

NC

HAD31 HAD29 HAD25 HAD22 HAD19 HC2 HIDSEL

H

HSERR HRST HGNT HAD14

NC

C

D

E

F

NC

D23

D21

D17

NC

MODD HAD26 HC3 HAD21 HAD18

HLOCK HREQ

HC1 HAD13 HAD12 HAD11 HAD8

V_CCHAD10 HAD9 HAD7 HAD5

FRAME

MODB

NC

MODC HAD28 V_CC

V_CC

V_CCHTRDY HSTOP PVCL

D22 MODA

V_CC

D18

V_CC

HC0

V_CC

HAD6 HAD4 HAD2

HAD3 HAD0 HAD1

D20

D19

V_CC

GND

V_CC

G

H

D14

D8

D16

D13

D10

D15

D9

D12

D11

V_CC

GND

V_CC

TI02

RXD

TI01

V_CC

TI00 HINTA SCLK

J

D7

D5

GND

SC10

TXD

SC12 SC11

K

L

D4

D1

D6

D2

D3

D0

V_CC

GND

V_CC

SRD0 SCK0 SCK1 STD1

SC01 SC02 STD0 SRD1

V_CC

M

N

P

R

T

A23

NC

A22

A20

NC

A21

A17

A15

A14

A13

A19

A16

NC

V_CC

A12

A9

V_CC

A8

V_CC

A2

A5

A3

A0

V_CC

A1

V_CC

BG

V_CC

TA

TMS

BL

TDO

NC

DE

TDI

BS

SC00

TCK

TRST

NC

V_CC

CLK

OUT

A18

NC

EXTAL

BLCK

RD

AA3

XTAL

WR

GND_PPINIT

AA0

AA1

A11

A10

A6

AA2

BR

BB

V_CCP

CAS

NC

A7

A4

GND_P1PCAP RESET BCLK

Figure 3-5. DSP56301 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

3-13

Packaging

Table 3-3. DSP56301 MAP-BGA Signal Identification by Pin Number

No.

Signal Name

A2

A3

NC

HAD15, HD7, or PB15

HCLK

B12

B13

B14

B15

B16

C1

HAD25 or HD17

HAD29 or HD21

HAD31 or HD23

NC

D5

D6

V

CC

PVCL

A4

D7

HSTOP or HWR/HRW

HTRDY, HDBEN, or PB20

A5

HPAR or HDAK

HPERR or HDRQ

HIRDY, HDBDR, or PB21

HAD16 or HD8

HAD17 or HD9

HAD20 or HD12

HAD23 or HD15

HAD24 or HD16

HAD27 or HD19

HAD30 or HD22

NC

D8

A6

NC

D9

V

CC

A7

HAD8, HD0, or PB8

HAD11, HD3, or PB11

HAD12, HD4, or PB12

HAD13, HD5, or PB13

HC1/HBE1, HA1, or PB17

HREQ or HTA

D10

D11

D12

D13

D14

D15

D16

E1

A8

C2

A9

C3

HAD28 or HD20

MODC/IRQC

A10

A11

A12

A13

A14

A15

B1

C4

C5

NC

C6

MODB/IRQB

C7

HLOCK, HBS, or PB23

HFRAME

D23

C8

HAD2, HA5, or PB2

HAD4, HA7, or PB4

HAD6, HA9, or PB6

HC0/HBE0, HA0, or PB16

C9

HAD18 or HD10

HAD21 or HD13

HC3/HBE3 or PB19

HAD26 or HD18

MODD/IRQD

E2

NC

C10

C11

C12

C13

C14

C15

C16

D1

E3

B2

NC

E4

B3

HAD14, HD6, or PB14

HGNT or HAEN

HRST/HRST

E5

V

CC

B4

E6

B5

NC

E7

B6

HSERR or HIRQ

HDEVSEL, HSAK, or PB22

HIDSEL or HRD/HDS

HC2/HBE2, HA2, or PB18

HAD19 or HD11

HAD22 or HD14

NC

E8

B7

NC

E9

B8

HAD5, HA8, or PB5

HAD7, HA10, or PB7

HAD9, HD1, or PB9

HAD10, HD2, or PB10

E10

E11

E12

E13

B9

D2

B10

B11

D3

D4

DSP56301 Technical Data, Rev. 10

3-14

Freescale Semiconductor

MAP-BGA Package Description

Signal Name

Table 3-3. DSP56301 MAP-BGA Signal Identification by Pin Number (Continued)

No.

Signal Name

E14

E15

E16

F1

MODA/IRQA

D22

G7

G8

GND

H16

J1

D8

SC11 or PD1

SC12 or PD2

TXD or PE1

SC10 or PD0

D21

G9

J2

HAD1, HA4, or PB1

HAD0, HA3, or PB0

HAD3, HA6, or PB3

G10

G11

G12

G13

G14

G15

G16

H1

J3

F2

J4

F3

V

J5

V

CC

F4

V

D12

D15

J6

GND

CC

F5

J7

F6

GND

D16

J8

F7

D14

J9

F8

SCLK or PE2

HINTA

TIO0

J10

J11

J12

J13

J14

J15

J16

K1

K2

K3

K4

K5

K6

K7

K8

F9

H2

F10

F11

F12

F13

F14

F15

F16

G1

G2

G3

G4

G5

G6

H3

V

CC

H4

V

CC

V

H5

D5

CC

D18

D19

H6

GND

D10

H7

D7

D20

H8

STD1 or PD5

SCK1 or PD3

SCK0 or PC3

SRD0 or PC4

D17

H9

TIO1

H10

H11

H12

H13

H14

H15

RXD or PE0

TIO2

V

CC

V

D11

D9

GND

CC

GND

D13

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

3-15

Packaging

Table 3-3. DSP56301 MAP-BGA Signal Identification by Pin Number (Continued)

No.

Signal Name

K9

K10

K11

K12

K13

K14

K15

K16

L1

GND

M2

M3

DE

N11

N12

N13

N14

N15

N16

P1

V

CC

TDO

TMS

M4

A16

A17

V

M5

V

CC

M6

A20

D3

M7

NC

D6

M8

TRST

BS

D4

M9

P2

SRD1 or PD4

STD0 or PC5

SC02 or PC2

SC01 or PC1

M10

M11

M12

M13

M14

M15

M16

N1

P3

AA0/RAS0

CLKOUT

PINIT/NMI

L2

P4

L3

P5

L4

A19

A21

A22

A23

TCK

TDI

NC

P6

GND

BG

P

L5

V

P7

CC

L6

GND

P8

AA3/RAS3

EXTAL

A5

L7

P9

L8

P10

P11

P12

P13

P14

P15

P16

R1

L9

N2

A8

L10

L11

L12

L13

L14

L15

L16

M1

N3

A12

N4

BL

NC

V

N5

TA

A15

CC

N6

V

NC

CC

D0

D2

N7

A18

N8

NC

D1

N9

A1

A2

R2

NC

SC00 or PC0

N10

R3

AA1/RAS1

DSP56301 Technical Data, Rev. 10

3-16

Freescale Semiconductor

MAP-BGA Package Description

Signal Name

Table 3-3. DSP56301 MAP-BGA Signal Identification by Pin Number (Continued)

No.

Signal Name

R4

R5

CAS

R13

R14

R15

R16

T2

A11

A14

T7

T8

BR

WR

RD

A0

V

CCP

R6

BB

AA2/RAS2

XTAL

BCLK

A3

NC

T9

R7

NC

T10

T11

T12

T13

T14

T15

R8

NC

A4

R9

T3

BCLK

RESET

PCAP

A7

R10

R11

R12

T4

A10

A13

NC

A6

T5

A9

T6

GND

P1

Notes: 1. Signal names are based on configured functionality. Most connections supply a single signal. Some connections provide a

signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted, but act as

interrupt lines during operation. Some signals have configurable polarity; these names are shown with and without overbars,

such as HAS/HAS. Some connections have two or more configurable functions; names assigned to these connections indicate

the function for a specific configuration. For example, connection N2 is data line H7 in non-multiplexed bus mode, data/address

line HAD7 in multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin. Unlike the TQFP

package, most of the GND pins are connected internally in the center of the connection array and act as heat sink for the chip.

Therefore, except for GND and GND that support the PLL, other GND signals do not support individual subsystems in the

P

P1

chip.

2. NC stands for Not Connected. The following pin groups are shorted to each other:

— pins A2, B1, and B2

— pins A15, B15, B16, C14, C15, C16, and D14

— pins N3, R1, R2, and T2

— pins N16, P13, P15, R15, R16, and T15

Do not connect any line, component, trace, or via to these pins.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

3-17

Packaging

Table 3-4. DSP56301 MAP-BGA Signal Identification by Name

No.

Signal Name

A0

A1

T10

N9

AA2

AA3

BB

R7

P8

D22

D23

D3

E15

D16

K14

K16

J14

K15

J16

H16

H14

M2

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A2

T13

R13

P12

T14

R14

P14

N13

N14

P16

M13

N10

N15

M14

M15

M16

R10

T11

P10

R11

T12

P11

R12

P3

R6

BCLK

BG

T3

D4

R9

D5

P7

D6

BL

N4

D7

BR

T7

D8

BS

P2

D9

CAS

CLKOUT

D0

R4

DE

P4

EXTAL

GND

P9

L14

L16

J15

H13

G13

H15

G16

G14

G15

F16

F13

F14

L15

F15

E16

F10

F11

F6

D1

A20

A21

A22

A23

A3

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D2

F7

F8

F9

G10

G11

G6

A4

A5

A6

G7

A7

G8

A8

G9

A9

H10

H11

H6

AA0

AA1

D20

D21

R3

DSP56301 Technical Data, Rev. 10

3-18

Freescale Semiconductor

MAP-BGA Package Description

Table 3-4. DSP56301 MAP-BGA Signal Identification by Name (Continued)

No.

Signal Name

GND

H7

H8

H9

J10

J11

J6

HA10

HA2

D2

B9

F2

HAD23

HAD24

HAD25

HAD26

HAD27

HAD28

HAD29

HAD3

HAD30

HAD31

HAD4

HAD5

HAD6

HAD7

HAD8

HAD9

HAEN

HBE0

HBE1

HBE2

HBE3

HBS

A11

A12

B12

C12

A13

D12

B13

F3

HA3

HA4

F1

HA5

E1

F3

HA6

J7

HA7

E2

D1

E3

F2

J8

HA8

J9

HA9

A14

B14

E2

K10

K11

K6

K7

K8

K9

L10

L11

L6

HAD0

HAD1

HAD10

HAD11

HAD12

HAD13

HAD14

HAD15

HAD16

HAD17

HAD18

HAD19

HAD2

HAD20

HAD21

HAD22

F1

D4

C2

C3

C4

B3

A3

A8

A9

C9

B10

E1

A10

C10

B11

D1

E3

D2

C1

D3

B4

E4

L7

C5

L8

B9

L9

C11

C7

GND

T6

P1

GND

P6

E4

C5

HC0

E4

P

HA0

HA1

HC1

C5

HC2

B9

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

3-19

Packaging

Table 3-4. DSP56301 MAP-BGA Signal Identification by Name (Continued)

No.

Signal Name

HC3

HCLK

HD0

C11

A4

HD9

HDAK

A9

A5

A7

D8

B7

A6

B8

C8

B4

B8

H2

A7

B6

C7

A5

A6

B8

C6

B5

D7

B7

B6

D7

C6

D8

HWR

IRQA

IRQB

IRQC

IRQD

MODA

MODB

MODC

MODD

NC

D7

E14

D15

D13

C13

E14

D15

D13

C13

A15

A2

C1

HDBDR

HDBEN

HDEVSEL

HDRQ

HDS

HD1

D3

HD10

HD11

HD12

HD13

HD14

HD15

HD16

HD17

HD18

HD19

HD2

C9

B10

A10

C10

B11

A11

A12

B12

C12

A13

D4

HFRAME

HGNT

HIDSEL

HINTA

HIRDY

HIRQ

NC

B1

NC

B15

B16

B2

HLOCK

HPAR

NC

HD20

HD21

HD22

HD23

HD3

D12

B13

A14

B14

C2

HPERR

HRD

NC

C14

C15

C16

D14

N16

N3

NC

HREQ

NC

HRST/HRST

HRW

NC

HD4

C3

HSAK

NC

HD5

C4

HSERR

HSTOP

HTA

NC

P13

P15

R1

HD6

B3

NC

HD7

A3

NC

HD8

A8

HTRDY

NC

R2

DSP56301 Technical Data, Rev. 10

3-20

Freescale Semiconductor

MAP-BGA Package Description

Table 3-4. DSP56301 MAP-BGA Signal Identification by Name (Continued)

No.

Signal Name

NC

R15

R16

T2

PB6

PB7

E3

D2

C1

D3

M1

L4

L3

K3

K4

L2

T5

J4

RAS3

RD

P8

T9

T4

G2

M1

L4

NC

PB8

RESET

RXD

NC

T15

P5

F2

PB9

NMI

PC0

PC1

PC2

PC3

PC4

PC5

PCAP

PD0

PD1

PD2

PD3

PD4

PD5

PE0

SC00

SC01

SC02

SC10

SC11

SC12

SCK0

SCK1

SCLK

SRD0

SRD1

STD0

STD1

TA

PB0

PB1

F1

L3

PB10

PB11

PB12

PB13

PB14

PB15

PB16

PB17

PB18

PB19

PB2

D4

C2

C3

C4

B3

A3

E4

C5

B9

C11

E1

D8

A7

B7

C7

F3

J4

J1

J2

K3

K2

H1

K4

L1

J1

J2

K2

L1

K1

G2

J3

L2

K1

N5

N1

N2

M3

H3

G1

G3

M4

PB20

PB21

PB22

PB23

PB3

PE1

TCK

PE2

H1

P5

D6

P3

R3

R7

TDI

PINIT

PVCL

RAS0

RAS1

RAS2

TDO

TIO0

TIO1

TIO2

TMS

PB4

E2

D1

PB5

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

3-21

Packaging

Table 3-4. DSP56301 MAP-BGA Signal Identification by Name (Continued)

No.

Signal Name

TRST

TXD

P1

J3

V

F5

G12

G4

V

M10

M11

M12

M5

M6

M7

M8

M9

N11

N12

N6

CC

V

D10

D11

D5

CC

G5

H12

H4

D9

E10

E11

E12

E13

E5

H5

J12

J13

J5

K12

K13

K5

E6

N7

E7

N8

E8

L12

L13

L5

V

R5

CCP

E9

WR

T8

F12

F4

XTAL

R8

Note:

NC stands for Not Connected. The following pin groups are shorted to each other:

—pins A2, B1, and B2

—pins A15, B15, B16, C14, C15, C16, and D14

—pins N3, R1, R2, and T2

—pins N16, P13, P15, R15, R16, and T15

Do not connect any line, component, trace, or via to these pins.

DSP56301 Technical Data, Rev. 10

3-22

Freescale Semiconductor

MAP-BGA Package Mechanical Drawing

3.4 MAP-BGA Package Mechanical Drawing

Notes:

1. Dimensions are in millimeters.

2. Interpret dimensions and

tolerances per ASME Y14.5M,

1994.

3. Dimension b is measured at the

maximum solder ball diameter,

parallel to datum plane Z.

4. Datum Z (seating plane) is

defined by the spherical crowns

of the solder balls.

5. Parallelism measurement shall

exclude any effect of mark on

top surface of package.

Millimeters

DIM MIN MAX

1.6

A

1.9

A1 0.50 0.70

A2 1.16 REF

b

D

E

e

0.60 0.90

21.00 BSC

1.27 BSC

Figure 3-6. DSP56301 Mechanical Information, 252-pin MAP-BGA Package

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

3-23

Packaging

DSP56301 Technical Data, Rev. 10

3-24

Freescale Semiconductor

Design Considerations

4

4.1 Thermal Design Considerations

An estimate of the chip junction temperature, T , in °C can be obtained from this equation:

J

Equation 1: T_J= T_A+ (P_D× R_θJA

)

Where:

T

=

ambient temperature °C

A

R

package junction-to-ambient thermal resistance °C/W

power dissipation in package

θJA

P

D

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-

to-ambient thermal resistance, as in this equation:

Equation 2: R_θJA= R_θJC+ R_θCA

Where:

R

=

package junction-to-ambient thermal resistance °C/W

package junction-to-case thermal resistance °C/W

package case-to-ambient thermal resistance °C/W

θJA

θJC

θCA

R

is device-related and cannot be influenced by the user. The user controls the thermal environment to change

θJC

the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around the device, add

θCA

a heat sink, change the mounting arrangement on the printed circuit board (PCB) or otherwise change the thermal

dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages

with heat sinks; some 90 percent of the heat flow is dissipated through the case to the heat sink and out to the

ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case

and an alternate path through the PCB, analysis of the device thermal performance may need the additional

modeling capability of a system-level thermal simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the

package is mounted. Again, if the estimates obtained from R

do not satisfactorily answer whether the thermal

θJA

performance is adequate, a system-level model may be appropriate.

A complicating factor is the existence of three common ways to determine the junction-to-case thermal resistance

in plastic packages.

•

To minimize temperature variation across the surface, the thermal resistance is measured from the junction

to the outside surface of the package (case) closest to the chip mounting area when that surface has a

proper heat sink.

•

To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is

measured from the junction to the point at which the leads attach to the case.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

4-1

Design Considerations

•

If the temperature of the package case (T ) is determined by a thermocouple, thermal resistance is

T

computed from the value obtained by the equation (T – T )/P .

J

T

D

As noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using the first

definition. From a practical standpoint, that value is also suitable to determine the junction temperature from a case

thermocouple reading in forced convection environments. In natural convection, the use of the junction-to-case

thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will

yield an estimate of a junction temperature slightly higher than actual temperature. Hence, the new thermal metric,

thermal characterization parameter or Ψ , has been defined to be (T – T )/P . This value gives a better estimate

JT

J

T

D

of the junction temperature in natural convection when the surface temperature of the package is used. Remember

that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of

the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a

40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.

4.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to

guard against damage due to high static

voltage or electrical fields. However, normal

precautions are advised to avoid application

of any voltages higher than maximum rated

voltages to this high-impedance circuit.

Reliability of operation is enhanced if unused

inputs are tied to an appropriate logic voltage

level (for example, either GND or V ).

CC

Use the following list of recommendations to ensure correct DSP operation.

•

Provide a low-impedance path from the board power supply to each V_CCpin on the DSP and from the

board ground to each GND pin.

Use at least six 0.01–0.1 μF bypass capacitors positioned as close as possible to the four sides of the

package to connect the V_CCpower source to GND.

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V_CCand GND pins

are less than 0.5 inch per capacitor lead.

•

Use at least a four-layer PCB with two inner layers for V_CCand GND.

Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This

recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQC, IRQD,

TA, and BG pins. Maximum PCB trace lengths on the order of 6 inches are recommended.

Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate

capacitance. This is especially critical in systems with higher capacitive loads that could create higher

transient currents in the V_CCand GND circuits.

•

All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the three pins with

internal pull-up resistors (TRST, TMS, DE).

•

Take special care to minimize noise levels on the V_CCP, GND_P, and GND_P1pins.

The following pins must be asserted after power-up: RESET and TRST.

DSP56301 Technical Data, Rev. 10

4-2

Freescale Semiconductor

Power Consumption Considerations

•

If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies due

to synchronous operation of the devices.

RESET must be asserted when the chip is powered up. A stable EXTAL signal should be supplied before

deassertion of RESET.

At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip V never

CC

exceeds 3.5 V.

4.3 Power Consumption Considerations

Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current consumption

are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is

charging and discharging the capacitances of the pins and internal nodes.

Current consumption is described by this formula:

Equation 3: I = C × V × f

Where:

C

V

f

=

node/pin capacitance

voltage swing

frequency of node/pin toggle

Example 1. Current Consumption

For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its maximum possible rate (33

MHz), the current consumption is expressed in Equation 4.

Equation 4: I = 50 × 10^–12× 3.3 × 33 × 10⁶= 5.48 mA

The maximum internal current (I max) value reflects the typical possible switching of the internal buses on best-

CCI

case operation conditions—not necessarily a real application case. The typical internal current (I

) value

CCItyp

reflects the average switching of the internal buses on typical operating conditions. Perform the following steps for

applications that require very low current consumption:

1. Set the EBD bit when you are not accessing external memory.

2. Minimize external memory accesses, and use internal memory accesses.

3. Minimize the number of pins that are switching.

4. Minimize the capacitive load on the pins.

5. Connect the unused inputs to pull-up or pull-down resistors.

6. Disable unused peripherals.

7. Disable unused pin activity (for example, CLKOUT, XTAL).

One way to evaluate power consumption is to use a current-per-MIPS measurement methodology to minimize

specific board effects (that is, to compensate for measured board current not caused by the DSP). A benchmark

power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current

measurements, and the following equation to derive the current-per-MIPS value.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

4-3

Design Considerations

Equation 5: I ⁄ MIPS = I ⁄ MHz = (I_typF2– I_typF1) ⁄ (F2 – F1)

Where:

I

=

current at F2

current at F1

typF2

typF1

F2

F1

=

high frequency (any specified operating frequency)

low frequency (any specified operating frequency lower than F2)

Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The

degree of difference between F1 and F2 determines the amount of precision with which the current rating

can be determined for an application.

4.4 PLL Performance Issues

The following explanations should be considered as general observations on expected PLL behavior. There is no

test that replicates these exact numbers. These observations were measured on a limited number of parts and were

not verified over the entire temperature and voltage ranges.

4.4.1 Phase Skew Performance

The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and CLKOUT

for a given capacitive load on CLKOUT, over the entire process, temperature and voltage ranges. As defined in

Figure 2-2, External Clock Timing, on page -5 for input frequencies greater than 15 MHz and the MF ≤ 4, this

skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF

< 10 and input frequencies greater than 10 MHz, this skew is between −1.4 ns and +3.2 ns.

4.4.2 Phase Jitter Performance

The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and

CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on

CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz

and MF ≤ 4, this jitter is less than 0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input

frequencies greater than 10 MHz, this jitter is less than 2 ns.

4.4.3 Frequency Jitter Performance

The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF < 10)

this jitter is smaller than 0.5 per cent. For mid-range MF (10 < MF < 500) this jitter is between 0.5 per cent and

approximately 2 per cent. For large MF (MF > 500), the frequency jitter is 2–3 per cent.

4.5 Input (EXTAL) Jitter Requirements

The allowed jitter on the frequency of EXTAL is 0.5 percent. If the rate of change of the frequency of EXTAL is slow

(that is, it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is

fast (that is, it does not stay at an extreme value for a long time), then the allowed jitter can be 2 percent. The phase

and frequency jitter performance results are valid only if the input jitter is less than the prescribed values.

DSP56301 Technical Data, Rev. 10

4-4

Freescale Semiconductor

Power Consumption Benchmark A

The following benchmark program permits evaluation of DSP power usage in a test situation. It enables the PLL,

disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of synthetic DSP

application data to emulate intensive sustained DSP operation.

;**************************************************************************

;*

*

;* CHECKS

;*

Typical Power Consumption

*

;**************************************************************************

page

200,55,0,0,0

nolist

I_VEC EQU$000000; Interrupt vectors for program debug only

START EQU$8000 ; MAIN (external) program starting address

INT_PROG EQU$100 ; INTERNAL program memory starting address

INT_XDAT EQU$0 ; INTERNAL X-data memory starting address

INT_YDAT EQU$0 ; INTERNAL Y-data memory starting address

INCLUDE "ioequ.asm"

INCLUDE "intequ.asm"

list

org

P:START

;

movep #$0123FF,x:M_BCR; BCR: Area 3 : 1 w.s (SRAM)

; Area 2 : 0 w.s (SSRAM)

; Default: 1 w.s (SRAM)

;

movep #$0d0000,x:M_PCTL; XTAL disable

; PLL enable

; CLKOUT disable

;

;Load the program

;

move

do

move

nop

#INT_PROG,r0

#PROG_START,r1

#(PROG_END-PROG_START),PLOAD_LOOP

p:(r1)+,x0

x0,p:(r0)+

PLOAD_LOOP

;

; Load the X-data

;

move

#INT_XDAT,r0

#XDAT_START,r1

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

A-1

Power Consumption Benchmark

do

#(XDAT_END-XDAT_START),XLOAD_LOOP

move

p:(r1)+,x0

x0,x:(r0)+

XLOAD_LOOP

;

;Load the Y-data

;

move

do

move

#INT_YDAT,r0

#YDAT_START,r1

#(YDAT_END-YDAT_START),YLOAD_LOOP

p:(r1)+,x0

x0,y:(r0)+

YLOAD_LOOP

;

jmp

INT_PROG

PROG_START

move

#$0,r0

#$0,r4

#$3f,m0

#$3f,m4

move

;

clr

a

clr

b

move

bset

#$0,x0

#$0,x1

#$0,y0

#$0,y1

#4,omr

; ebd

;

sbr

dor

mac

add

mac

move

#60,_end

x0,y0,ax:(r0)+,x1

x1,y1,ax:(r0)+,x0

a,b

x0,y0,ax:(r0)+,x1

x1,y1,a

y:(r4)+,y1

y:(r4)+,y0

b1,x:$ff

_end

bra

nop

sbr

PROG_END

nop

XDAT_START

;

org

dc

x:0

$262EB9

$86F2FE

$E56A5F

$616CAC

$8FFD75

$9210A

$A06D7B

$CEA798

$8DFBF1

$A063D6

DSP56301 Technical Data, Rev. 10

A-2

Freescale Semiconductor

dc

$6C6657

$C2A544

$A3662D

$A4E762

$84F0F3

$E6F1B0

$B3829

$8BF7AE

$63A94F

$EF78DC

$242DE5

$A3E0BA

$EBAB6B

$8726C8

$CA361

$2F6E86

$A57347

$4BE774

$8F349D

$A1ED12

$4BFCE3

$EA26E0

$CD7D99

$4BA85E

$27A43F

$A8B10C

$D3A55

$25EC6A

$2A255B

$A5F1F8

$2426D1

$AE6536

$CBBC37

$6235A4

$37F0D

$63BEC2

$A5E4D3

$8CE810

$3FF09

$60E50E

$CFFB2F

$40753C

$8262C5

$CA641A

$EB3B4B

$2DA928

$AB6641

$28A7E6

$4E2127

$482FD4

$7257D

$E53C72

$1A8C3

$E27540

XDAT_END

YDAT_START

;

org

dc

y:0

$5B6DA

$C3F70B

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

A-3

Power Consumption Benchmark

dc

$6A39E8

$81E801

$C666A6

$46F8E7

$AAEC94

$24233D

$802732

$2E3C83

$A43E00

$C2B639

$85A47E

$ABFDDF

$F3A2C

$2D7CF5

$E16A8A

$ECB8FB

$4BED18

$43F371

$83A556

$E1E9D7

$ACA2C4

$8135AD

$2CE0E2

$8F2C73

$432730

$A87FA9

$4A292E

$A63CCF

$6BA65C

$E06D65

$1AA3A

$A1B6EB

$48AC48

$EF7AE1

$6E3006

$62F6C7

$6064F4

$87E41D

$CB2692

$2C3863

$C6BC60

$43A519

$6139DE

$ADF7BF

$4B3E8C

$6079D5

$E0F5EA

$8230DB

$A3B778

$2BFE51

$E0A6B6

$68FFB7

$28F324

$8F2E8D

$667842

$83E053

$A1FD90

$6B2689

$85B68E

$622EAF

DSP56301 Technical Data, Rev. 10

A-4

Freescale Semiconductor

dc

$6162BC

$E4A245

YDAT_END

;**************************************************************************

;

EQUATES for DSP56301 I/O registers and ports

Reference: DSP56301 Specifications Revision 3.00

Last update: November 15 1993

Changes:

GPIO for ports C,D and E,

HI32

DMA status reg

PLL control reg

AAR

SCI registers address

SSI registers addr. + split TSR from SSISR

December 19 1993 (cosmetic - page and opt directives)

August 9 1994 ESSI and SCI control registers bit update

;

;**************************************************************************

page

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132,55,0,0,0

mex

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ident

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;------------------------------------------------------------------------

;

EQUATES for I/O Port Programming

;------------------------------------------------------------------------

;

Register Addresses

M_DATH EQU $FFFFCF ; Host port GPIO data Register

M_DIRH EQU $FFFFCE; Host port GPIO direction Register

M_PCRC EQU $FFFFBF; Port C Control Register

M_PRRC EQU $FFFFBE; Port C Direction Register

M_PDRC EQU $FFFFBD ; Port C GPIO Data Register

M_PCRD EQU $FFFFAF ; Port D Control register

M_PRRD EQU $FFFFAE ; Port D Direction Data Register

M_PDRD EQU $FFFFAD; Port D GPIO Data Register

M_PCRE EQU $FFFF9F; Port E Control register

M_PRRE EQU $FFFF9E; Port E Direction Register

M_PDRE EQU $FFFF9D; Port E Data Register

M_OGDB EQU $FFFFFC; OnCE GDB Register

;------------------------------------------------------------------------

;

EQUATES for Host Interface

;------------------------------------------------------------------------

;

Register Addresses

M_DTXS EQU $FFFFCD ; DSP SLAVE TRANSMIT DATA FIFO (DTXS)

M_DTXM EQU $FFFFCC; DSP MASTER TRANSMIT DATA FIFO (DTXM)

M_DRXR EQU $FFFFCB; DSP RECEIVE DATA FIFO (DRXR)

M_DPSR EQU $FFFFCA; DSP PCI STATUS REGISTER (DPSR)

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

A-5

Power Consumption Benchmark

M_DSR EQU $FFFFC9; DSP STATUS REGISTER (DSR)

M_DPAR EQU $FFFFC8; DSP PCI ADDRESS REGISTER (DPAR)

M_DPMC EQU $FFFFC7; DSP PCI MASTER CONTROL REGISTER (DPMC)

M_DPCR EQU $FFFFC6; DSP PCI CONTROL REGISTER (DPCR)

M_DCTR EQU $FFFFC5 ; DSP CONTROL REGISTER (DCTR)

;

Host Control Register Bit Flags

M_HCIE EQU 0 ; Host Command Interrupt Enable

M_STIE EQU 1 ; Slave Transmit Interrupt Enable

M_SRIE EQU 2 ; Slave Receive Interrupt Enable

M_HF35 EQU $38 ; Host Flags 5-3 Mask

M_HF3 EQU 3

M_HF4 EQU 4

M_HF5 EQU 5

; Host Flag 3

; Host Flag 4

; Host Flag 5

M_HINT EQU 6 ; Host Interrupt A

M_HDSM EQU 13 ; Host Data Strobe Mode

M_HRWP EQU 14 ; Host RD/WR Polarity

M_HTAP EQU 15 ; Host Transfer Acknowledge Polarity

M_HDRP EQU 16 ; Host Dma Request Polarity

M_HRSP EQU 17 ; Host Reset Polarity

M_HIRP EQU 18 ; Host Interrupt Request Polarity

M_HIRC EQU 19 ; Host Interupt Request Control

M_HM0 EQU 20 ; Host Interface Mode

M_HM1 EQU 21 ; Host Interface Mode

M_HM2 EQU 22 ; Host Interface Mode

M_HM EQU $700000 ; Host Interface Mode Mask

;

Host PCI Control Register Bit Flags

M_PMTIE EQU 1 ; PCI Master Transmit Interrupt Enable

M_PMRIE EQU 2 ; PCI Master Receive Interrupt Enable

M_PMAIE EQU 4 ; PCI Master Address Interrupt Enable

M_PPEIE EQU 5 ; PCI Parity Error Interrupt Enable

M_PTAIE EQU 7 ; PCI Transaction Abort Interrupt Enable

M_PTTIE EQU 9 ; PCI Transaction Termination Interrupt Enable

M_PTCIE EQU 12

; PCI Transfer Complete Interrupt Enable

M_CLRT EQU 14 ; Clear Transmitter

M_MTT EQU 15 ; Master Transfer Terminate

M_SERF EQU 16 ; HSERR~ Force

M_MACE EQU 18 ; Master Access Counter Enable

M_MWSD EQU 19 ; Master Wait States Disable

M_RBLE EQU 20 ; Receive Buffer Lock Enable

M_IAE EQU 21 ; Insert Address Enable

;

Host PCI Master Control Register Bit Flags

M_ARH EQU $00ffff; DSP PCI Transaction Address (High)

M_BL EQU $3f0000; PCI Data Burst Length

M_FC EQU $c00000; Data Transfer Format Control

;

Host PCI Address Register Bit Flags

M_ARL EQU $00ffff; DSP PCI Transaction Address (Low)

M_C EQU $0f0000; PCI Bus Command

M_BE EQU $f00000; PCI Byte Enables

;

DSP Status Register Bit Flags

M_HCP EQU 0 ; Host Command pending

DSP56301 Technical Data, Rev. 10

A-6

Freescale Semiconductor

M_STRQ EQU 1 ; Slave Transmit Data Request

M_SRRQ EQU 2 ; Slave Receive Data Request

M_HF02 EQU $38; Host Flag 0-2 Mask

M_HF0 EQU 3

M_HF1 EQU 4

M_HF2 EQU 5

; Host Flag 0

; Host Flag 1

; Host Flag 2

;

DSP PCI Status Register Bit Flags

M_MWS EQU 0 ; PCI Master Wait States

M_MTRQ EQU 1 ; PCI Master Transmit Data Request

M_MRRQ EQU 2 ; PCI Master Receive Data Request

M_MARQ EQU 4 ; PCI Master Address Request

M_APER EQU 5

M_DPER EQU 6

M_MAB EQU 7

M_TAB EQU 8

M_TDIS EQU 9

M_TRTY EQU 10

M_TO EQU 11

; PCI Address Parity Error

; PCI Data Parity Error

; PCI Master Abort

; PCI Target Abort

; PCI Target Disconnect

; PCI Target Retry

; PCI Time Out Termination

M_RDC EQU $3F0000; Remaining Data Count Mask (RDC5-RDC0)

M_RDC0 EQU 16

M_RDC1 EQU 17

M_RDC2 EQU 18

M_RDC3 EQU 19

M_RDC4 EQU 20

M_RDC5 EQU 21

M_HACT EQU 23

; Remaining Data Count

; Hi32 Active

0

1

2

3

4

5

;------------------------------------------------------------------------

;

EQUATES for Serial Communications Interface (SCI)

;------------------------------------------------------------------------

;

Register Addresses

M_STXH EQU $FFFF97; SCI Transmit Data Register (high)

M_STXM EQU $FFFF96; SCI Transmit Data Register (middle)

M_STXL EQU $FFFF95; SCI Transmit Data Register (low)

M_SRXH EQU $FFFF9A; SCI Receive Data Register (high)

M_SRXM EQU $FFFF99; SCI Receive Data Register (middle)

M_SRXL EQU $FFFF98; SCI Receive Data Register (low)

M_STXA EQU $FFFF94; SCI Transmit Address Register

M_SCR EQU $FFFF9C; SCI Control Register

M_SSR EQU $FFFF93; SCI Status Register

M_SCCR EQU $FFFF9B; SCI Clock Control Register

;

SCI Control Register Bit Flags

M_WDS EQU $7

M_WDS0 EQU 0

M_WDS1 EQU 1

M_WDS2 EQU 2

M_SSFTD EQU 3

M_SBK EQU 4

M_WAKE EQU 5

M_RWU EQU 6

M_WOMS EQU 7

; Word Select Mask (WDS0-WDS3)

; Word Select 0

; Word Select 1

; Word Select 2

; SCI Shift Direction

; Send Break

; Wakeup Mode Select

; Receiver Wakeup Enable

; Wired-OR Mode Select

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

A-7

Power Consumption Benchmark

M_SCRE EQU 8

M_SCTE EQU 9

M_ILIE EQU 10

M_SCRIE EQU 11

M_SCTIE EQU 12

M_TMIE EQU 13

M_TIR EQU 14

M_SCKP EQU 15

M_REIE EQU 16

; SCI Receiver Enable

; SCI Transmitter Enable

; Idle Line Interrupt Enable

; SCI Receive Interrupt Enable

; SCI Transmit Interrupt Enable

; Timer Interrupt Enable

; Timer Interrupt Rate

; SCI Clock Polarity

; SCI Error Interrupt Enable (REIE)

;

SCI Status Register Bit Flags

M_TRNE EQU 0

M_TDRE EQU 1

M_RDRF EQU 2

M_IDLE EQU 3

M_OR EQU 4

M_PE EQU 5

M_FE EQU 6

M_R8 EQU 7

; Transmitter Empty

; Transmit Data Register Empty

; Receive Data Register Full

; Idle Line Flag

; Overrun Error Flag

; Parity Error

; Framing Error Flag

; Received Bit 8 (R8) Address

;

SCI Clock Control Register

M_CD EQU $FFF

M_COD EQU 12

M_SCP EQU 13

M_RCM EQU 14

M_TCM EQU 15

; Clock Divider Mask (CD0-CD11)

; Clock Out Divider

; Clock Prescaler

; Receive Clock Mode Source Bit

; Transmit Clock Source Bit

;------------------------------------------------------------------------

;

EQUATES for Synchronous Serial Interface (SSI)

;------------------------------------------------------------------------

;

Register Addresses Of SSI0

M_TX00 EQU $FFFFBC; SSI0 Transmit Data Register 0

M_TX01 EQU $FFFFBB; SSIO Transmit Data Register 1

M_TX02 EQU $FFFFBA; SSIO Transmit Data Register 2

M_TSR0 EQU $FFFFB9; SSI0 Time Slot Register

M_RX0 EQU $FFFFB8; SSI0 Receive Data Register

M_SSISR0 EQU $FFFFB7; SSI0 Status Register

M_CRB0 EQU $FFFFB6; SSI0 Control Register B

M_CRA0 EQU $FFFFB5; SSI0 Control Register A

M_TSMA0 EQU $FFFFB4; SSI0 Transmit Slot Mask Register A

M_TSMB0 EQU $FFFFB3; SSI0 Transmit Slot Mask Register B

M_RSMA0 EQU $FFFFB2; SSI0 Receive Slot Mask Register A

M_RSMB0 EQU $FFFFB1; SSI0 Receive Slot Mask Register B

;

Register Addresses Of SSI1

M_TX10 EQU $FFFFAC; SSI1 Transmit Data Register 0

M_TX11 EQU $FFFFAB; SSI1 Transmit Data Register 1

M_TX12 EQU $FFFFAA; SSI1 Transmit Data Register 2

M_TSR1 EQU $FFFFA9; SSI1 Time Slot Register

M_RX1 EQU $FFFFA8; SSI1 Receive Data Register

M_SSISR1 EQU $FFFFA7; SSI1 Status Register

M_CRB1 EQU $FFFFA6; SSI1 Control Register B

M_CRA1 EQU $FFFFA5; SSI1 Control Register A

M_TSMA1 EQU $FFFFA4; SSI1 Transmit Slot Mask Register A

DSP56301 Technical Data, Rev. 10

A-8

Freescale Semiconductor

M_TSMB1 EQU $FFFFA3; SSI1 Transmit Slot Mask Register B

M_RSMA1 EQU $FFFFA2; SSI1 Receive Slot Mask Register A

M_RSMB1 EQU $FFFFA1; SSI1 Receive Slot Mask Register B

;

SSI Control Register A Bit Flags

M_PM EQU $FF

M_PSR EQU 11

; Prescale Modulus Select Mask (PM0-PM7)

; Prescaler Range

M_DC EQU $1F000 ; Frame Rate Divider Control Mask (DC0-DC7)

M_ALC EQU 18 ; Alignment Control (ALC)

M_WL EQU $380000; Word Length Control Mask (WL0-WL7)

M_SSC1 EQU 22 ; Select SC1 as TR #0 drive enable (SSC1)

;

SSI Control Register B Bit Flags

M_OF EQU $3

M_OF0 EQU 0

M_OF1 EQU 1

; Serial Output Flag Mask

; Serial Output Flag 0

; Serial Output Flag 1

M_SCD EQU $1C ; Serial Control Direction Mask

M_SCD0 EQU 2 ; Serial Control 0 Direction

M_SCD1 EQU 3

M_SCD2 EQU 4

M_SCKD EQU 5

M_SHFD EQU 6

; Serial Control 1 Direction

; Serial Control 2 Direction

; Clock Source Direction

; Shift Direction

M_FSL EQU $180; Frame Sync Length Mask (FSL0-FSL1)

M_FSL0 EQU 7 ; Frame Sync Length 0

M_FSL1 EQU 8 ; Frame Sync Length 1

M_FSR EQU 9

; Frame Sync Relative Timing

M_FSP EQU 10 ; Frame Sync Polarity

M_CKP EQU 11 ; Clock Polarity

M_SYN EQU 12 ; Sync/Async Control

M_MOD EQU 13 ; SSI Mode Select

M_SSTE EQU $1C000; SSI Transmit enable Mask

M_SSTE2 EQU 14; SSI Transmit #2 Enable

M_SSTE1 EQU 15 ; SSI Transmit #1 Enable

M_SSTE0 EQU 16 ; SSI Transmit #0 Enable

M_SSRE EQU 17 ; SSI Receive Enable

M_SSTIE EQU 18 ; SSI Transmit Interrupt Enable

M_SSRIE EQU 19; SSI Receive Interrupt Enable

M_STLIE EQU 20 ; SSI Transmit Last Slot Interrupt Enable

M_SRLIE EQU 21 ; SSI Receive Last Slot Interrupt Enable

M_STEIE EQU 22; SSI Transmit Error Interrupt Enable

M_SREIE EQU 23 ; SSI Receive Error Interrupt Enable

;

SSI Status Register Bit Flags

M_IF EQU $3

M_IF0 EQU 0

M_IF1 EQU 1

M_TFS EQU 2

M_RFS EQU 3

M_TUE EQU 4

M_ROE EQU 5

M_TDE EQU 6

M_RDF EQU 7

; Serial Input Flag Mask

; Serial Input Flag 0

; Serial Input Flag 1

; Transmit Frame Sync Flag

; Receive Frame Sync Flag

; Transmitter Underrun Error FLag

; Receiver Overrun Error Flag

; Transmit Data Register Empty

; Receive Data Register Full

;

SSI Transmit Slot Mask Register A

M_SSTSA EQU $FFFF ; SSI Transmit Slot Bits Mask A (TS0-TS15)

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

A-9

Power Consumption Benchmark

;

SSI Transmit Slot Mask Register B

M_SSTSB EQU $FFFF ; SSI Transmit Slot Bits Mask B (TS16-TS31)

;

SSI Receive Slot Mask Register A

M_SSRSA EQU $FFFF ; SSI Receive Slot Bits Mask A (RS0-RS15)

SSI Receive Slot Mask Register B

;

M_SSRSB EQU $FFFF ; SSI Receive Slot Bits Mask B (RS16-RS31)

;------------------------------------------------------------------------

;

EQUATES for Exception Processing

;------------------------------------------------------------------------

;

Register Addresses

M_IPRC EQU $FFFFFF; Interrupt Priority Register Core

M_IPRP EQU $FFFFFE; Interrupt Priority Register Peripheral

;

Interrupt Priority Register Core (IPRC)

M_IAL EQU $7

M_IAL0 EQU 0

M_IAL1 EQU 1

M_IAL2 EQU 2

M_IBL EQU $38

M_IBL0 EQU 3

M_IBL1 EQU 4

M_IBL2 EQU 5

M_ICL EQU $1C0

M_ICL0 EQU 6

M_ICL1 EQU 7

M_ICL2 EQU 8

M_IDL EQU $E00

M_IDL0 EQU 9

M_IDL1 EQU 10

M_IDL2 EQU 11

; IRQA Mode Mask

; IRQA Mode Interrupt Priority Level (low)

; IRQA Mode Interrupt Priority Level (high)

; IRQA Mode Trigger Mode

; IRQB Mode Mask

; IRQB Mode Interrupt Priority Level (low)

; IRQB Mode Interrupt Priority Level (high)

; IRQB Mode Trigger Mode

; IRQC Mode Mask

; IRQC Mode Interrupt Priority Level (low)

; IRQC Mode Interrupt Priority Level (high)

; IRQC Mode Trigger Mode

; IRQD Mode Mask

; IRQD Mode Interrupt Priority Level (low)

; IRQD Mode Interrupt Priority Level (high)

; IRQD Mode Trigger Mode

M_D0L EQU $3000 ; DMA0 Interrupt priority Level Mask

M_D0L0 EQU 12

M_D0L1 EQU 13

; DMA0 Interrupt Priority Level (low)

; DMA0 Interrupt Priority Level (high)

M_D1L EQU $C000 ; DMA1 Interrupt Priority Level Mask

M_D1L0 EQU 14

M_D1L1 EQU 15

; DMA1 Interrupt Priority Level (low)

; DMA1 Interrupt Priority Level (high)

M_D2L EQU $30000 ; DMA2 Interrupt priority Level Mask

M_D2L0 EQU 16

M_D2L1 EQU 17

; DMA2 Interrupt Priority Level (low)

; DMA2 Interrupt Priority Level (high)

M_D3L EQU $C0000 ; DMA3 Interrupt Priority Level Mask

M_D3L0 EQU 18

M_D3L1 EQU 19

; DMA3 Interrupt Priority Level (low)

; DMA3 Interrupt Priority Level (high)

M_D4L EQU $300000; DMA4 Interrupt priority Level Mask

M_D4L0 EQU 20

M_D4L1 EQU 21

; DMA4 Interrupt Priority Level (low)

; DMA4 Interrupt Priority Level (high)

DSP56301 Technical Data, Rev. 10

A-10

Freescale Semiconductor

M_D5L EQU $C00000; DMA5 Interrupt priority Level Mask

M_D5L0 EQU 22

M_D5L1 EQU 23

; DMA5 Interrupt Priority Level (low)

; DMA5 Interrupt Priority Level (high)

;

Interrupt Priority Register Peripheral (IPRP)

M_HPL EQU $3

M_HPL0 EQU 0

M_HPL1 EQU 1

M_S0L EQU $C

M_S0L0 EQU 2

M_S0L1 EQU 3

M_S1L EQU $30

M_S1L0 EQU 4

M_S1L1 EQU 5

M_SCL EQU $C0

M_SCL0 EQU 6

M_SCL1 EQU 7

M_T0L EQU $300

M_T0L0 EQU 8

M_T0L1 EQU 9

; Host Interrupt Priority Level Mask

; Host Interrupt Priority Level (low)

; Host Interrupt Priority Level (high)

; SSI0 Interrupt Priority Level Mask

; SSI0 Interrupt Priority Level (low)

; SSI0 Interrupt Priority Level (high)

; SSI1 Interrupt Priority Level Mask

; SSI1 Interrupt Priority Level (low)

; SSI1 Interrupt Priority Level (high)

; SCI Interrupt Priority Level Mask

; SCI Interrupt Priority Level (low)

; SCI Interrupt Priority Level (high)

; TIMER Interrupt Priority Level Mask

; TIMER Interrupt Priority Level (low)

; TIMER Interrupt Priority Level (high)

;------------------------------------------------------------------------

;

EQUATES for TIMER

;------------------------------------------------------------------------

;

Register Addresses Of TIMER0

M_TCSR0 EQU $FFFF8F; TIMER0 Control/Status Register

M_TLR0 EQU $FFFF8E; TIMER0 Load Reg

M_TCPR0 EQU $FFFF8D; TIMER0 Compare Register

M_TCR0 EQU $FFFF8C ; TIMER0 Count Register

;

Register Addresses Of TIMER1

M_TCSR1 EQU $FFFF8B; TIMER1 Control/Status Register

M_TLR1 EQU $FFFF8A; TIMER1 Load Reg

M_TCPR1 EQU $FFFF89; TIMER1 Compare Register

M_TCR1 EQU $FFFF88; TIMER1 Count Register

;

Register Addresses Of TIMER2

M_TCSR2 EQU $FFFF87; TIMER2 Control/Status Register

M_TLR2 EQU $FFFF8; TIMER2 Load Reg

M_TCPR2 EQU $FFFF85; TIMER2 Compare Register

M_TCR2 EQU $FFFF84 ; TIMER2 Count Register

M_TPLR EQU $FFFF83 ; TIMER Prescaler Load Register

M_TPCR EQU $FFFF82 ; TIMER Prescalar Count Register

;

Timer Control/Status Register Bit Flags

M_TE EQU 0

; Timer Enable

M_TOIE EQU 1

M_TCIE EQU 2

; Timer Overflow Interrupt Enable

; Timer Compare Interrupt Enable

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

A-11

Power Consumption Benchmark

M_TC EQU $F0

M_INV EQU 8

M_TRM EQU 9

M_DIR EQU 11

M_DI EQU 12

M_DO EQU 13

; Timer Control Mask (TC0-TC3)

; Inverter Bit

; Timer Restart Mode

; Direction Bit

; Data Input

; Data Output

M_PCE EQU 15 ; Prescaled Clock Enable

M_TOF EQU 20

M_TCF EQU 21

; Timer Overflow Flag

; Timer Compare Flag

;

Timer Prescaler Register Bit Flags

M_PS EQU $600000 ; Prescaler Source Mask

M_PS0 EQU 21

M_PS1 EQU 22

;

Timer Control Bits

M_TC0 EQU 4

M_TC1 EQU 5

M_TC2 EQU 6

M_TC3 EQU 7

; Timer Control 0

; Timer Control 1

; Timer Control 2

; Timer Control 3

;------------------------------------------------------------------------

;

EQUATES for Direct Memory Access (DMA)

;------------------------------------------------------------------------

;

Register Addresses Of DMA

M_DSTR EQU $FFFFF4; DMA Status Register

M_DOR0 EQU $FFFFF3; DMA Offset Register 0

M_DOR1 EQU $FFFFF2; DMA Offset Register 1

M_DOR2 EQU $FFFFF1; DMA Offset Register 2

M_DOR3 EQU $FFFFF0; DMA Offset Register 3

;

Register Addresses Of DMA0

M_DSR0 EQU $FFFFEF; DMA0 Source Address Register

M_DDR0 EQU $FFFFEE; DMA0 Destination Address Register

M_DCO0 EQU $FFFFED; DMA0 Counter

M_DCR0 EQU $FFFFEC; DMA0 Control Register

;

Register Addresses Of DMA1

M_DSR1 EQU $FFFFEB; DMA1 Source Address Register

M_DDR1 EQU $FFFFEA; DMA1 Destination Address Register

M_DCO1 EQU $FFFFE9; DMA1 Counter

M_DCR1 EQU $FFFFE8; DMA1 Control Register

;

Register Addresses Of DMA2

M_DSR2 EQU $FFFFE7; DMA2 Source Address Register

M_DDR2 EQU $FFFFE6; DMA2 Destination Address Register

M_DCO2 EQU $FFFFE5; DMA2 Counter

M_DCR2 EQU $FFFFE4; DMA2 Control Register

;

Register Addresses Of DMA4

DSP56301 Technical Data, Rev. 10

A-12

Freescale Semiconductor

M_DSR3 EQU $FFFFE3; DMA3 Source Address Register

M_DDR3 EQU $FFFFE2; DMA3 Destination Address Register

M_DCO3 EQU $FFFFE1; DMA3 Counter

M_DCR3 EQU $FFFFE0; DMA3 Control Register

;

Register Addresses Of DMA4

M_DSR4 EQU $FFFFDF; DMA4 Source Address Register

M_DDR4 EQU $FFFFDE; DMA4 Destination Address Register

M_DCO4 EQU $FFFFDD; DMA4 Counter

M_DCR4 EQU $FFFFDC; DMA4 Control Register

;

Register Addresses Of DMA5

M_DSR5 EQU $FFFFDB; DMA5 Source Address Register

M_DDR5 EQU $FFFFDA; DMA5 Destination Address Register

M_DCO5 EQU $FFFFD9; DMA5 Counter

M_DCR5 EQU $FFFFD8; DMA5 Control Register

;

DMA Control Register

M_DSS EQU $3 ; DMA Source Space Mask (DSS0-Dss1)

M_DSS0 EQU 0 ; DMA Source Memory space 0

M_DSS1 EQU 1 ; DMA Source Memory space 1

M_DDS EQU $C ; DMA Destination Space Mask (DDS-DDS1)

M_DDS0 EQU 2 ; DMA Destination Memory Space 0

M_DDS1 EQU 3 ; DMA Destination Memory Space 1

M_DAM EQU $3F0; DMA Address Mode Mask (DAM5-DAM0)

M_DAM0 EQU 4 ; DMA Address Mode 0

M_DAM1 EQU 5 ; DMA Address Mode 1

M_DAM2 EQU 6 ; DMA Address Mode 2

M_DAM3 EQU 7 ; DMA Address Mode 3

M_DAM4 EQU 8 ; DMA Address Mode 4

M_DAM5 EQU 9 ; DMA Address Mode 5

M_D3D EQU 10 ; DMA Three Dimensional Mode

M_DRS EQU $F800; DMA Request Source Mask (DRS0-DRS4)

M_DCON EQU 16 ; DMA Continuous Mode

M_DPR EQU $60000; DMA Channel Priority

M_DPR0 EQU 17 ; DMA Channel Priority Level (low)

M_DPR1 EQU 18 ; DMA Channel Priority Level (high)

M_DTM EQU $380000; DMA Transfer Mode Mask (DTM2-DTM0)

M_DTM0 EQU 19 ; DMA Transfer Mode 0

M_DTM1 EQU 20 ; DMA Transfer Mode 1

M_DTM2 EQU 21 ; DMA Transfer Mode 2

M_DIE EQU 22 ; DMA Interrupt Enable bit

M_DE EQU 23

DMA Status Register

M_DTD EQU $3F ; Channel Transfer Done Status MASK (DTD0-DTD5)

; DMA Channel Enable bit

;

M_DTD0 EQU 0

M_DTD1 EQU 1

M_DTD2 EQU 2

M_DTD3 EQU 3

M_DTD4 EQU 4

M_DTD5 EQU 5

; DMA Channel Transfer Done Status 0

; DMA Channel Transfer Done Status 1

; DMA Channel Transfer Done Status 2

; DMA Channel Transfer Done Status 3

; DMA Channel Transfer Done Status 4

; DMA Channel Transfer Done Status 5

M_DACT EQU 8 ; DMA Active State

M_DCH EQU $E00; DMA Active Channel Mask (DCH0-DCH2)

M_DCH0 EQU 9 ; DMA Active Channel 0

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

A-13

Power Consumption Benchmark

M_DCH1 EQU 10 ; DMA Active Channel 1

M_DCH2 EQU 11 ; DMA Active Channel 2

;------------------------------------------------------------------------

;

EQUATES for Phase Lock Loop (PLL)

;------------------------------------------------------------------------

Register Addresses Of PLL

M_PCTL EQU $FFFFFD; PLL Control Register

PLL Control Register

;

M_MF EQU $FFF

; Multiplication Factor Bits Mask (MF0-MF11)

M_DF EQU $7000 ; Division Factor Bits Mask (DF0-DF2)

M_XTLR EQU 15

M_XTLD EQU 16

M_PSTP EQU 17

M_PEN EQU 18

M_PCOD EQU 19

; XTAL Range select bit

; XTAL Disable Bit

; STOP Processing State Bit

; PLL Enable Bit

; PLL Clock Output Disable Bit

M_PD EQU $F00000; PreDivider Factor Bits Mask (PD0-PD3)

;------------------------------------------------------------------------

;

EQUATES for BIU

;------------------------------------------------------------------------

;

Register Addresses Of BIU

M_BCR EQU $FFFFFB; Bus Control Register

M_DCR EQU $FFFFFA; DRAM Control Register

M_AAR0 EQU $FFFFF9; Address Attribute Register 0

M_AAR1 EQU $FFFFF8; Address Attribute Register 1

M_AAR2 EQU $FFFFF7; Address Attribute Register 2

M_AAR3 EQU $FFFFF6; Address Attribute Register 3

M_IDR EQU $FFFFF5; ID Register

;

Bus Control Register

M_BA0W EQU $1F

M_BA1W EQU $3E0

; Area 0 Wait Control Mask (BA0W0-BA0W4)

; Area 1 Wait Control Mask (BA1W0-BA14)

M_BA2W EQU $1C00 ; Area 2 Wait Control Mask (BA2W0-BA2W2)

M_BA3W EQU $E000 ; Area 3 Wait Control Mask (BA3W0-BA3W3)

M_BDFW EQU $1F0000; Default Area Wait Control Mask (BDFW0-BDFW4)

M_BBS EQU 21

M_BLH EQU 22

M_BRH EQU 23

; Bus State

; Bus Lock Hold

; Bus Request Hold

;

DRAM Control Register

M_BCW EQU $3

M_BRW EQU $C

M_BPS EQU $300

M_BPLE EQU 11

; In Page Wait States Bits Mask (BCW0-BCW1)

; Out Of Page Wait States Bits Mask (BRW0-BRW1)

; DRAM Page Size Bits Mask (BPS0-BPS1)

; Page Logic Enable

DSP56301 Technical Data, Rev. 10

A-14

Freescale Semiconductor

M_BME EQU 12

M_BRE EQU 13

M_BSTR EQU 14

; Mastership Enable

; Refresh Enable

; Software Triggered Refresh

M_BRF EQU $7F8000; Refresh Rate Bits Mask (BRF0-BRF7)

M_BRP EQU 23 ; Refresh prescaler

;

Address Attribute Registers

M_BAT EQU $3

M_BAAP EQU 2

M_BPEN EQU 3

M_BXEN EQU 4

M_BYEN EQU 5

M_BAM EQU 6

; External Access Type and Pin Definition Bits Mask (BAT0-BAT1)

; Address Attribute Pin Polarity

; Program Space Enable

; X Data Space Enable

; Y Data Space Enable

; Address Muxing

M_BPAC EQU 7 ; Packing Enable

M_BNC EQU $F00

; Number of Address Bits to Compare Mask (BNC0-BNC3)

M_BAC EQU $FFF000; Address to Compare Bits Mask (BAC0-BAC11)

;

control and status bits in SR

M_CP EQU $c00000 ; mask for CORE-DMA priority bits in SR

M_CA EQU 0

M_V EQU 1

; Carry

; Overflow

M_Z EQU 2

; Zero

M_N EQU 3

; Negative

M_U EQU 4

; Unnormalized

M_E EQU 5

; Extension

M_L EQU 6

; Limit

M_S EQU 7

; Scaling Bit

M_I0 EQU 8

M_I1 EQU 9

M_S0 EQU 10

M_S1 EQU 11

M_SC EQU 13

M_DM EQU 14

M_LF EQU 15

M_FV EQU 16

M_SA EQU 17

M_CE EQU 19

M_SM EQU 20

M_RM EQU 21

M_CP0 EQU22

M_CP1 EQU 23

; Interupt Mask Bit 0

; Interupt Mask Bit 1

; Scaling Mode Bit 0

; Scaling Mode Bit 1

; Sixteen_Bit Compatibility

; Double Precision Multiply

; DO-Loop Flag

; DO-Forever Flag

; Sixteen-Bit Arithmetic

; Instruction Cache Enable

; Arithmetic Saturation

; Rounding Mode

; bit 0 of priority bits in SR

; bit 1 of priority bits in SR

;

control and status bits in OMR

M_CDP EQU$300 ; mask for CORE-DMA priority bits in OMR

M_MA EQU 0

; Operating Mode A

M_MB EQU 1

; Operating Mode B

M_MC EQU 2

; Operating Mode C

M_MD EQU 3

; Operating Mode D

M_EBD EQU 4

M_SD EQU 6

; External Bus Disable bit in OMR

; Stop Delay

M_CDP0 EQU 8

M_CDP1 EQU 9

M_BEN EQU 10

M_TAS EQU 11

M_BRT EQU 12

M_XYS EQU 16

M_EUN EQU 17

M_EOV EQU 18

; bit 0 of priority bits in OMR

; bit 1 of priority bits in OMR

; Burst Enable

; TA Synchronize Select

; Bus Release Timing

; Stack Extension space select bit in OMR.

; Extensed stack UNderflow flag in OMR.

; Extended stack OVerflow flag in OMR.

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

A-15

Power Consumption Benchmark

M_WRP EQU 19

M_SEN EQU 20

; Extended WRaP flag in OMR.

; Stack Extension Enable bit in OMR.

;*************************************************************************

;

EQUATES for DSP56301 interrupts

Reference: DSP56301 Specifications Revision 3.00

Last update: November 15 1993 (Debug request & HI32 interrupts)

December 19 1993 (cosmetic - page and opt directives)

August 16 1994 (change interrupt addresses to be

relative to I_VEC)

;

;*************************************************************************

page

opt

132,55,0,0,0

mex

intequ ident

1,0

if

@DEF(I_VEC)

;leave user definition as is.

else

I_VEC equ

endif

$0

;------------------------------------------------------------------------

; Non-Maskable interrupts

;------------------------------------------------------------------------

I_RESET EQU I_VEC+$00

I_STACK EQU I_VEC+$02

; Hardware RESET

; Stack Error

I_ILL

I_DBG

I_TRAP

I_NMI

EQU I_VEC+$04

EQU I_VEC+$06

EQU I_VEC+$08

EQU I_VEC+$0A

; Illegal Instruction

; Debug Request

; Trap

; Non Maskable Interrupt

;------------------------------------------------------------------------

; Interrupt Request Pins

;------------------------------------------------------------------------

I_IRQA

I_IRQB

I_IRQC

I_IRQD

EQU I_VEC+$10

EQU I_VEC+$12

EQU I_VEC+$14

EQU I_VEC+$16

; IRQA

; IRQB

; IRQC

; IRQD

;------------------------------------------------------------------------

; DMA Interrupts

;------------------------------------------------------------------------

I_DMA0

I_DMA1

I_DMA2

I_DMA3

I_DMA4

I_DMA5

EQU I_VEC+$18

EQU I_VEC+$1A

EQU I_VEC+$1C

EQU I_VEC+$1E

EQU I_VEC+$20

EQU I_VEC+$22

; DMA Channel 0

; DMA Channel 1

; DMA Channel 2

; DMA Channel 3

; DMA Channel 4

; DMA Channel 5

;------------------------------------------------------------------------

; Timer Interrupts

;------------------------------------------------------------------------

I_TIM0C EQU I_VEC+$24

I_TIM0OF EQU I_VEC+$26

; TIMER 0 compare

; TIMER 0 overflow

DSP56301 Technical Data, Rev. 10

A-16

Freescale Semiconductor

I_TIM1C EQU I_VEC+$28

I_TIM1OF EQU I_VEC+$2A

I_TIM2C EQU I_VEC+$2C

I_TIM2OF EQU I_VEC+$2E

; TIMER 1 compare

; TIMER 1 overflow

; TIMER 2 compare

; TIMER 2 overflow

;------------------------------------------------------------------------

; ESSI Interrupts

;------------------------------------------------------------------------

I_SI0RD EQU I_VEC+$30

I_SI0RDE EQU I_VEC+$32

I_SI0RLS EQU I_VEC+$34

I_SI0TD EQU I_VEC+$36

I_SI0TDE EQU I_VEC+$38

I_SI0TLS EQU I_VEC+$3A

I_SI1RD EQU I_VEC+$40

I_SI1RDE EQU I_VEC+$42

I_SI1RLS EQU I_VEC+$44

I_SI1TD EQU I_VEC+$46

I_SI1TDE EQU I_VEC+$48

I_SI1TLS EQU I_VEC+$4A

; ESSI0 Receive Data

; ESSI0 Receive Data With Exception Status

; ESSI0 Receive last slot

; ESSI0 Transmit data

; ESSI0 Transmit Data With Exception Status

; ESSI0 Transmit last slot

; ESSI1 Receive Data

; ESSI1 Receive Data With Exception Status

; ESSI1 Receive last slot

; ESSI1 Transmit data

; ESSI1 Transmit Data With Exception Status

; ESSI1 Transmit last slot

;------------------------------------------------------------------------

; SCI Interrupts

;------------------------------------------------------------------------

I_SCIRD EQU I_VEC+$50

I_SCIRDE EQU I_VEC+$52

I_SCITD EQU I_VEC+$54

I_SCIIL EQU I_VEC+$56

I_SCITM EQU I_VEC+$58

; SCI Receive Data

; SCI Receive Data With Exception Status

; SCI Transmit Data

; SCI Idle Line

; SCI Timer

;------------------------------------------------------------------------

; HOST Interrupts

;------------------------------------------------------------------------

I_HPTT

I_HPTA

I_HPPE

I_HPTC

I_HPMR

I_HSR

I_HPMT

I_HST

I_HPMA

EQU I_VEC+$60

EQU I_VEC+$62

EQU I_VEC+$64

EQU I_VEC+$66

EQU I_VEC+$68

EQU I_VEC+$6A

EQU I_VEC+$6C

EQU I_VEC+$6E

EQU I_VEC+$70

; Host PCI Transaction Termination

; Host PCI Transaction Abort

; Host PCI Parity Error

; Host PCI Transfer Complete

; Host PCI Master Receive

; Host Slave Receive

; Host PCI Master Transmit

; Host Slave Transmit

; Host PCI Master Address

; Host Command/Host NMI (Default)

I_HCNMI EQU I_VEC+$72

;------------------------------------------------------------------------

; INTERRUPT ENDING ADDRESS

;------------------------------------------------------------------------

I_INTEND EQU I_VEC+$FF

; last address of interrupt vector space

DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

A-17

Ordering Information

Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.

Core

Frequency

(MHz)

Supply

Voltage

Count

Part

Package Type

Solder Spheres

Order Number

DSP56301

3.3 V

Thin Quad Flat Pack (TQFP)

208

252

80

100

80

Lead-free

Lead-bearing

Lead-free

DSP56301AG80

DSP56301PW80

DSP56301AG100

DSP56301PW100

DSP56301VL80

DSP56301VF80

DSP56301VL100

DSP56301VF100

Lead-bearing

Lead-free

Molded Array Process-Ball Grid

Array (MAP-BGA)

Lead-bearing

Lead-free

100

Lead-bearing

Information in this document is provided solely to enable system and software implementers to

use Freescale Semiconductor products. There are no express or implied copyright licenses

granted hereunder to design or fabricate any integrated circuits or integrated circuits based on

the information in this document.

How to Reach Us:

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Document Order No.: DSP56301

Rev. 10

7/2006


型号：	DSP56301PW80
厂家：	Freescale
描述：	24-Bit Digital Signal Processor 24位数字信号处理器外围集成电路数字信号处理器时钟
文件：	总124页 (文件大小：2296K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DSP56301PW80 [FREESCALE]

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