181-FREQ2-BM [FOX]

HCMOS/TTL Output Clock Oscillator, 50MHz Min, 160MHz Max, DIP-14/4;


型号：	181-FREQ2-BM
厂家：	FOX ELECTRONICS
描述：	HCMOS/TTL Output Clock Oscillator, 50MHz Min, 160MHz Max, DIP-14/4 机械振荡器
文件：	总1页 (文件大小：172K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

5.0V HCMOS TRI-STATE ENABLE/DISABLE OSCILLATORS

MODEL: F5C-2E

FEATURES

OPTIONS

• 5.0V Operationg

• HCMOS/TTL Output

• Tri-State Enable/Disable

• 14-Pin DIP

• 8-Pin DIP Available (H5C-2E)

Discontinued

Learn more about:

Part Marking Identiﬁcation

Mechanical Speciﬁcation

Internet required

• PART NUMBER SELECTION^{Learn More - Internet Required}

Frequency

Operating

Frequency

Model

Number

Part Number

Stability¹Temperature (ºC) Range (MHz)

147-Frequency-xxxxx F5C-2E

326-Frequency-xxxxx F5C-2ER ±100PPM

180-Frequency-xxxxx F6C-2E

±50PPM

181-Frequency-xxxxx F6C-2ER ±50PPM

199-Frequency-xxxxx F7C-2E

±25PPM

330-Frequency-xxxxx F7C-2ER ±25PPM

513-Frequency-xxxxx F8C-2E

±20PPM

±100PPM

0 ~ +70

-40 ~ +85

0 ~ +70

-40 ~ +85

0 ~ +70

1.000 ~ 160.000

1.000 ~ 125.000

-40 ~ +85

0 ~ +70

• ELECTRICAL CHARACTERISTICS

PARAMETERS

Frequency Range (Fo)

Storage Temperature Range (Tstg)

MAX (unless otherwise noted)

1.000 ~ 160.000 MHz

-55ºC ~ +125ºC

Supply Voltage

Input Current

(Vdd)

(I^dd)

5.0V ± 10%

1.000 ~ 40.000 MHz

40mA

60mA

100mA

40.000+ ~ 125.000 MHz

125.000+ ~ 160.000 MHz

Output Symmetry (50% Vdd)

1.000 ~ 50.000 MHz

50.000+ ~ 160.000 MHz

Rise Time (10% ~ 90% Vdd) (Tr)

1.000 ~ 125.000 MHz

125.000+ ~ 160.000 MHz

Fall Time (90% ~ 10% Vdd) (Tf)

1.000 ~ 125.000 MHz

45% ~ 55%

40% ~ 60%

10 nS

6 nS

10 nS

6 nS

125.000+ ~ 160.000 MHz

Output Voltage

(Vol)

(Voh)

(Iol)

(Ioh)

10% Vdd

90% Vdd Min

16mA Min

-16mA Min

Output Current

Output Load

TTL

HCMOS

All dimensions are in millimeters.

10TTL

50pF

Start-up Time

(Ts)

10mS

100nS

Output Enable/Disable Time ²

¹Inclusive of 25ºC tolerance, operating temperature range, input voltage change, load change, aging,

shock, and vibration.

²An internal pullup resistor from pin 1 to VDD allows active output if pin 1 is left open.

All speciﬁcations subject to change without notice. Rev. 6/1/04

• ENABLE / DISABLE FUNCTION

INH (Pin 1)

OPEN ²

OUTPUT (Pin 8)

ACTIVE

'1' Level Vih ≥ 2.2 V

'0' Level Vil ≤ 0.8 V

ACTIVE

High Z

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