120-1.544MHZ-BE0 [FOX]

HCMOS Output Clock Oscillator, 1.544MHz Nom, LEAD FREE, SMD, 4 PIN;


型号：	120-1.544MHZ-BE0
厂家：	FOX ELECTRONICS
描述：	HCMOS Output Clock Oscillator, 1.544MHz Nom, LEAD FREE, SMD, 4 PIN
文件：	总1页 (文件大小：114K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

5.0V HCMOS SMD OSCILLATOR WITH STANDBY

MODEL: F4101 Series

FEATURES

• 5.0V Operation

• HCMOS Output

• Standby Function

• Tape and Reel (2,000 pcs. STD)

Learn more about:

Part Marking Identification

Tape and Reel Specification

• PART NUMBER SELECTION^{Learn More - Internet Required}

Frequency

Model Frequency Operating

Number Stability¹Temperature

F4101

Mechanical Specification

Part Number

Range (MHz)

1.544 ~ 170.000

1.544 ~ 162.000

1.544 ~ 156.250

1.544 ~ 162.000

Internet required

±100PPM

±50PPM

±25PPM

±20PPM

-10 ~ +70ºC

-40 ~ +85ºC

-10 ~ +70ºC

-40 ~ +85ºC

-10 ~ +70º)

-40 ~ +85ºC

-10 ~ +70ºC

118-Frequency-xxxxx

119-Frequency-xxxxx

120-Frequency-xxxxx

121-Frequency-xxxxx

122-Frequency-xxxxx

123-Frequency-xxxxx

446-Frequency-xxxxx

F4101R

F4102

F4102R

F4103

F4103R*

F4104*

• ELECTRICAL CHARACTERISTICS

PARAMETERS

Frequency Range (FO)

Storage Temperature Range (TSTG)

MAX (unless otherwise noted)

1.544 ~ 170.000 MHz

-55ºC ~ +125ºC

Supply Voltage

Input Current

(VDD)

(I^DD)

5.0V ± 10%

1.544 ~ 32.000 MHz

32.000+ ~ 67.000 MHz

18mA

50mA

67.000+ ~ 125.000 MHz

125.000+ ~ 170.000 MHz

Output Symmetry (50% V^DD)

Rise Time (10% ~ 90% VDD) (TR)

1.544 ~ 79.999999 MHz

80.000 ~ 170.000 MHz

80mA

90mA

40% ~ 60%

5nS

4nS

Fall Time (90% ~ 10% V^DD) (TF)

1.544 ~ 79.999999 MHz

80.000 ~ 170.000 MHz

5nS

4nS

Output Voltage

(VOL)

(VOH)

(IOL)

(IOH)

10% V^DD

90% VDD Min

2mA Min

-2mA Min

15pF

Output Current

Output Load

(HCMOS)

Standby Current

Start-up Time

Output Disable Time

Output Enable Time ²

10μA

10mS

150nS

10mS

(TS)

¹Inclusive of 25ºC tolerance, operating temperature range, input voltage change, load change, aging,

shock, and vibration. *Excludes shock/vibration.

²An internal pullup resistor from pin 1 to pin 4 allows active output if pin 1 is left open.

Note: A 0.01μF bypass capacitor should be placed between VDD (Pin 4) and GND (Pin 2) to

minimize power supply line noise.

All dimensions are in millimeters.

All specifications subject to change without notice. Rev. 5/26/04

• ENABLE / DISABLE FUNCTION

OUTPUT (Pin 3)

ACTIVE

INH (Pin 1)

OPEN

ACTIVE

High Z

'1' Level VIH ≥ 70% VDD

'0' Level VIL ≤ 30% VDD

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