FP6329ASOGTR [FITIPOWER]

Synchronous Buck PWM DC-DC Controller;


型号：	FP6329ASOGTR
厂家：	Fitipower
描述：	Synchronous Buck PWM DC-DC Controller
文件：	总16页 (文件大小：699K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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FP6329/A

Synchronous Buck PWM

DC-DC Controller

Description

Features

The FP6329/A is designed to drive two N-channel

MOSFETs in a synchronous rectified buck topology.

It provides the output adjustment, internal soft-start,

frequency compensation networks, monitoring and

protection functions into a single package.

● Operates from +5V or +12V

● High Output Current

● Drives Two Low Cost N-Channel MOSFETs

● Fast Transient Response

● Simple Single-Loop Control Design

( Voltage-Mode PWM Control)

● Internal Soft-Start

● Over-Current Protection

● Over-Voltage Protection

● Under-Voltage Protection

● SOP-8 Package

The FP6329/A operating at fixed 300/600kHz

frequency provide simple, single feedback loop,

voltage mode control with fast transient response.

The resulting PWM duty ratio ranges from 0-100%.

The FP6329/A features over current protection.

The output current is monitored by sensing the

voltage drop across the R_DS-ONof the low side

MOSFET which eliminates the need for a current

sensing resistor.

● RoHS Compliant

Applications

● Motherboard

● Graphic Card

This device is available in SOP-8 package.

● Telecomm Equipments

● High Power DC-DC Regulators

● Switching Power Supply (SPS)

Pin Assignment

Ordering Information

FP6329□□□□

SO Package (SOP-8)

TR: Tape / Reel

PHASE

COMP/SD

BOOT

UGATE

G: Green

GND

Package Type

SO: SOP-8

VCC

LGATE/OCSET

SP: SOP-8(Exposed Pad)

Switching Frequency

Blank: 300 kHz

A: 600 kHz

SP Package (SOP-8<Exposed Pad>)

PHASE

COMP/SD

BOOT

UGATE

GND

VCC

LGATE/OCSET

Figure 1. Pin Assignment of FP6329/A

FP6329/A/B-1.0-APR-2010

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FP6329/A

Typical Application Circuit

V_IN

Vcc

+5V/ +12V

+3.3V/ +5V/ +12V

1µF

C_IN

0.1µF

BOOT

UGATE

PHASE

VCC

V_OUT

FP6329/A

1µF

COMP/SD

C_OUT

GND

LGATE/OCSET

ROCSET

Figure 2. Typical Application Circuit of FP6329/A

Functional Pin Description

Pin Name

Pin Function

This pin provides bias voltage to the high side MOSFET Driver. A bootstrap circuit may be to create a BOOT

voltage suitable to drive a standard N-Channel MOSFET.

BOOT

Connect UGATE to the high side MOSFET gate. This pin is monitored by the adaptive shoot-through protection

circuitry to determine when the high side MOSFET has turned off.

UGATE

GND

Ground.

Connect LGATE to the low side MOSFET gate. This pin is monitored by the adaptive shoot-through protection

circuitry to determine when the high side MOSFET has turned off. Connect a resistor (R_OCSET) from this pin to

GND to determine the over-current threshold of the converter.

LGATE/OCSET

VCC

Power Pin.

Feedback Pin. The typical reference voltage is 0.6V.

PWM error amplifier output and Shutdown Control pin. It can be used to compensate the voltage control

feedback loop of the converter

COMP/SD

PHASE

Connect the PHASE pin to the high side MOSFET source.

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FP6329/A

Absolute Maximum Ratings

● VCC to GND --------------------------------------------------------------------------------------- -0.3V to +16V

● BOOT, V_BOOT- V_PHASE---------------------------------------------------------------------------- -0.3V to +16V

● PHASE ---------------------------------------------------------------------------------------------- -5V to +16V

● UGATE ---------------------------------------------------------------------------------------------- V_PHASE- 0.3V to V_BOOT+0.3V

● LGATE ---------------------------------------------------------------------------------------------- -0.3V to VCC+0.3V

●FB,COMP to GND -------------------------------------------------------------------------------- -0.3V to +6V

● Continuous Power Dissipation @ T_A=+25°C (P_D) ----------------------------------------

SOP-8 ---------------------------------------------------------------------------------- +0.63W

SOP-8 (Expose Pad) --------------------------------------------------------------- +1.25W

● Package Thermal Resistance, SOP-8 (θ_JA) ------------------------------------------------

SOP-8 ---------------------------------------------------------------------------------- +160°C/W

SOP-8 (Expose Pad) --------------------------------------------------------------- +80°C/W

● Junction Temperature --------------------------------------------------------------------------- +150°C

● Storage Temperature Range ------------------------------------------------------------------ -65°C to +150°C

● Lead Temperature (Soldering, 10sec.) ------------------------------------------------------ +260°C

Note 1：Stresses beyond those listed under “Absolute Maximum Ratings" may cause permanent damage to the device.

Recommended Operating Conditions

● Supply Voltage, V_CC------------------------------------------------------------------------------ 5V ±5%, 12V ±10%

● Operating Temperature Range ---------------------------------------------------------------- -40°C to +85°C

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FP6329/A

Block Diagram

VCC

20µA

0.4V

Enable

COMP/SD

Power on

Reset

Bias

Regulators

50%V_REF

Soft-Start

Fault Logic

Sample

AND

Hold

125%V_REF

BOOT

LGATE/OCSET

Soft-Start

Inhibit

UGATE

REFERENCE

20kΩ

0.6V_REF

COMP

Gate

Control

Logic

PHASE

PWM

VCC

LGATE/OCSET

Oscillator

GND

Figure 3. Block Diagram of FP6329/A

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FP6329/A

Electrical Characteristics

(V_CC=12V, T_A=25°C, unless otherwise specified)

Parameter

Symbol

V_UVLO

I_CC

Conditions

Min

Typ

Max

Unit

INPUT

V_CCUnder Voltage Lockout

UVLO Hysteresis

VCC rising

3.9

4.1

0.45

4.3

VCC falling

Quiescent Current

ERROR AMPLIFIER

Feedback Voltage

FB Input Bias Current

Open Loop DC gain (Note2)

Open Loop Bandwidth (Note2)

Slew Rate (Note2)

OSCILLATOR

UGATE and LGATE open

V_FB

I_FB

0.591

0.6

0.1

0.609

V_FB=1V

µA

A_O

MHz

V/μs

FP6329

270

540

300

600

1.5

330

660

Frequency

F_OSC

kHz

FP6329A

△V_OSC

Ramp Amplitude (Note2)

Vp-p

GATE DRIVERS

Upper Gate Source Current

(Note2)

V_BOOT=12V,

V_UGATE-V_PHASE=2V

I_UGATE

R_UGATE

I_LGATE

2.6

1.6

Upper Gate Sink Impedance

V_BOOT=12V, I_UGATE=0.1A

V_VCC=12V, V_LGATE=2V

V_VCC=12V, I_LGATE=0.1A

Lower Gate Source Current

(Note2)

4.9

Lower Gate Sink Impedance

Dead Time (Note2)

R_LGATE

T_DT

1.25

100

PROTECTION

FB Under-Voltage Trip

FB Over-Voltage Trip

OCSET Current Source

Disable Threshold

FB falling

125

21.5

0.4

µA

I_OCSET

19.5

0.3

23.5

0.5

V_DISABLE

COMP/SD falling

Note 2：The specification is guaranteed by design, not production tested.

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FP6329/A

Typical Performance Curves

350

340

330

320

310

300

290

280

270

260

250

0.70

0.65

0.60

0.55

0.50

-40

-20

-40

-20

Junction Temperature (^OC)

Figure 4. Reference Voltage vs. Junction Temperature

Figure 5. Frequency vs. Junction Temperature

V_LGATE

V_OUT

-40

-20

Junction Temperature (^OC)

Figure 6. OCSET Current Source vs. Junction Temperature

Figure 7. Under Voltage Protection

V_CC

V_CC=12V, V_IN=12V

V_OUT

V_PHASE

V_OUT

V_PHASE

I_L

Figure 8. Power On at 0A Loading

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Figure 9. Power OFF at 0A Loading

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FP6329/A

Typical Performance Curves (Continued)

V_CC=12V, V_IN=12V

V_CC

V_CC=12V, V_IN=12V

V_OUT

I_L

V_OUT

I_L

V_PHASE

Figure 10. Power On at 15A Loading

Figure 11. Power OFF at 15A Loading

V_CC=12V, V_IN=12V

V_UGATE

V_PHASE

V_LGATE

Figure 12. Switching waveform (UGATE rising) I_OUT=0A

Figure 13. Switching waveform (UGATE rising) I_OUT=15A

V_CC=12V, V_IN=12V

V_UGATE

V_CC=12V, V_IN=12V

V_UGATE

V_PHASE

V_LGATE

Figure 14. Switching waveform (UGATE Falling) I_OUT=0A

Figure 15. Switching waveform (UGATE Falling) I_OUT=15A

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Typical Performance Curves (Continued)

V_CC=12V, V_IN=12V

V_OUT

V_CC=12V, V_IN=12V

V_OUT

I_L

Figure 16. Output Ripple at 0A

Figure 17. Output Ripple at 15A

V_CC=12V, V_IN=12V

V_OUT

V_CC=12V, V_IN=12V

V_OUT

I_L

Figure 18. Transient test: Slew rate:2.5A/µs,(1A to 10A)

Figure 19. Transient test: Slew rate:2.5A/µs, (1A to 15A)

V_CC=12V, V_IN=12V

V_OUT

V_CC=12V, V_IN=12V

V_OUT

I_L

Figure 20. Output short after power on

Figure 21. OCP using DC loading

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Typical Performance Curves (Continued)

V_CC=12V, V_IN=12V

V_CC

I_L

V_OUT

V_PHASE

I_L

V_PHASE

Figure 22. Power On with Enable at 0A Loading

Figure 23. Power On with Enable at 15A Loading

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FP6329/A

Functional Description

The Power-On Reset (POR) function continually

monitors the input supply voltage and the enable

function. The POR monitors the bias voltage at the

VCC pin. When VCC power is ready, the FP6329/A

starts to ramp up the output voltage up to the target

voltage.

To avoid the normal operation trigger the OCP

function at load transient and junction temperature.

All parameters variation must be concerned.

(1) The maximum R_DS-ONat the highest junction

temperature.

(2) The minimum OCSET current.

Soft-Start

Shutdown

The FP6329/A features soft-start to limit inrush

current and control the output voltage rise at start-up.

The soft-start is accomplished by ramping the

internal reference input from 0V to 0.6V. The

soft-start interval is 3.5ms typical.

Connecting a small transistor to COMP/SD pin, and

pulling the voltage of COMP/SD pin less than 0.4V

can shutdown the FP6329/A. At this condition, the

FP6329/A is shutdown and high side and low side

MOSFETs are turned off.

Over-Current Protection

Under-Voltage Protection

The over-current function protects the converter a

shorted output by using the low side MOSFET

on-resistance R_DS-ONto monitor the current. This

method enhances the converter’s efficiency and

reduces cost by eliminating a current sensing

resistor.

The under-voltage function monitors the FB voltage

to protection the converter against the output

short-circuit condition.

threshold is 0.5xV_REF

The under- voltage

When UVP happens, the

high side and low side gate will turn off and the

output is latched off until the VCC bias supply is

re-started.

The over-current function cycles the soft-start

function in a hiccup mode to provide fault protection.

After four times are counted, the high side and low

side gate will turn off and the output is latched off

until the VCC bias supply is re-started. A resistor

(R_OCSET), connected from the gate of low side

MOSFET to the source of low side MOSFET to set

the over-current trigger level. An internal 21.5μA

(typical) current source develops the voltage across

Over-Voltage Protection

The over-voltage function monitors the FB voltage

to protection the converter against the output from

over-voltage. When the feedback voltage rises to

1.25xV_REF, the FP6329/A turns on the low side

MOSFET until the feedback voltage below the OVP

the R_OCSET

The over-current setting equation is

threshold.

During the soft start period, the

shown as below:

over-voltage protection function is disabled.

221.5µAR_OCSET

I_OCSET



R_DSON

*Note: If R_OCSET> 25kΩ, the over-current function will

be disabled.

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FP6329/A

Application Information

Introduction

The ESR can be calculated from the following

formula.

The FP6329/A integrated circuit is a synchronous

PWM controller; it operates over a wide input voltage

range. Being low cost, it is a very popular choice of

PWM controller. This section will describe the

FP6329/A application suggestion. The operation

and the design of this application will also be

discussed in detail.









V_RIPPLE

ΔIL

ESR 





An aluminum electrolytic capacitor's ESR value is

related to the capacitance and its voltage rating. In

most case, higher voltage electrolytic capacitors

have lower ESR values.

Most of the time,

Design Procedures

capacitors with much higher voltage ratings may be

needed to provide the low ESR values required for

low output ripple voltage.

This section will describe the steps to design

synchronous buck system, and explains how to

construct basic power conversion circuits including

the design of the control chip functions and the basic

loop.

The capacitor voltage rating should be at least 1.5

times greater than the output voltage, and often

much higher voltage ratings are needed to satisfy

the low ESR requirements needed for low output

ripple voltage.

(1) Synchronous Buck Converter

Since this is a buck output system, the first quantity

to be determined is the duty cycle value. The

formula calculated the PWM duty ratio; apply to the

system which we propose to design:

(4) Input Capacitor Selection

The RMS current rating of the input capacitor can

be calculated as below:

V_O+V_{DS(sat), Lowside N}

T_ON

Duty ratio D =

T_S

V - V_DS(sat),

+V_DS(sat),Lowside N

Highside N

 I

 D(1 D)

IN((rms)

OUT

(2) Inductor Selection

To find the inductor value it is necessary to consider

the inductor ripple current. Choose an inductor

which operated in continuous mode down to 10

percent of the rated output load:

This capacitor should be located close to the IC

using short leads and the volt age rating should be

approximately 1.5 times the maximum input voltage.

(5) Output N-channel MOSFET Selection

ΔI_L= 2 x 10% x I_O

The current ability of the output N-channel

MOSFETs must be at least more than the peak

switching current I_PK. The voltage rating V_DSof the

N-channel MOSFETs should be at least 1.25 times

The inductor “L” value for this system is connected to

be:

(V_IN- V_DS(sat)– V_O) x D_MIN

L ≧

the maximum input voltage.

Choose the low

RDS-ON MOSFETs for reducing the conduction power

loss. Choose the low CISS MOSFETs for reducing

the switching loss. But most of time, the two

ΔI_Lx f_S

If the core loss is a problem, increasing the

inductance of L will be helpful. But large inductor

values reduce the converter’s response time to a

load transient.

factors are trade-off.

Consider the system

requirement and define the MOSFETs rating. The

MOSFETs must be fast (switch time) and must be

located close to the FP6329/A using short leads and

short printed circuit traces. In case of a large

output current, we must layout a copper to reduce

the temperature of these two MOSFETs.

(3) Output Capacitor Selection

The output capacitor is required to filter the output

noise and provide regulator loop stability. When

selecting an output capacitor, the important capacitor

parameters are Equivalent Series Resistance (ESR),

the RMS ripples current rating, the voltage rating,

and capacitance value. For the output capacitor,

the ESR value is the most important parameter.

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Application Information (Continued)

Compensation the Converter

The error amplifier output is compared with the

oscillator triangle wave to provide a PWM wave.

The gain of modulator is input voltage divided by the

ramp amplitude.

The FP6329/A single-phase converter is

voltage-mode controller. The design consideration

for a voltage-mode controller requires external

compensation. Proper compensation of the system

will allow for a calculable bandwidth. In most case,

a Type Ⅲ compensation network is recommended.

The target of the compensation network is to provide

the closed loop transfer function with 0dB crossing

frequency and sufficient phase margin (greater than

45°).

V_IN

GAIN_MODULATOR



V_OSC

V_IN

GAIN_MODULATOR(dB)  20log

V_OSC

The output filter includes the inductor and the output

capacitance. Remember that do not ignore the

DCR of the inductor and the ESR of output

capacitor. The transfer function for the output filter

shows a double pole break frequency at F_LCof LC

filter and a zero at F_ESRof Co and ESR.

The buck converter is composed of three basic

blocks as Figure24 shown: modulator, output filter,

and compensation network. Figure26 is the

voltage-mode

control

loop

with

Type

Ⅲ

compensation for synchronous rectified buck

converter.

1 S  C_OESR

1 S  (ESR  DCR) C_O S²L  C_O

Reference

GAIN_FILTER



Modulator

Output

Filter

Output

Output filter break frequency equation

Compensation

Netw ork

F_ESR



F_LC



2 C_OESR

2 L C_O

Figure24. Basic structure of the buck converter

The open loop small-signal transfer function is

dominated by a DC gain and developed by the

double pole at F_LCand a zero at F_ESR. Figure26

represents the Bode plot of the open loop system

gain. The system has different double pole and

zero frequency. The phase will decline a sharp

slope at the double pole for system with very low

DCR and ESR parameters. System will more

difficult to compensate while the phase needs an

extra boost to provide required phase margin for

stability.

GAIN_OPENLOOP GAIN_MODULATOR GAIN_FILTER

V_IN

1 S  C_OESR

1 S (ESR  DCR)  C_O S²L  C_O





V_OSC

Figure25. Voltage-mode buck converter compensation

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Application Information (Continued)

F_LC

F_P2

F_Z1F_Z2F_P1

COMPENSATION GAIN

CLOSED LOOP GAIN

20 log

-40dB/dec

V_IN

V_OSC

(D_MAX

)

•

F_ESR

OPEN LOOP GAIN

F_C

-20dB/dec

Frequency (Hz)

F_LCF_ESR

Frequency (Hz)

Figure27. Bode plot of converter closed loop gain

Figure26. Bode plot of open loop gain

The following guidelines will help calculate the poles

and zeroes of the compensation network.

Proper Type Ⅲ compensation of the system closes

the control loop to allow for a desired bandwidth

with stability.

The ideal Bode plot for

1. Select R1, 1kΩ to 10kΩ typically.

compensation system should be satisfied two

conditions; one is a gain that decline with

-20dB/decade slope and cross 0dB at the

predictable bandwidth. Another one is phase

margin greater than 45° below the 0dB crossing.

2. Choose a gain (R6/R3) that will shift the open loop

gain to the desired bandwidth, Fc (1/10 to 1/4 of

Fsw). R6 can be calculated by the equation:

V_OSCF_C

R₆





R₃D_MAX

V_IN

F_LC

where D_MAX=1, since FP6329/A supports 100% duty

cycle.

V_OSC=1.5V, the FP6329/A uses a 1.5V ramp

amplitude.

(S 

)(S 

)

R3  R4

R3R4C4

C9(R3  R4)

C4  C5

R6C4C5

R6C5

GAIN_TYPEIII





S(S 

)

R4C9

V_OSCF_C

1.5F_CR₃

V F

IN LC

R₆





R₃D_MAX

Compensation break frequency equation

3. Calculate C5 to place first zero, F_Z1, before F_LC.

F_Z1is adjustable from 0.1 to 0.75 of F_LC. Usually

pick the 0.5 factor.



F_P2

R6C4C5

C4  C5

2R4C9

C5 



2

2  R6  0.5  F

  R6  F

4. Calculate C4 to place first pole, F_P1, at F_ESR

C4 

F_Z1



1

2R6C5F

ESR

2R6C5

2 R4  (R3  R4)

5. Calculate R4 to place second zero, F_Z2, at the

output filter double pole, F_LC.

Figure27 shows the transfer function of closed loop

system with Type Ⅲ compensation. The Type Ⅲ

compensation network applies two zeroes to give a

180° boost to the phase. This boost is necessary

to contract the effect of an under damped at the

double pole.

R4 

1

6. Calculate C9 to place second pole, F_P2, lower than

F_LC. F_P2is adjustable from 0.3 to 1.0 of F_SW

Usually set the F_P2at half the switching frequency.

Set F_P2lower in frequency helps reduce the gain of

the compensation network in high frequency and

minimize duty cycle jitter.

C9 



2  R4  0.5  F_SW  R4  F_SW

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Application Information (Continued)

Layout Notice

(4) Compensation

When designing

regulated power supply, layout is very important.

Using a good layout can solve many problems

high frequency switching

If external compensation components are needed

for stability, they should also be placed closed to

the IC.

Surface mount components are

associated with these types of supplies.

The

recommended here as well for the same reasons

discussed for the filter capacitors.

problems due to a bad layout are often seen at high

current levels and are usually more obvious at large

input to output voltage differentials. Some of the

main problems are loss of regulation at high output

current and/or large input to output voltage

differentials, excessive noise on the output and

switch waveforms, and instability. Using the simple

guidelines that follow will help minimize these

problems.

(5) Traces and Ground Plane

Make all of the power (high current) traces as short,

direct, and thick as possible. It is a good practice

on a standard PCB board to make the traces an

absolute minimum of 15mils (0.381mm) per

Ampere. The inductor, output capacitors, and low

side switch should be as close to each other

possible. This will reduce lead inductance and

resistance as well which in turn reduces noise

spikes, ringing, and resistive losses which produce

voltage errors. The grounds of the IC, input

capacitors, output capacitors, and low side switch

should be connected close together directly to a

ground plane. It would also be a good idea to

have a ground plane on both sides of the PCB.

For multi-layer boards with more than two layers, a

ground plane can be used to separate the power

plane and the signal plane for improved

performance. It is good practice to use one

standard via per 200mA of current if the trace will

need to conduct a significant amount of current

from one plane to the other. Due to the way

switching regulators operate, there are power on

and power off states. During each state there will

be a current loop made by the power components

that are currently conducting. Place the power

components so that during each of the two states

the current loop is conducting in the same direction.

(1) Inductor

Always try to use a low EMI inductor with a ferrite

type closed core. Open core can be used if they

have low EMI characteristics and are located a bit

more away from the low power traces and

components.

(2) Feedback

Try to put the feedback trace as far from the inductor

and noisy power traces as possible. You would also

like the feedback trace to be as direct as possible

and somewhat thick. These two sometimes involve

a trade-off, but keeping it away from inductor EMI

and other noise sources is the more critical of the

two. It is often a good idea to run the feedback trace

on the side of the PCB opposite of the inductor with a

ground plane separating the two.

(3) Filter Capacitors

When using a low value ceramic input filter capacitor,

it should be located as close to the VIN pin of the IC

as possible. This will eliminate as much trace

inductance effects as possible and give the internal

IC rail a cleaner voltage supply. Sometimes using a

small resistor between V_CCand IC VCC pin will more

useful because the RC will be a low-pass filter.

Some designs require the use of a feed-forward

capacitor connected from the output to the feedback

pin as well, usually for stability reasons.

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Outline Information

SOP- 8 Package (Unit: mm)

DIMENSION IN MILLIMETER

SYMBOLS

UNIT

MIN

MAX

1.35

1.75

0.05

1.30

0.31

4.80

3.80

1.20

5.80

0.40

0.25

1.50

0.51

5.00

4.00

1.34

6.20

1.27

Note：Followed From JEDEC MO-012-E

FP6329/A-1.0-APR-2010

fitipower integrated technology lnc.

FP6329/A

Outline Information (Continued)

SOP- 8 (Exposed Pad) Package (Unit: mm)

DIMENSION IN MILLIMETER

SYMBOLS

UNIT

MIN

1.25

0.00

1.25

0.31

4.80

1.82

3.80

1.82

1.20

5.80

0.40

MAX

1.70

0.15

1.55

0.51

5.00

3.35

4.00

2.41

1.34

6.20

1.27

Note：Followed From JEDEC MO-012-E.

Life Support Policy

Fitipower’s products are not authorized for use as critical components in life support devices or other medical system

FP6329/A-1.0-APR-2010

FP6329ASOGTR [FITIPOWER]

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