TMC3211G1C [FAIRCHILD]
Divider, 32-Bit, CMOS, CPGA120, CERAMIC, PGA-120;
| 型号： | TMC3211G1C |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Divider, 32-Bit, CMOS, CPGA120, CERAMIC, PGA-120 时钟 外围集成电路 |
| 文件： | 总10页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
TMC3 2 1 1
In t e g e r Divid e r
3 2 -Bit , 2 0 MOP S
Data is input on separate busses, and quotients are available
on a 32-bit output bus with synchronous three-state enable.
All data inputs and outputs are registered and TTL compati-
ble. All input and output signal timing is referenced to the
rising edge of Clock.
Features
• 32-bit by 16-bit fixed-point integer division with 32-bit
quotient
• 20 MHz clock rate and pipelined throughput rate
• Three-bus I/O architecture allows unrestricted throughput
• Easy system interfacing
• Status flags for divide-by-zero and inexact result
• All inputs and outputs TTL compatible
The TMC3211 has a single system clock and separate load
enable controls for the dividend and divisor registers. This
allows the device to be used in applications requiring divi-
sion by a constant. Underflow automatically produces the
expected zero quotient, and dividing by zero sets a divide-
by-zero output flag.
Applications
• Graphics and image processors
• Matrix operations and geometric transforms
• Perspective extraction
• Radar signal processing
• Range scaling
The internal architecture of the TMC3211 allows all 32-bit
two’s complement integer dividends and nonzero 16-bit
two’s complement integer divisors, without prenormaliza-
tion. The output quotient format is 32-bit integer.
Description
The TMC3211 makes a full-precision, full-speed divide
function available to designers of workstations, image
processors, and radar systems who need to perform
perspective extractions, matrix operations, range scaling, and
other complex functions.
The TMC3211 is a fast monolithic two’s complement integer
divider which can divide a 32-bit dividend by a 16-bit divisor
to produce a 32-bit quotient, with a maximum pipelined
throughput of 20 MOPS (Million Operations Per Second).
Block Diagram
X
X
15-0
16
31-0
32
ENY
ENX
CLK
Divisor
16
Dividend
32
1
16 - Stage
2-18 Non-Restoring
Divider
Flags
32
19
Quotients
32
20
OE
32
2
Q31-0
DZERO, INX
REV. 1.0.1 5/9/00
PRODUCT SPECIFICATION
TMC3211
The 32-bit parallel quotient output register includes
Functional Description
three-state output drivers with synchronous enable control,
which permits multiple TMC3211s to be operated in parallel
or connected directly to a system bus.
General Information
The TMC3211 consists of input registers, a pipelined array
divider, and output (quotient) registers. The 16-bit divisor
and 32-bit dividend input registers can each be loaded inde-
pendently using the two synchronous load enable controls.
The divider is a 16-stage pipelined non-restoring array which
produces a 32-bit quotient and condition flags which indicate
an attempted division by zero, or operations which yield a
non-zero remainder or inexact result.
The TMC3211 requires a total of 19 clock cycles to generate
a full 32-bit quotient result. Once the internal pipeline is full,
a new quotient is available at the output every clock cycle.
Pin Assignments
N M
L K J H G F E D C B A
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
2
A1
GND
C5
C6
C7
C8
C9
C10
Y
Y
Y
Y
G11
G12
G13
H1
Q
L10
L11
L12
L13
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
N1
Q
27
11
8
17
A2
Y
Y
V
Y
Y
Y
Y
V
V
DD
14
13
DD
9
DD
3
A3
Q
GND
4
16
24
25
4
A4
Y
Y
Q
0
24
31
0
5
A5
Q
Q
H2
Y
X
X
X
X
X
X
X
1
5
6
A6
H3
GND
GND
TOP VIEW
CAVITY UP
6
7
A7
C11 GND
C12 GND
H11
H12
H13
J1
5
2
8
A8
Q
Q
2
19
18
4
9
A9
REM
C13
D1
Q
9
6
10
11
12
13
A10
A11
A12
A13
B1
Q
Q
Q
Y
Y
Y
Y
V
V
0
18
17
26
9
D2
J2
3
27
11
14
D3
GND
J3
6
DD
DD
V
D11
D12
D13
E1
V
J11
J12
J13
H1
CLK
DD
DD
YEN
Q
Q
Q
Q
Q
30
10
11
20
19
21
20
24
25
B2
Y
V
Y
Y
Y
Y
Y
GND
GND
15
DD
12
10
7
B3
Y
Y
Y
Y
B4
E2
H2
Q
25
B5
E3
GND
GND
H3
GND
GND
GND
B6
E11
E12
E13
F1
H11
H12
H13
L1
N2
X
X
X
X
X
X
X
21
3
B7
Q
Q
Q
N3
3
12
13
19
18
30
DD
B8
Q
N4
1
5
B9
DZ
Y
Y
V
V
Y
V
N5
22
7
B10
B11
B12
B13
C1
C2
C3
C4
Q
Q
Q
Q
F2
L2
N6
2
21
10
12
13
F3
L3
GND
N7
4
DD
DD
F11
F12
F13
G1
L4
V
N8
7
DD
Q
Q
L5
GND
N9
XEN
OEQ
8
14
15
23
Y
V
V
L6
X
V
X
N10
N11
N12
N13
16
DD
DD
8
Y
L7
Q
Q
Q
DD
15
29
28
26
G2
GND
L8
GND
G3
V
L9
Q
31
DD
2
REV. 1.0.1 5/9/00
TMC3211
PRODUCT SPECIFICATION
Pin Descriptions
Signal Signal
Pin Number
Description
Type
Name
Power
VDD
B3, A4, A13, D11, F11, G12, J11,
K11, L11, L7, L4, L2, J3, G3, F3,
C2, C3
Supply Voltage, Ground. The TMC3211 operates on
a single +5V supply. All power and ground lines must
be connected.
GND
CLK
A1, C4, C11, C12, E11, H11, L12,
M12, M11, L5, L3, N1, K3, H3, G2,
E3, D3
Clock
Inputs
M9
System Clock. The TMC3211 has a single Clock input.
All input and output signal timing is referenced to the
rising edge of Clock.
Y31-0
M1, L1, K2, K1, J2, J1, H2, H1, G1, Dividend Data. The 32-bit Dividend is presented
F1, F2, E1, E2, D1, D2, C1, B2, A2, through the registered Y input port. Y31 is the sign bit.
A3, B4, C5, B5, A5, C6, B6, A6, A7, The LSB is Y0.
C7, B7, A8, B8, C8
X15-0
U8, M8, N8, N7, M7, N6, M6, L6,
NS, MS, N4, M4, N3, M3, N2, M2
Divisor Data. The 16-bit Divisor is presented through
the registered X input port. X15 is the sign bit. The LSB
is X0.
Outputs Q31-0
Controls YEN
L9, M10, N11, N12, L10, N13, M13, Quotient Data. The current Quotient is available on the
L13, K12, K13, J12, J13, H12, H13, registered Q output bus. Q31 is the sign bit. The LSB
G11, G13, F13, F12, E13, E12,
D13, D12, C13, B13, B12, A12,
C10, B11, A11, B10, C9, A10
is Q0.
B1
Dividend Write Enable. Data present at the Dividend
input Y31-0 is latched into the input registers on the
rising edge of clock when the enable control YEN is
LOW.
XEN
OEQ
N9
Divisor Write Enable. Data present at the Divisor input
X15-0 is latched into the input registers on the rising
edge of clock when the enable control XEN is LOW.
N10
Quotient Output Enable. The quotient output bus Q31-0
and flags DZ and REM are in the high-impedance state
when the registered Output Enable OEQ is HIGH.
When OEQ is LOW, they are enabled on the next clock
cycle.
Flags
DZ
B9
A9
Divide-By Zero Flag. When a zero divisor is input, the
resulting invalid output quotient will be accompanied by
a registered Divide-By-Zero Flag HIGH.
REM
Inexact Remainder Flag. Whenever a division
operation leaves a nonzero remainder, the resulting
qotient is accompanied by a registered nonzero
Remainder Flag HIGH.
No
D4
Index Pin (optional)
Connect
REV. 1.0.1 5/9/00
3
PRODUCT SPECIFICATION
TMC3211
Data Formats
Applications Discussion
The TMC3211 supports fixed-point two’s complement data
formats. By keeping track of the binary points of the input
data, the user can then interpret the resulting quotient prop-
erly. Two possible binary weightings of the input and output
bits are as follows:
Division Using A Constant
By utilizing the separate input data register load enable con-
trols, the TMC3211 can perform division by a constant. The
data currently held remain in the input registers until updated
by the user.
Pin D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
14
14
13
13
13
12
12
12
11
11
11
10
10
10
9
9
9
8
8
8
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
Y
X
Q
-2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
15
-2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
-2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Figure 1. Integer Data Format
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
5
-11
-12
-13
-14
-15
-16
0
-17
-1
-18
-2
-19
-3
-20
-4
-21
-5
-22
-6
-23
-7
-24
-8
-25
-9
-26
-10
-11
-27
-11
-12
-28
-12
-13
-29
-13
-14
-30
-14
-15
-31
-15
-16
Y
-2
.2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
X
Q
-2
.2
2
2
2
2
2
2
2
2
15
14
13
12
11
10
9
8
7
6
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-2
.2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Figure 2. Fractional Data Format
where a leading minus sign indicates a sign bit.
Inexact Results
The flag REM is provided to indicate that the current quotient
left a nonzero remainder and was truncated toward zero.
Care must be taken when adopting fractional data formats.
By observing the binary weighting applied to the input data
in the dividend and divisor, the binary point of the quotient
can then be correctly established. The difference lies only in
constant scale factors, which must be considered in order to
maintain a data format which is compatible with the bit
weighting of the hardware system. The two most common
choices are fractional and integer notation. If integer notation
is used, the LSBs of the dividend, divisor, and quotient all
have the same value. With fractional notation the MSBs are
all of equal weight.
Negative Full-Scale Overflow
Due to a finite data word width, a two’s complement over-
flow error occurs under the following unique condition:
Divisor Y=80000000H (– Full-Scale)
Dividend X=FFFFH (-1)
Result:
Quotient Q=80000000H (– Full-Scale)
Divide by Zero
The flag DZ indicates that the divisor input for the current
calculation was a zero, independent of the dividend. Dividing
by zero is an undefined operation yielding a meaningless
quotient. Thus, this flag must be monitored to guard against
possible errors.
As stated above, this is due to a limitation in the number of bits
available to indicate a positive full-scale quotient, and data
overflows into the MSB position to indicate an incorrect sign.
4
REV. 1.0.1 5/9/00
TMC3211
PRODUCT SPECIFICATION
t
t
PWL
PWH
2
1
3
19
20
21
CLK
t
H
t
CY
t
S
Y
Y
Y
2
Y
X
0
1
31-0
Note 1
X
X
1
15-0
0
XEN
YEN
t
t
HO
D
Q
Q
Q
2
2
0
1
Q
, DZ, REM
31-0
Notes:
1. Demonstrates division by a constant, Q = Y /X .
2
2
1
2. Assumes OEQ = Low.
Figure 3. Timing Diagram
V
V
DD
DD
n Substrate
D1
n Substrate
p
p
D1
p+
p+
Control
Input
Output
1kΩ
n+
D2
n+
D2
n
n
p Well
p Well
GND
Figure 5. Equivalent Output Circuit
GND
Figure 4. Equivalent Input Circuit
REV. 1.0.1 5/9/00
5
PRODUCT SPECIFICATION
TMC3211
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Supply Voltage
Input Voltage
Output
Min
Max
+7.0
Units
V
-0.5
-0.5
-0.5
-3.0
VDD + 0.5
VDD + 0.5
6.0
V
Applied Voltage2
Forced Current3,4
V
mA
sec
°C
°C
°C
°C
Short-circuit duration (single output in HIGH state to ground)
1
Temperature
Operating, case
Junction
-60
-65
+130
175
Lead, soldering (10 seconds)
Storage
300
+150
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating
conditions. Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range, and measured with respect to GND.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
Operating Conditions
Temperature Range
Parameter
Test Conditions
Standard
Nom.
5.0
Units
Min.
Max.
5.25
0.8
VDD
VIL
VIH
IOL
IOH
tCY
tPWL
tPWH
tS
Supply Voltage
4.75
V
V
Input Voltage, Logic LOW
Input Voltage, Logic HIGH
Output Current, Logic LOW
Output Current, Logic HIGH
Cycle Time
2.0
V
4.0
-2.0
50
mA
mA
ns
ns
ns
ns
ns
°C
VDD = Min
VDD = Min
VDD = Min
Clock Pulse Width, LOW
Clock Pulse Width, HIGH
Input Setup Time
15
15
12
6
tH
Input Hold Time
TA
Ambient Temperature, Still Air
0
70
6
REV. 1.0.1 5/9/00
TMC3211
PRODUCT SPECIFICATION
DC Characteristics within Specified Operating Conditions1
Temperature Range
Standard
Parameter
Test Conditions
Units
Min.
Max.
IDDQ
IDDU
IIL
Supply Current, Quiescent
VDD = Max, VIN = 0V
5
mA
mA
µA
µA
V
Supply Current, Unloaded
Input Current, Logic LOW
Input Current, Logic HIGH
Output Voltage, Logic LOW
Output Voltage, Logic HIGH
VDD = Max, OEQ = 5V, f = 20MHz
VDD = Max, VIN = 0V
150
-10
10
IIH
VDD = Max, VIN = VDD
VDD = Min, lOL = Max
VOL
VOH
IOZL
0.4
VDD = Min, lOH = Max
2.4
V
Hi-Z Output Leakage Current, VDD = Max, VIN = 0V
Output LOW
-40
40
µA
IOZH
IOS
Hi-Z Output Leakage Current, VDD = Max, VIN = VDD
Output HIGH
µA
Short-Circuit Output Current
VDD = Max, Output HIGH, one pin to
-150
mA
ground, one second duration max.
Cl
Input Capacitance
Output Capacitance
TA = 25°C, f = 1MHz
10
10
pF
pF
CO
TA = 25°C, f = 1MHz
Note:
1. Actual test conditions may vary from those shown, but guarantee operation as specified
AC Characteristics within Specified Operating Conditions
Temperature
Standard
Parameter
Test Conditions
Units
Min
Max
tD
Output Delay1
Output Hold Time
VDD = Min, CLOAD = 25pF
VDD = Max, CLOAD = 25pF
35
ns
ns
tHO
5
Note:
1. Equivalent to t
and t
of the three-state outputs
DIS
ENA
REV. 1.0.1 5/9/00
7
PRODUCT SPECIFICATION
TMC3211
Mechanical Dimensions
120-Pin Ceramic Pin Grid Array—G1 Package
Notes:
Inches
Millimeters
Symbol
Notes
1. Pin #1 identifier shall be within shaded area shown.
2. Pin diameter excludes solder dip finish.
3. Dimension "M" defines matrix size.
Min.
Max.
Min.
Max.
A
.080
.040
.125
.016
.160
.060
.215
.020
2.03
1.01
3.17
0.40
4.06
1.53
5.46
0.51
A1
A2
øB
øB2
D
4. Dimension "N" defines the maximum possible number of pins.
5. Orientation pin is at supplier's option.
2
2
6. Controlling dimension: inch.
.050 NOM.
1.27 NOM.
1.340
1.380
33.27
35.05
SQ
D1
e
1.200 BSC
.100 BSC
30.48 BSC
2.54 BSC
L
.110
.145
.190
2.79
3.68
4.83
L1
M
.170
4.31
13
13
3
4
N
120
120
.003
—
.076
—
P
A
A2
A1
øB
øB2
L
D
P
e
Top View
Cavity Up
D1
Pin 1 Identifier
8
REV. 1.0.1 5/9/00
TMC3211
PRODUCT SPECIFICATION
Mechanical Dimensions
120-Pin Plastic Pin Grid Array—H5 Package
Notes:
Inches
Millimeters
Symbol
Notes
1. Pin #1 identifier shall be within shaded area shown.
2. Dimension "M" defines matrix size.
Min.
Max.
Min.
Max.
A
.080
.040
.105
.017
.125
.060
.180
.020
2.03
1.02
2.67
0.43
3.18
1.52
4.57
0.51
3. Dimension "N" defines the maximum possible number of pins.
4. Controlling dimension: inch.
A1
A2
øB
øB2
D
.050 NOM.
1.27 NOM.
1.340
1.350
34.04
35.05
D1
e
1.200 BSC
.100 BSC
.120 .140
30.48 BSC
2.54 BSC
3.05 3.56
L
M
13
13
2
3
N
121
121
.003
—
.076
—
P
A
A2
L
A1
e
øB
øB2
D
P
Bottom View
D1
Top View
Pin 1 Identifier
Beveled Corner
Vendor Option
REV. 1.0.1 5/9/00
9
PRODUCT SPECIFICATION
TMC3211
Ordering Information
Temperature
Product Number
Screening
Package
Package Marking
Range
TMC3211H5C
TMC3211G1C
0 to 70°C
0 to 70°C
Commercial
Commercial
120 Pin Plastic Pin Grid Array
120 Pin Ceramic Pin Grid Array
3211H5C
3211G1C
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OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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