TMC2011AB2C1 [FAIRCHILD]
Variable-Length Shift Register; 可变长度移位寄存器
| 型号： | TMC2011AB2C1 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Variable-Length Shift Register |
| 文件： | 总12页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
TMC2 0 1 1 A/2 1 1 1 A
Va ria b le -Le n g t h S h ift Re g is t e r
Features
Applications
• Low power CMOS
• Video filtering
• TMC2011A is a pin compatible replacement for the
TDC1011 and TMC2011
• TMC2211A is a pin compatible replacement for the
TMC2111
• Inputs and outputs are TTL compatible
• DC–40MHz clock rate
• High speed data registers
• Local storage registers
• Digital delay lines
• Television special effects
• Pipeline register
• Selectable delay lengths (TMC2011A: 3 to 18 stages,
TMC2111A: 1 to 16 stages)
• Special 4-bit wide mixed-delay mode (TMC2011A)
• Available in 24-pin CERDIP and plastic DIP and 28-lead
Plastic Leadless Chip Carrier
Description
The TMC2011A and TMC2111A are high-speed, byte-wide
shift registers with programmable delay lengths.
The TMC2011A and TMC2111A are fully synchronous,
with all operations controlled by a single master clock. Input
and output registers are positive-edge triggered D-type flip-
flops. The length and mode controls are also registered. Both
devices operate with a maximum clock rate of 40 MHz.
The TMC2011A can be programmed to any length between
3 and 18 stages. It offers a special split-word mode which
allows for mixed delay lengths. The TMC2011A, con-
structed in low-power CMOS, is pin and function compatible
with the bipolar TDC1011.
Fabricated in a submicron CMOS process, the TMC2011A
and TMC2111A are TTL-compatible, and are available in
24-pin CERDIP and Plastic DIP packages as well as a
28-lead Plastic Leadless Chip Carrier.
The TMC2111A is a byte-wide shift register that can be pro-
grammed to lengths of 1 to 16 stages.
Block Diagrams
TMC2011A
TMC2111A
R
R
R
DI
R
R
R
R
R
DI
7-0
1
14
15
3-0
1
2
3
16
17
8
4
8
8
4
4
8
8
4
4
8-Bit Wide
1 of 16 Selector
4-Bit Wide
1 of 16 Selector
L
R
R
R
R
L
3-0
DO
3-0
DO
DO
L
16
L
18
7-0
3-0
7-4
4
8
8
8
4
4
4
4
4
4
4
65-2011A-02
CLK
4-Bit Wide
1 of 16 Selector
R
4
4
R
I
18
MC
4
4
CLK
4
4
4
DI
R
R
R
R
R
17
7-4
1
2
3
16
65-2011A-01
4
Rev. 1.1.0
TMC2011A/2111A
PRODUCT SPECIFICATION
Functional Description
The TMC2011A consists of two 4-bit wide, programmable
length shift registers. The TMC2111A consists of a single
8-bit wide, programmable length shift register. The internal
registers of each device share control signals and a common
clock.
Pin Assignments
24 Lead DIP (B2, N2) Packages
DI
DI
DI
DI
L
1
24
DO
DO
DO
DO
DI
DI
DI
DI
L
1
24
DO
DO
DO
DO
0
1
2
3
0
1
0
1
2
3
0
1
2
3
0
1
0
1
2
3
L
2
L
3
L
2
L
3
L
L
V
GND
MC
V
GND
GND
DD
DD
CLK
CLK
DI
DI
DI
DI
DO
DO
DO
DO
DI
DI
DI
DI
DO
DO
DO
DO
4
5
6
7
4
5
6
7
4
5
6
7
4
5
6
7
12
13
12
13
65-2011A-03
28 Lead PLCC (R3) Package
1 28
1 28
DI
L
L
NC
DI
L
L
NC
3
0
1
3
0
1
L
2
L
3
L
2
L
3
V
CLK
DI
TMC2011A
GND
GND
MC
V
CLK
DI
4
TMC2111A
GND
GND
MC
DD
DD
4
NC
NC
NC
NC
65-2011A-04
2
PRODUCT SPECIFICATION
TMC2011A/2111A
Pin Descriptions – TMC2011A
Pin Number
Pin Name
Power
DIP
PLCC
Pin Function Description
V
DD
7
8
Supply Voltage. The TMC2011A and operates from a single +5V supply.
All power and ground lines must be connected.
GND
18
21,22
Ground. The TMC2011A operates from a single +5V supply. All power
and ground lines must be connected.
Data Inputs
DI
7-0
12,11,10, 14,13,12, Data Input. Eight inputs are provided for the data, which pass through the
9,4,3,2,1 10,5,4,3,2 shift register unchanged. The eight inputs on the TMC2011A are divided
into two groups of four bits to allow mixed delay operation. The lengths of
these two groups are different when the Mode Control (MC) is HIGH (see
Table 1). When MC is LOW both groups have equal delays.
Data Outputs
DO
13,14,15, 15,16,17, Data Output. The outputs of the shift register are delayed relative to the
7-0
16,21,22, 18,26,27, input signals. The amount of the delay is programmable (see Table 1).
23,24
28,1
The outputs remain valid for a minimum of t nanoseconds after the
HO
leading edge of CLK. This allow the data to be latched into circuits with
non-zero hold time requirements.
Controls
CLK
8
9
Master Clock. All inputs and outputs are synchronous and operate from a
single master clock. All operations occur on the rising edge of the master
clock.
L
3-0
19,20,6,5 23,24,7,6 Length Select. The length select input is used to determine the register
delay of the TMC2011A. This input is registered and affects the output t
DO
after the clock edge after it is input to the device (see Timing Diagram).
Delay lengths are specified in Table 1.
MC
17
20
Mode Control. The Mode Control is used to select the special 4-bit wide
split mode. When HIGH, the delay on DO
DO
3-0
is fixed at 18 stages, while
have the delay specified by the length select. When MC is LOW, all
7-4
eight bits have equal delays as specified by the length select.
3
TMC2011A/2111A
PRODUCT SPECIFICATION
Pin Descriptions – TMC2111A
Pin Number
Pin Name
Power
DIP
PLCC
Pin Function Description
V
7
8
Supply Voltage. The TMC2111A operates from a single +5V supply. All
DD
power and ground lines must be connected.
GND
17,18
20,21,22 Ground. The TMC2111A operates from a single +5V supply. All power
and ground lines must be connected.
Data Inputs
DI
7-0
12,11,10, 14,13,12, Data Input. Eight inputs are provided for the data, which pass through the
9,4,3,2,1 10,5,4,3,2 shift register unchanged. The TMC2111A consists of a single group of
eight bits with all data bits having equal delays.
Data Outputs
DO
13,14,15, 15,16,17, Data Output. The outputs of the shift register are delayed relative to the
7-0
16,21,22, 18,26,27, input signals. The amount of the delay is programmable (see Table 1).
23,24
28,1
The outputs remain valid for a minimum of t nanoseconds after the
HO
leading edge of CLK. This allow the data to be latched into circuits with
non-zero hold time requirements.
Controls
CLK
8
9
Master Clock. All inputs and outputs are synchronous and operate from a
single master clock. All operations occur on the rising edge of the master
clock.
L
3-0
19,20,6,5 23,24,7,6 Length Select. The length select input is used to determine the register
delay of the TMC2111A. This input is registered and affects the output t
DO
after the clock edge after it is input to the device (see Timing Diagram).
Delay lengths are specified in Table 1.
Table 1. Programming Length Controls
TMC2011A
Input Code
Mode (MC) =0
Mode (MC) =1
TMC2111A
L
L
2
L
L
0
DO
3-0
Length DO
Length DO
3-0
Length DO
Length DO
7-0
Length
3
1
7-4
7-4
0
0
0
0
3
4
5
6
7
8
9
3
3
4
5
6
7
8
9
18
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4
5
6
7
8
9
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
4
PRODUCT SPECIFICATION
TMC2011A/2111A
Absolute Maximum Ratings
(beyond which the device may be damaged)1
Parameter
Min
-0.5
-0.5
-0.5
-3.0
Typ
Max
Unit
Supply Voltage
7.0
V
Input Voltage
V
V
+ 0.5
V
V
DD
Output, Applied Voltage2
Output, Externally Forced Current3,4
+ 0.5
DD
6.0
mA
sec
Output, Short Circuit Duration (single output in HIGH state to
ground)
1
Operating, Ambient Temperature
Junction Temperature
Storage Temperature
Lead Soldering (10 seconds)
Notes:
-20
-65
110
140
150
300
°C
°C
°C
°C
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
Operating Conditions
Parameter
Min
Nom
Max
5.25
30
Units
V
V
Power Supply Voltage
Clock frequency
4.75
5.0
DD
f
TMC2011A, 2111A
MHz
CLK
TMC2011A-1, 2111A-1
40
t
t
t
t
CLK pulse width, HIGH
CLK pulse width, LOW
Input Data Set-up Time
Input Data Hold Time
Input Voltage, Logic HIGH
12
12
6
ns
ns
ns
ns
V
PWH
PWL
S
1
H
V
DI , L , MC
7-0 3-0
2.0
2.6
IH
CLK
V
Input Voltage, Logic LOW
Output Current, Logic HIGH
Output Current, Logic LOW
Ambient Temperature, Still Air
0.8
-2.0
4.0
70
V
IL
OH
OL
I
I
mA
mA
°C
T
A
0
5
TMC2011A/2111A
PRODUCT SPECIFICATION
Electrical Characteristics
Parameter
Conditions
Min
Typ
Max
Units
I
Power Supply Current, Unloaded
V
DD
V
DD
= Max, f
= Max, f
=30 MHz
=40 MHz
30
40
mA
mA
DDU
CLK
CLK
I
Power Supply Current, Quiescent
I/O Pin Capacitance
V
= Max, CLK = LOW
0.5
mA
pF
mA
mA
mA
V
DDQ
DD
C
5
PIN
I
I
I
Input Current, HIGH
V
V
= Max, V = V
IN DD
±10
±10
IH
DD
Input Current, LOW
= Max, V = 0 V
IN
IL
DD
Short-Circuit Current
Output Voltage, HIGH
Output Voltage, LOW
-100
OS
V
V
DO , I
7-0 OH
= Max
2.4
OH
DO , I = Max
7-0 OL
0.4
V
OL
Switching Characteristics
Parameter
Conditions
Min
Typ
Max
Units
ns
t
t
Output Delay Time
Output Hold Time
C
C
= 25 pF
= 25 pF
15
DO
HO
LOAD
3
ns
LOAD
6
PRODUCT SPECIFICATION
TMC2011A/2111A
Timing Diagrams
1/f
t
t
PWH
4
PWL
CLK
1
2
3
5
t
t
H
S
Data
N+L-1
Data
N+L
Data
N+L+1
Data
N+L+2
DI
7-0
t
t
H
S
MC, L
DO
Controls
Controls
Controls
Controls
Controls
3-0
t
t
DO
HO
Data
N-1
Data
N
Data
N+1
Data
N+2
7-0
L is Length from Table 1.
65-2011A-05
Figure 1. Preset Length Controls
CLK
Data
10
Data
11
Data
12
Data
13
Data
14
Data
15
Data
16
DI
L
7-0
0010
0010
0011
0011
0011
0011
0011
3-0
TMC2011A
DO (MC=0)
Data
5
Data
6
Data
7
Data
8
Data
8
Data
9
Data
10
7-0
TMC2111A
DO (MC=1)
Data
7
Data
8
Data
9
Data
10
Data
10
Data
11
Data
12
3-0
65-2011A-06
Figure 2. Length Control Operation
Equivalent Circuits
V
DD
V
DD
p
n
p
n
Data or
Control
Input
Output
27011B
27014B
GND
GND
Figure 3. Equivalent Digital Input Circuit
Figure 4. Equivalent Digital Output Circuit
7
TMC2011A/2111A
PRODUCT SPECIFICATION
Notes:
8
PRODUCT SPECIFICATION
TMC2011A/2111A
Mechanical Dimensions
24-Lead Ceramic DIP Package
Notes:
Inches
Millimeters
Min. Max.
Symbol
Notes
1. Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
Min.
Max.
A
—
.200
.023
.065
.015
1.280
.310
—
.36
1.14
.20
—
5.08
.58
2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads
number 1, 12, 13 and 24 only.
b1
b2
c1
D
.014
.045
.008
—
8
2, 8
1.65
.38
3. Dimension "Q" shall be measured from the seating plane to the base
plane.
8
4
4
5
7
32.51
7.87
4. This dimension allows for off-center lid, meniscus and glass overrun.
E
.220
5.59
5. The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 24.
e
.100 BSC
.300 BSC
2.54 BSC
7.62 BSC
eA
L
.125
.200
.060
—
3.18
5.08
1.52
—
6. Applies to all four corners (leads number 1, 12, 13, and 24).
Q
s1
a
.015
.005
90¡
.38
.13
90¡
3
6
7. "eA" shall be measured at the center of the lead bends or at the
centerline of the leads when "a" is 90¡.
105¡
105¡
8. All leads – Increase maximum limit by .003 (.08mm) measured at the
center of the flat, when lead finish applied.
9. Twenty-two spaces.
D
1
12
13
NOTE 1
E
24
s1
e
eA
Q
A
c1
a
L
b1
b2
9
TMC2011A/2111A
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
24-Lead Plastic DIP Package
Notes:
Inches
Millimeters
Min. Max.
Symbol
Notes
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Min.
Max.
2. "D" and "E1" do not include mold flashing. Mold flash or protrusions
shall not exceed .010 inch (0.25mm).
A
—
.210
—
—
.38
5.33
—
A1
A2
B
.015
.115
3. Terminal numbers are shown for reference only.
4. "C" dimension does not include solder finish thickness.
5. Symbol "N" is the maximum number of terminals.
.195
2.53
4.95
.014
.045
.008
1.125
.005
.300
.240
.36
1.14
.20
.022
.070
.015
1.275
—
.56
1.78
.38
B1
C
4
2
D
28.58
.13
32.39
—
D1
.325
.280
7.62
6.10
8.26
7.11
E
E1
e
2
5
.100 BSC
2.54 BSC
eB
L
N
—
.430
.160
—
10.92
4.06
.115
2.92
24
24
D
1
12
E1
D1
13
24
E
e
A
A1
C
L
eB
B1
B
10
PRODUCT SPECIFICATION
TMC2011A/2111A
Mechanical Dimensions (continued)
28-Lead PLCC Package
Notes:
Inches
Millimeters
Symbol
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982
Min.
Max.
Min.
Max.
2. Corner and edge chamfer (J) = 45¡
A
.165
.090
.020
.013
.026
.485
.450
.180
.120
—
4.19
2.29
.51
4.57
3.05
—
3. Dimension D1 and E1 do not include mold protrusion. Allowable
protrusion is .101" (.25mm)
A1
A2
B
.021
.032
.495
.456
.33
.53
B1
.66
.81
D/E
D1/E1
D3/E3
e
12.32
11.43
12.57
11.58
3
2
.300 BSC
.050 BSC
.042 .048
7.62 BSC
1.27 BSC
1.07 1.22
J
ND/NE
N
7
7
28
28
ccc
—
.004
—
0.10
E
E1
J
D
D1
D3/E3
B1
J
e
A
A1
– C – LEAD COPLANARITY
ccc C
B
A2
11
TMC2011A/2111A
PRODUCT SPECIFICATION
Ordering Information
Product
Number
Temperature
Speed
Grade
Package
Marking
Range
Screening
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Package
TMC2011AB2C
TMC2011AB2C1
TMC2011AN2C
TMC2011AN2C1
TMC2011AR3C
TMC2011AR3C1
TMC2111AB2C
TMC2111AB2C1
TMC2111AN2C
TMC2111AN2C1
TMC2111AR3C
TMC2111AR3C1
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
30 MHz
40 MHz
30 MHz
40 MHz
30 MHz
40 MHz
30 MHz
40 MHz
30 MHz
40 MHz
30 MHz
40 MHz
24 Pin 0.3" CerDIP
24 Pin 0.3" CerDIP
24 Pin 0.3" Plastic DIP
24 Pin 0.3" Plastic DIP
28 Lead PLCC
2011AB2C
2011AB2C1
2011AN2C
2011AN2C1
2011AR3C
2011AR3C1
2111AB2C
2111AB2C1
2111AN2C
2111AN2C1
2111AR3C
2111AR3C1
28 Lead PLCC
24 Pin 0.3" CerDIP
24 Pin 0.3" CerDIP
24 Pin 0.3" Plastic DIP
24 Pin 0.3" Plastic DIP
28 Lead PLCC
28 Lead PLCC
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
5/20/98 0.0m 001
Stock#DS30002011A
Ó 1998 Fairchild Semiconductor Corporation
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