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SCAN182541A [FAIRCHILD]

Non-Inverting Line Driver with 25ohm Series Resistor Outputs; 与25ohm串联电阻输出非反相线路驱动器
SCAN182541A
型号： SCAN182541A
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述：

Non-Inverting Line Driver with 25ohm Series Resistor Outputs
与25ohm串联电阻输出非反相线路驱动器

驱动器
文件： 总11页 (文件大小：98K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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January 1993  
Revised August 2000  
SCAN182541A  
Non-Inverting Line Driver  
with 25Ω Series Resistor Outputs  
General Description  
Features  
■ IEEE 1149.1 (JTAG) Compliant  
The SCAN182541A is a high performance BiCMOS line  
driver featuring separate data inputs organized into dual 9-  
bit bytes with byte-oriented paired output enable control  
signals. This device is compliant with IEEE 1149.1 Stan-  
dard Test Access Port and Boundary-Scan architecture  
with the incorporation of the defined Boundary-Scan test  
logic and test access port consisting of Test Data Input  
(TDI), Test Data Out (TDO), Test Mode Select (TMS), and  
Test Clock (TCK).  
■ High performance BiCMOS technology  
■ 25Ω series resistor outputs eliminate need for external  
terminating resistors  
■ Dual output enable signals per byte  
■ 3-STATE outputs for bus-oriented applications  
■ 25 mil pitch SSOP (Shrink Small Outline Package)  
■ Includes CLAMP, IDCODE and HIGHZ instructions  
■ Additional instructions SAMPLE-IN, SAMPLE-OUT and  
EXTEST-OUT  
■ Power up 3-STATE for hot insert  
■ Member of Fairchild’s SCAN Products  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
SCAN182541ASSC  
MS56A  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin  
Description  
Names  
AI(0–8)  
Input Pins, A Side  
BI(0–8)  
Input Pins, B Side  
AOE1,  
AOE2  
3-STATE Output Enable Input Pins, A Side  
BOE1,  
BOE2  
3-STATE Output Enable Input Pins, B Side  
AO(0–8)  
BO(0–8)  
Output Pins, A Side  
Output Pins, B Side  
© 2000 Fairchild Semiconductor Corporation  
DS011543  
www.fairchildsemi.com  
Truth Tables  
Inputs  
Inputs  
AO(0–8)  
BO(0–8)  
†AOE1  
†AOE2  
AI(0–8)  
†BOE1  
†BOE2  
BI(0–8)  
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
L
L
H
X
L
X
H
L
H
X
X
L
H
Z
Z
L
L
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Z = High Impedance  
† = Inactive-to-active transition must occur to enable outputs upon  
power-up.  
Block Diagrams  
Byte A  
Tap Controller  
Byte B  
Note: BSR stands for Boundary Scan Register.  
www.fairchildsemi.com  
2
Description of BOUNDARY-SCAN Circuitry  
The scan cells used in the BOUNDARY-SCAN register are  
one of the following two types depending upon their loca-  
tion. Scan cell TYPE1 is intended to solely observe system  
data, while TYPE2 has the additional ability to control sys-  
tem data.  
The INSTRUCTION register is an 8-bit register which cap-  
tures the default value of 10000001 (SAMPLE/PRELOAD)  
during the CAPTURE-IR instruction command. The benefit  
of capturing SAMPLE/PRELOAD as the default instruction  
during CAPTURE-IR is that the user is no longer required  
to shift in the 8-bit instruction for SAMPLE/PRELOAD. The  
sequence of: CAPTURE-IR→EXIT1-IR→ UPDATE-IR will  
update the SAMPLE/PRELOAD instruction. For more infor-  
mation refer to the section on instruction definitions.  
Scan cell TYPE1 is located on each system input pin while  
scan cell TYPE2 is located at each system output pin as  
well as at each of the two internal active-high output enable  
signals. AOE controls the activity of the A-outputs while  
BOE controls the activity of the B-outputs. Each will acti-  
vate their respective outputs by loading a logic high.  
Instruction Register Scan Chain Definition  
The BYPASS register is a single bit shift register stage  
identical to scan cell TYPE1. It captures a fixed logic low.  
Bypass Register Scan Chain Definition  
Logic 0  
MSB→LSB  
Instruction Code  
00000000  
10000001  
10000010  
00000011  
01000001  
01000010  
00100010  
10101010  
11111111  
Instruction  
EXTEST  
SAMPLE/PRELOAD  
CLAMP  
SCAN182541A Product IDCODE  
(32-Bit Code per IEEE 1149.1)  
HIGH-Z  
Part  
Manufacture Required b  
SAMPLE-IN  
SAMPLE-OUT  
EXTEST-OUT  
IDCODE  
Version Entity  
r
y
1149.1  
1
Number  
ID  
0000 111111 000000100 00000001111  
1
BYPASS  
MSB  
LSB  
All Others  
BYPASS  
Scan Cell TYPE1  
Scan Cell TYPE2  
3
www.fairchildsemi.com  
Description of BOUNDARY-SCAN Circuitry (Continued)  
BOUNDARY-SCAN Register  
Scan Chain Definition (42 Bits in Length)  
www.fairchildsemi.com  
4
Description of BOUNDARY-SCAN Circuitry (Continued)  
Input BOUNDARY-SCAN Register  
Scan Chain Definition (22 Bits in Length)  
When SAMPLE-IN is Active  
5
www.fairchildsemi.com  
Description of BOUNDARY-SCAN Circuitry (Continued)  
Output BOUNDARY-SCAN Register  
Scan Chain Definition (20 Bits in Length)  
When SAMPLE-OUT and EXTEXT Out are Active  
www.fairchildsemi.com  
6
Description of BOUNDARY-SCAN Circuitry (Continued)  
BOUNDARY-SCAN Register Definition Index  
Bit No.  
Pin Name  
Pin No.  
Pin Type  
Scan Cell Type  
TYPE1  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
AOE1  
AOE2  
AOE  
BOE1  
BOE2  
BOE  
AI0  
3
Input  
Input  
54  
TYPE1  
TYPE2  
TYPE1  
TYPE1  
TYPE2  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE2  
TYPE2  
TYPE2  
TYPE2  
TYPE2  
TYPE2  
TYPE2  
TYPE2  
TYPE2  
TYPE2  
TYPE2  
TYPE2  
TYPE2  
TYPE2  
TYPE2  
TYPE2  
TYPE2  
TYPE2  
Internal  
Input  
Control  
Signals  
26  
31  
Input  
Internal  
Input  
55  
53  
52  
50  
49  
47  
46  
44  
43  
42  
41  
39  
38  
36  
35  
33  
32  
30  
2
AI1  
Input  
AI2  
Input  
AI3  
Input  
AI4  
Input  
A–in  
AI5  
Input  
AI6  
Input  
AI7  
Input  
AI8  
Input  
BI0  
Input  
BI1  
Input  
BI2  
Input  
BI3  
Input  
BI4  
Input  
B–in  
BI5  
Input  
BI6  
Input  
BI7  
Input  
BI8  
Input  
AO0  
AO1  
AO2  
AO3  
AO4  
AO5  
AO6  
AO7  
AO8  
BO0  
BO1  
BO2  
BO3  
BO4  
BO5  
BO6  
BO7  
BO8  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
4
5
7
8
A–out  
10  
11  
13  
14  
15  
16  
18  
19  
21  
22  
24  
25  
27  
8
7
6
5
4
B–out  
3
2
1
0
7
www.fairchildsemi.com  
Absolute Maximum Ratings(Note 1)  
Recommended Operating  
Conditions  
Storage Temperature  
−65°C to +150°C  
Ambient Temperature under Bias  
Junction Temperature under Bias  
VCC Pin Potential to Ground Pin  
Input Voltage (Note 2)  
−55°C to +125°C  
−55°C to +150°C  
−0.5V to +7.0V  
Free Air Ambient Temperature  
Supply Voltage  
−40°C to +85°C  
+4.5V to +5.5V  
(∆V/∆t)  
Minimum Input Edge Rate  
Data Input  
−0.5V to +7.0V  
50 mV/ns  
Input Current (Note 2)  
−30 mA to +5.0 mA  
Enable Input  
20 mV/ns  
Voltage Applied to Any Output  
in Disabled or Power-Off State  
in the HIGH State  
−0.5V to +5.5V  
−0.5V to VCC  
Current Applied to Output  
in LOW State (Max)  
Twice the Rated IOL (mA)  
Note 1: Absolute Maximum Ratings are values beyond which the device  
may be damaged or have its useful life impaired. Functional operation  
under these conditions is not implied.  
DC Latchup Source Current  
Over Voltage Latchup (I/O)  
EDS (HBM) Min.  
−500 mA  
10V  
Note 2: Either voltage limit or current limit is sufficient to protect inputs.  
2000V  
DC Electrical Characteristics  
VCC  
Symbol  
VIH  
Parameter  
Input HIGH Voltage  
Min  
Typ  
Max  
Units  
V
Conditions  
Recognized HIGH Signal  
Recognized LOW Signal  
2.0  
VIL  
Input LOW Voltage  
0.8  
V
VCD  
VOH  
Input Clamp Diode Voltage  
Output HIGH Voltage  
Min  
Min  
−1.2  
V
I
I
I
I
IN = −18 mA  
OH = −3 mA  
OH = −32 mA  
OL = 15 mA  
2.5  
2.0  
V
Min  
V
VOL  
IIH  
Output LOW Voltage  
Input HIGH Current  
Min  
0.8  
5
V
Max  
Max  
Max  
Max  
Max  
Max  
Max  
Max  
0.0  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
V
V
V
V
V
V
V
V
V
IN = 2.7V (Note 3)  
IN = VCC  
All Others  
TMS, TDI  
5
5
IN = VCC  
IBVI  
IBVIT  
IIL  
Input HIGH Current Breakdown Test  
7
IN = 7.0V  
Input HIGH Current Breakdown Test (I/O)  
100  
−5  
−5  
−385  
IN = 5.5V  
Input LOW Current  
All Others  
IN = 0.5V (Note 3)  
IN = 0.0V  
TMS, TDI  
IN = 0.0V  
VID  
Input Leakage Test  
4.75  
I
ID = 1.9 µA  
All Other Pins Grounded  
I
I
IH + IOZH  
IL + LOZL  
Output Leakage Current  
Output Leakage Current  
Output Leakage Current  
Output Leakage Current  
Output Short-Circuit Current  
Output HIGH Leakage Current  
Bus Drainage Test  
Max  
Max  
Max  
Max  
Max  
Max  
0.0  
50  
−50  
50  
µA  
µA  
µA  
µA  
mA  
µA  
µA  
V
V
V
V
V
V
V
OUT = 2.7V  
OUT = 0.5V  
OUT = 2.7V  
OUT = 0.5V  
OUT = 0.0V  
OUT = VCC  
OUT = 5.5V  
IOZH  
IOZL  
IOS  
−50  
−275  
50  
−100  
ICEX  
IZZ  
100  
All Others Grounded  
www.fairchildsemi.com  
8
DC Electrical Characteristics (Continued)  
VCC  
Symbol  
ICCH  
Parameter  
Power Supply Current  
Min  
Typ  
Max  
250  
1.0  
65  
Units  
µA  
Conditions  
Max  
Max  
Max  
Max  
Max  
Max  
Max  
Max  
Max  
V
V
V
V
OUT = VCC; TDI, TMS = VCC  
OUT = VCC; TDI, TMS = GND  
OUT = LOW; TDI, TMS = VCC  
OUT = LOW; TDI, TMS = GND  
mA  
mA  
mA  
µA  
ICCL  
ICCZ  
ICCT  
ICCD  
Power Supply Current  
Power Supply Current  
Additional ICC/Input  
Dynamic ICC  
65.8  
250  
1.0  
2.9  
3
TDI, TMS = VCC  
TDI, TMS = GND  
mA  
mA  
mA  
mA/  
MHz  
All Other Inputs  
TDI, TMS Inputs  
No Load  
V
IN = VCC − 2.1V  
IN = VCC − 2.1V  
V
0.2  
Outputs Open  
One Bit Toggling, 50% Duty Cycle  
Note 3: Guaranteed not tested.  
AC Electrical Characteristics  
Normal Operation:  
VCC  
(V)  
TA = −40°C to +85°C  
Symbol  
Parameter  
CL = 50 pF  
Units  
(Note 4)  
Min  
1.0  
1.9  
2.0  
1.9  
2.4  
1.6  
3.2  
4.5  
2.5  
3.7  
4.9  
3.1  
3.7  
4.9  
4.2  
5.3  
5.0  
6.2  
3.7  
4.3  
3.7  
4.3  
4.7  
5.5  
5.5  
4.0  
5.8  
4.3  
6.6  
4.9  
Typ  
3.4  
4.1  
5.2  
5.6  
6.1  
5.1  
6.0  
7.6  
5.8  
7.4  
8.6  
6.7  
6.7  
8.3  
7.9  
9.2  
9.4  
10.9  
7.9  
8.7  
8.5  
9.4  
10.1  
10.9  
9.8  
7.9  
10.9  
9.0  
12.5  
10.5  
Max  
5.2  
tPLH  
Propagation Delay  
Data to Q  
5.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPHL  
tPLZ  
tPHZ  
tPZL  
tPZH  
tPLH  
tPHL  
tPLZ  
tPHZ  
tPZL  
tPZH  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPLZ  
tPHZ  
tPLZ  
tPHZ  
tPLZ  
tPHZ  
tPZL  
tPZH  
tPZL  
tPZH  
tPZL  
tPZH  
6.5  
Disable Time  
5.0  
5.0  
5.0  
5.0  
5.0  
8.7  
9.2  
Enable Time  
9.6  
8.5  
Propagation Delay  
TCK to TDO  
9.4  
11.3  
9.9  
Disable Time  
TCK to TDO  
11.8  
12.9  
10.7  
10.3  
12.4  
12.2  
13.8  
14.6  
16.4  
13.0  
13.7  
14.2  
14.8  
16.6  
17.3  
14.7  
12.5  
16.5  
14.4  
19.1  
16.9  
Enable Time  
TCK to TDO  
Propagation Delay  
TCK to Data Out during Update-DR State  
Propagation Delay  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
TCK to Data Out during Update-IR State  
Propagation Delay  
TCK to Data Out during Test Logic Reset State  
Disable Time  
TCK to Data Out during Update-DR State  
Disable Time  
TCK to Data Out during Update-IR State  
Disable Time  
TCK to Data Out during Test Logic Reset State  
Enable Time  
TCK to Data Out during Update-DR State  
Enable Time  
TCK to Data Out during Update-IR State  
Enable Time  
TCK to Data Out during Test Logic Reset State  
Note 4: Voltage Range 5.0V ± 0.5V  
9
www.fairchildsemi.com  
AC Operating Requirements  
Scan Test Operation:  
VCC  
T
A = −40°C to +85°C  
L = 50 pF  
Symbol  
Parameter  
C
Units  
(V)  
(Note 5)  
Guaranteed Minimum  
tS  
Setup Time  
5.0  
5.0  
5.0  
5.0  
2.2  
ns  
ns  
ns  
ns  
Data to TCK (Note 6)  
Hold Time  
tH  
tS  
tH  
tS  
1.8  
3.7  
1.8  
Data to TCK (Note 6)  
Setup Time, H or L  
AOEn, BOEn to TCK (Note 7)  
Hold Time, H or L  
TCK to AOEn, BOEn (Note 7)  
Setup Time, H or L  
Internal AOEn, BOEn,  
to TCK (Note 8)  
5.0  
5.0  
2.7  
1.8  
ns  
ns  
tH  
Hold Time, H or L  
TCK to Internal  
AOEn, BOEn (Note 8)  
Setup Time, H or L  
TMS to TCK  
tS  
tH  
tS  
tH  
tW  
5.0  
5.0  
5.0  
7.5  
1.8  
5.0  
2.0  
ns  
ns  
ns  
ns  
ns  
Hold Time, H or L  
TCK to TMS  
Setup Time, H or L  
TDI to TCK  
Hold Time, H or L  
TCK to TDI  
5.0  
5.0  
Pulse Width TCK  
H
10.0  
10.8  
50  
L
fMAX  
tPU  
Maximum TCK Clock Frequency  
Wait Time, Power Up to TCK  
Power Down Delay  
5.0  
5.0  
0.0  
MHz  
ns  
100  
100  
tDN  
ms  
Note 5: Voltage Range 5.0V ± 0.5V  
Note 6: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35.  
Note 7: Timing pertains to BSR 38 and 41 or BSR 37 and 40.  
Note 8: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.  
Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK.  
Capacitance  
Conditions, TA = 25°C  
Symbol  
CIN  
COUT  
Parameter  
Typ  
5.8  
Units  
pF  
Input Capacitance  
Output Capacitance (Note 9)  
V
V
CC = 0.0V  
CC = 5.0V  
13.8  
pF  
Note 9: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.  
www.fairchildsemi.com  
10  
Physical Dimensions inches (millimeters) unless otherwise noted  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide  
Package Number MS56A  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
11  
www.fairchildsemi.com  

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