RLD03N06CLE_技术文档

RLD03N06CLE,

RLD03N06CLESM, RLP03N06CLE

S E M I C O N D U C T O R

0.3A, 60V, ESD Rated, Current Limited, Voltage Clamped

Logic Level N-Channel Enhancement-Mode Power MOSFETs

July 1996

Features

Packages

JEDEC TO-220AB

• 0.30A, 60V

SOURCE

DRAIN

GATE

• r_DS(ON)= 6.0Ω

• Built in Current Limit I_LIMIT0.140 to 0.210A at 150^oC

• Built in Voltage Clamp

• Temperature Compensating PSPICE Model

• 2kV ESD Protected

DRAIN

(FLANGE)

• Controlled Switching Limits EMI and RFI

JEDEC TO-251AA

Description

SOURCE

DRAIN

GATE

The RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE

are intelligent monolithic power circuits which incorporate a lat-

eral bipolar transistor, resistors, zener diodes and a power MOS

transistor. The current limiting of these devices allow it to be used

safely in circuits where a shorted load condition may be encoun-

tered. The drain-source voltage clamping offers precision control

of the circuit voltage when switching inductive loads. The “Logic

Level” gate allows this device to be fully biased on with only 5.0V

from gate to source, thereby facilitating true on-off power control

directly from logic level (5V) integrated circuits.

DRAIN

(FLANGE)

JEDEC TO-252AA

DRAIN

(FLANGE)

GATE

SOURCE

The RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE

incorporate ESD protection and are designed to withstand 2kV

(Human Body Model) of ESD.

Symbol

D

PACKAGING AVAILABILITY

PART NUMBER

PACKAGE

TO-251AA

BRAND

03N06C

RLD03N06CLE

G

RLD03N06CLESM TO-252AA

RLP03N06CLE TO-220AB

03N06C

03N06CLE

NOTE: When ordering, use the entire part number. Add the sufﬁx 9A

to obtain the TO-252AA variant in tape and reel, i.e.

RLD03N06CLESM9A.

S

Formerly developmental type TA49026.

o

Absolute Maximum Ratings T = +25 C

C

RLD03N06CLE,

RLD03N06CLESM,

RLP03N06CLE

UNITS

Drain Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

60

V

DSS

Drain Gate Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DGR

Gate Source Voltage (Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Reverse Voltage Gate Bias Not Allowed

+5.5

GS

Drain Current

RMS Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Self Limited

D

Power Dissipation

o

T

= +25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

30

0.2

W

C

o

Derate above +25 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

W/ C

T

Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . . . . . . . . ESD

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T

2

KV

o

-55 to +175

C

STG

J

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures.

File Number 3948.3

1

Speciﬁcations RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE

o

Electrical Speciﬁcations T = +25 C, Unless Otherwise Speciﬁed

C

PARAMETERS

Drain-Source Breakdown Voltage

Gate Threshold Voltage

SYMBOL

BV

TEST CONDITIONS

= 250µA, V = 0V

MIN

TYP

MAX

85

UNITS

V

I

60

-

DSS

D

GS

V

= V , I = 250µA

1

-

2.5

50

V

GS(TH)

GS

DS

D

o

Zero Gate Voltage Drain Current

I

V

= 45V,

= 0V

T = +25 C

-

µA

Ω

DSS

GSS

DS

GS

J

o

T = +150 C

-

200

5

J

o

Gate-Source Leakage Current

On Resistance

I

V

= 5V

T = +25 C

-

GS

J

o

T = +150 C

-

20

J

o

r

I

= 0.100A,

T = +25 C

-

6.0

12.0

420

210

7.5

2.5

5.0

7.5

5.0

12.5

-

DS(ON)

D

J

V

= 5V

GS

o

T = +150 C

-

Ω

J

o

Limiting Current

I

V

= 15V,

= 5V

T = +25 C

280

-

mA

µs

DS(LIMIT)

DS

GS

J

o

T = +150 C

140

-

J

Turn-On Time

t

V

= 30V, I = 0.10A,

-

ON

DD

D

R = 300Ω, V = 5V,

R

L

GS

Turn-On Delay Time

Rise Time

t

= 25Ω

-

µs

D(ON)

GS

t

-

µs

R

Turn-Off Delay Time

Fall Time

t

-

µs

D(OFF)

t

-

µs

F

Turn-Off Time

t

µs

OFF

Input Capacitance

C

V

= 25V, V = 0V,

100

65

3.0

-

pF

ISS

DS

GS

f = 1MHz

Output Capacitance

Reverse Transfer Capacitance

Thermal Resistance Junction to Case

Thermal Resistance Junction to Ambient

C

-

OSS

RSS

-

o

R

5.0

80

C/W

JC

JA

θ

o

R

TO-220 Package

-

C/W

θ

o

TO-251 and TO-252 Packages

-

100

C/W

Source-Drain Diode Ratings and Speciﬁcations

PARAMETERS

Forward Voltage

Reverse Recovery Time

SYMBOL

TEST CONDITIONS

= 0.1A

MIN

TYP

MAX

1.5

UNITS

V

I

-

SD

RR

SD

t

= 0.1A, dI /dt = 100A/µs

1.0

ms

SD

2

RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE

Typical Performance Curves

T_C= +25^oC

1

10

OPERATION IN THIS

AREA IS LIMITED BY

JUNCTION TEMPERATURE

1

0.5

0.2

25^oC

P_DM

DC

0.1

0.05

175^oC

0.1

OPERATION IN THIS

AREA MAY BE

LIMITED BY r_DS(ON)

0.02

t₁

0.01

t₂

SINGLE PULSE

NOTES:

DUTY FACTOR: D = t₁/t₂

PEAK T_J= P_DMx Z _JC+ T_C

θ

0.1

0.01

10^-5

10^-4

10^-3

10^-2

10^-1

10⁰

10¹

1

10

100

V_DS, DRAIN-TO-SOURCE VOLTAGE (V)

t, RECTANGULAR PULSE DURATION (s)

FIGURE 1. SAFE OPERATING AREA CURVE

FIGURE 2. NORMALIZED MAXIMUM TRANSIENT THERMAL

IMPEDANCE

2.0

1.5

1.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

0.5

0

-80

-40

0

40

80

120

160

200

0

25

50

75

100

125

150

175

T_J, JUNCTION TEMPERATURE (^oC)

T_C, CASE TEMPERATURE (^oC)

FIGURE 3. TYPICAL NORMALIZED DRAIN CURRENT vs

JUNCTION TEMPERATURE

FIGURE 4. NORMALIZED POWER DISSIPATION vs

TEMPERATURE DERATING CURVE

PULSE DURATION = 250µs, T_C= +25^oC

V_DD= 15V

-55^oC

0.60

0.50

0.40

0.30

0.20

0.10

V_GS= 5V

V_GS= 7.5V

PULSE TEST

V_GS= 4V

PULSE DURATION = 250µs

DUTY CYCLE = 0.5% MAX

0.40

0.30

V_GS= 3V

+25^oC

0.20

0.10

0

+175^oC

0

0.0

1.0

2.0

3.0

4.0

5.0

0

1.0

2.0

3.0

4.0

5.0

V_DS, DRAIN-TO-SOURCE VOLTAGE (V)

V_GS, GATE-TO-SOURCE VOLTAGE (V)

FIGURE 5. TYPICAL SATURATION CHARACTERISTICS

FIGURE 6. TYPICAL TRANSFER CHARACTERISTICS

3

RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE

Typical Performance Curves (Continued)

I_D= 250µA

V_GS= V_DS

,

I_D= 0.30A

PULSE DURATION = 250µs, V_GS= 5V,

2.0

1.5

2.5

2.0

1.5

1.0

0.5

0.0

0.5

0.0

-80

-40

0

40

80

120

160

200

-80

-40

0

40

80

120

160

200

T_J, JUNCTION TEMPERATURE (^oC)

FIGURE 7. NORMALIZED r

vs JUNCTION TEMPERATURE

FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs

TEMPERATURE

DS(ON)

T_C= +25^oC

I_D= 20mA

1

2.0

1.5

TEMPERATURES LISTED ARE STARTING

JUNCTION TEMPERATURES

+25^oC

+50^oC

1.0

+75^oC

+100^oC

0.5

0.0

+150^oC

+125^oC

10

0.1

0.001

-80

-40

0

40

80

120

160

200

0.01

0.1

1

T_J, JUNCTION TEMPERATURE (^oC)

t_AV, TIME IN CLAMP (s)

FIGURE 9. NORMALIZED DRAIN SOURCE BREAKDOWN

VOLTAGE vs TEMPERATURE

FIGURE 10. SELF-CLAMPED INDUCTIVE SWITCHING

V_GS= 0V, FREQUENCY (f) = 1MHz

5.00

60

300

45

30

15

0

3.75

2.50

1.25

0.00

V_DD= BV_DSS

200

100

R_L= 600Ω

0.75 BV_DSS

I_G(REF)= 0.1mA

C_ISS

V_GS= 5V

0.50 BV_DSS

0.25 BV_DSS

C_OSS

C_RSS

I

0

G(REF)

0

5

10

15

20

25

---------------------

10

t, TIME (µs)

---------------------

40

I

G(ACT)

V_DS, DRAIN-TO-SOURCE VOLTAGE (V)

FIGURE 11. TYPICAL CAPACITANCE vs DRAIN-TO-SOURCE

VOLTAGE

FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR

CONSTANT GATE CURRENT. REFER TO HARRIS

APPLICATION NOTES AN7254 AND AN7260

4

RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE

Test Circuit and Waveform

V_DD

t_ON

t_D(ON)

t_OFF

t_D(OFF)

t_R

t_F

R_L

V_DS

90%

V_GS

10%

DUT

90%

50%

0V

50%

V_GS

10%

PULSE WIDTH

R_GS

FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT

FIGURE 14. RESISTIVE SWITCHING WAVEFORMS

Detailed Description

Duty Cycle Operation

Temperature Dependence of Current Limiting and

Switching Speed Performance

In many applications either the drain to source voltage or the

gate drive is not available 100% of the time. The copper

header on which the RLD03N06CLE, RLD03N06CLESM

and RLP03N06CLE is mounted has a very large thermal

storage capability, so for pulse widths of less then 1ms, the

temperature of the header can be considered a constant,

thereby the junction temperature can be calculated simply as

shown in Equation 2:

The RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE

are a monolithic power device which incorporates a Logic Level

power MOSFET transistor with a current sensing scheme and

control circuitry to enable the device to self limit the drain

source current ﬂow. The current sensing scheme supplies cur-

rent to a resistor that is connected across the base to emitter of

a bipolar transistor in the control section. The collector of this

bipolar transistor is connected to the gate of the power MOS-

FET transistor. When the ratiometric current from the current

sensing reaches the value required to forward bias the base

emitter junction of this bipolar transistor, the bipolar “turns on”.

A resistor is incorporated in series with the gate of the power

MOSFET transistor allowing the bipolar transistor to adjust the

drive on the gate of the power MOSFET transistor to a voltage

which then maintains a constant current in the power MOSFET

transistor. Since both the ratiometric current sensing scheme

and the base emitter unction voltage of the bipolar transistor

vary with temperature, the current at which the device limits is a

function of temperature. This dependence is shown in Figure 3.

(EQ. 2)

T

= (V

• I • D • R

) + T

θCA A MBIENT

C

DS

D

Generally the heat storage capability of the silicon chip in a

power transistor is ignored for duty cycle calculations. Mak-

ing this assumption, limiting junction temperature to 175^oC

and using the T_Ccalculated in Equation 2, the expression for

maximum V_DSunder duty cycle operation is shown in Equa-

tion 3:

o

150 C – T

C

V

=

(EQ. 3)

-----------------------------------------

DS

I

• D • R

LM

θJC

These values are plotted as Figures 16 through 21 for vari-

ous heatsink thermal resistances.

The resistor in series with the gate of the power MOSFET

transistor also results in much slower switching performance

than in standard power MOSFET transistors. This is an Limited Time Operations

advantage where fast switching can cause EMI or RFI. The

switching speed is very predictable.

Protection for a limited period of time is sufﬁcient for many

applications. As stated above the heat storage in the silicon

chip can usually be ignored for computations of over 10 ms,

thereby the thermal equivalent circuit reduces to a simple

enough circuit to allow easy computation on the limiting con-

ditions. The variation in limiting current with temperature

complicates the calculation of junction temperature, but a

simple straight line approximation of the variation is accurate

enough to allow meaningful computations. The curves

shown as Figures 22 through 25 (RLP03N06CLE) and Fig-

ure 26 through 29 (RLD03N06CLE and RLD03N06CLESM)

give an accurate indication of how long the speciﬁed voltage

can be applied to the device in the current limiting mode

without exceeding the maximum speciﬁed 175^oC junction

temperature. In practice this tells you how long you have to

DC Operation

The limit on the drain to source voltage for operation in cur-

rent limiting on a steady state (DC) basis is shown in the

equation below. The dissipation in the device is simply the

applied drain to source voltage multiplied by the limiting cur-

rent. This device, like most power MOSFET devices today, is

limited to 175^oC. The maximum voltage allowable can,

therefore, be expressed as shown in Equation 1:

(150°C–T

)

A MBIENT

V

=

-------------------------------------------------------

DS

(EQ. 1)

I

LM • (R

+ R

)

θJC

θJA

The results of this equation are plotted in Figure 15 for vari- alleviate the condition causing the current limiting to occur.

ous heatsinks.

5

RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE

Performance Curves

HEAT SINK THERMAL RESISTANCE = HSTR

DUTY CYCLE = DC MAX PULSE WIDTH = 100ms

90

HSTR = 0^oC/W

HSTR = 1^oC/W

HSTR = 2^oC/W

DC = 20%

DC = 50%

DC = 2%

DC = 5%

75

60

45

30

15

0

75

60

45

30

15

0

HSTR = 5^oC/W

HSTR = 10^oC/W

T_J= 175^oC

DC = 10%

I

R

_LIM= 0.210A

_JC= 5.0^oC/W

θ

HSTR = 25^oC/W

HSTR = 80^oC/W

T_J= 175^oC

I

R

_LIM= 0.210A

_JC= 5.0^oC/W

θ

25

50

75

100

125

150

175

100

125

150

175

T_A, AMBIENT TEMPERATURE (^oC)

FIGURE 15. DC OPERATION IN CURRENT LIMITING

FIGURE 16. MAXIMUM V vs AMBIENT TEMPERATURE IN

DS

CURRENT LIMITING. (HEATSINK THERMAL

o

RESISTANCE = 1 C/W)

DUTY CYCLE = DC MAX PULSE WIDTH = 100ms

90

DUTY CYCLE = DC MAX PULSE WIDTH = 100ms

90

DC = 20%

DC = 2%

75

60

45

30

15

0

DC = 20%

DC = 5%

DC = 50%

60

DC = 10%

DC = 50%

45

30

T_J= 175^oC

I

R

_LIM= 0.210A

15

0

I

R

_LIM= 0.210A

_JC= 5.0^oC/W

θ

75

100

125

150

175

100

125

150

175

T_A, AMBIENT TEMPERATURE (^oC)

FIGURE 17. MAXIMUM V vs AMBIENT TEMPERATURE IN

FIGURE 18. MAXIMUM V vs AMBIENT TEMPERATURE IN

DS

o

CURRENT LIMITING. (HSTR = 2 C/W)

CURRENT LIMITING. (HSTR = 5 C/W)

DUTY CYCLE = DC MAX PULSE WIDTH = 100ms

90

DUTY CYCLE = DC MAX PULSE WIDTH = 100ms

90

DC = 20%

DC = 2%

DC = 10%

DC = 2%

DC = 5%

DC = 20%

75

60

45

30

15

0

DC = 5%

DC = 50%

60

45

30

15

0

DC = 10%

DC = 50%

T_J= 175^oC

I

R

_LIM= 0.210A

_JC= 5.0^oC/W

I_LIM= 0.210A

θ

R

_JC= 5.0^oC/W

θ

25

50

75

100

125

150

175

25

50

75

100

125

150

175

T_A, AMBIENT TEMPERATURE (^oC)

FIGURE 19. MAXIMUM V vs AMBIENT TEMPERATURE IN

FIGURE 20. MAXIMUM V vs AMBIENT TEMPERATURE IN

DS

o

CURRENT LIMITING. (HSTR = 10 C/W)

CURRENT LIMITING. (HSTR = 25 C/W)

6

RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE

Performance Curves (Continued)

DUTY CYCLE = DC MAX PULSE WIDTH = 100ms

10

8

90

DC = 1%

DC = 2%

DC = 5%

DC = 10%

STARTING T_J= 75^oC

STARTING T_J= 100^oC

STARTING T_J= 125^oC

STARTING T_J= 150^oC

75

60

45

30

15

0

T_J= 175^oC

I_LIM= 0.210A

R

_JC= 5.0^oC/W

θ

6

4

2

0

DC = 20%

DC = 50%

25

50

75

100

125

150

175

10

30

50

70

90

T_A, AMBIENT TEMPERATURE (^oC)

V_DS, DRAIN TO SOURCE VOLTAGE (V)

o

FIGURE 21. MAXIMUM V vs AMBIENT TEMPERATURE IN

FIGURE 22. TIME TO 175 C IN CURRENT LIMITING

DS

o

CURRENT LIMITING. (HSTR = 80 C/W)

(HEATSINK THERMAL RESISTANCE = 25 C/W)

(HEATSINK THERMAL CAPACITANCE = 0.5J/ C)

o

10

8

STARTING T_J= 75^oC

STARTING T_J= 100^oC

8

STARTING T_J= 125^oC

STARTING T_J= 150^oC

STARTING T_J= 75^oC

6

4

2

0

6

4

2

0

STARTING T_J= 100^oC

STARTING T_J= 125^oC

STARTING T_J= 150^oC

10

30

50

70

90

10

30

50

70

90

V_DS, DRAIN TO SOURCE VOLTAGE (V)

o

V_DS, DRAIN TO SOURCE VOLTAGE (V)

o

FIGURE 23. TIME TO 175 C IN CURRENT LIMITING

FIGURE 24. TIME TO 175 C IN CURRENT LIMITING

o

(HEATSINK THERMAL RESISTANCE = 10 C/W)

(HEATSINK THERMAL CAPACITANCE = 1.0J/ C)

(HEATSINK THERMAL RESISTANCE = 5 C/W)

(HEATSINK THERMAL CAPACITANCE = 2.0J/ C)

o

10

8

10

8

STARTING T_J= 75^oC

STARTING T_J= 100^oC

STARTING T_J= 125^oC

STARTING T_J= 150^oC

STARTING T_J= 100^oC

6

4

2

0

6

4

2

0

STARTING T_J= 125^oC

STARTING T_J= 150^oC

10

30

50

70

90

10

30

50

70

90

V_DS, DRAIN TO SOURCE VOLTAGE (V)

o

V_DS, DRAIN TO SOURCE VOLTAGE (V)

o

FIGURE 25. TIME TO 175 C IN CURRENT LIMITING

FIGURE 26. TIME TO 175 C IN CURRENT LIMITING

o

(HEATSINK THERMAL RESISTANCE = 2 C/W)

(HEATSINK THERMAL CAPACITANCE = 4J/ C)

(HEATSINK THERMAL RESISTANCE = 25 C/W)

(HEATSINK THERMAL CAPACITANCE = 0.5J/ C)

o

7

RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE

Performance Curves (Continued)

10

8

10

8

STARTING T_J= 75^oC

STARTING T_J= 100^oC

STARTING T_J= 125^oC

STARTING T_J= 150^oC

STARTING T_J= 75^oC

6

4

2

0

6

4

2

0

STARTING T_J= 100^oC

STARTING T_J= 125^oC

STARTING T_J= 150^oC

10

30

50

70

90

10

30

50

70

90

V_DS, DRAIN TO SOURCE VOLTAGE (V)

o

V_DS, DRAIN TO SOURCE VOLTAGE (V)

o

FIGURE 27. TIME TO 175 C IN CURRENT LIMITING

FIGURE 28. TIME TO 175 C IN CURRENT LIMITING

o

(HEATSINK THERMAL RESISTANCE = 10 C/W)

(HEATSINK THERMAL CAPACITANCE = 1.0J/ C)

(HEATSINK THERMAL RESISTANCE = 5 C/W)

(HEATSINK THERMAL CAPACITANCE = 2.0J/ C)

o

10

STARTING T_J= 75^oC

8

6

4

STARTING T_J= 100^oC

STARTING T_J= 125^oC

2

0

STARTING T_J= 150^oC

10

30

50

70

90

V_DS, DRAIN TO SOURCE VOLTAGE (V)

o

FIGURE 29. TIME TO 175 C IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 2 C/W)

o

(HEATSINK THERMAL CAPACITANCE = 4J/ C)

8

RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE

Temperature Compensated PSPICE Model for the RLD03N06CLE, RLD03N06CLESM,

RLP03N06CLE

SUBCKT RLD03N06CLE 2 1 3;

CA 12 8 0.547e-9

CB 15 14 0.547e-9

rev 4/18/94

5

DRAIN

2

LDRAIN

CIN 6 8 0.301e-9

DBREAK

DPLCAP

DBODY 7 5 DBDMOD

10

DBREAK 5 11 DBKMOD

DESD1 91 9 DESD1MOD

DESD2 91 7 DESD2MOD

DPLCAP 10 5 DPLCAPMOD

11

+

ESG

RDRAIN

DBODY

6

8

17

18

EBREAK

16

EBREAK 11 20 17 18 66.5

EDS 14 8 5 8 1

EGS 13 8 6 8 1

ESG 6 10 6 8 1

EVTO 20 6 18 8 1

+

VTO

-

+

MOS2

EVTO

+

21

GATE

1

RGATE

18

8

MOS1

6

9

LGATE

DESD1

C_IN

R_IN

IT 8 17 1

91

LSOURCE

DESD2

RSOURCE1 RSOURCE2

70

8

LDRAIN 2 5 1e-9

LGATE 1 9 2.96e-9

LSOURCE 3 7 2.96e-9

3

7

SOURCE

S1A

S2A

MOS1 16 6 8 8 MOSMOD M = 0.99

MOS2 16 21 8 8 MOSMOD M = 0.01

RBREAK

12

14

13

15

13

8

18

RVTO

17

S1B

CA

S2B

QCONTROL 20 70 7 QMOD 1

13

RBREAK 17 18 RBKMOD 1

RDRAIN 5 16 RDSMOD 1.123

RGATE 9 20 3200

19

CB

IT

+

14

VBAT

6

8

5

8

EDS

EGS

+

RIN 6 8 1e9

RSOURCE1 8 70 RDSMOD 1.12

RSOURCE2 70 7 RSMOD 2.16

RVTO 18 19 RVTOMOD 1

S1A 6 12 13 8 S1AMOD

S1B 13 12 13 8 S1BMOD

S2A 6 15 14 13 S2AMOD

S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1

VTO 21 6 0.22

.MODEL DBDMOD D (IS = 7.97e-17 RS = 1.82 TRS1 = 3.91e-3 TRS2 = 1.24e-5 CJO = 3.00e-10 TT = 1.83e-7)

.MODEL DBKMOD D (RS = 3150 TRS1 =0 TRS2 = 0)

.MODEL DESD1MOD D (BV = 13.54 TBV1 = 0 TBV2 = 0 RS = 45.5 TRS1 = 0 TRS2 = 0)

.MODEL DESD2MOD D (BV = 11.46 TBV1 = -7.576e-4 TBV2 = -3.0e-6 RS = 0 TRS1 = 0 TRS2 = 0)

.MODEL DPLCAPMOD D (CJO = 74.2e-12 IS = 1e-30 N = 10)

.MODEL MOSMOD NMOS (VTO = 1.67 KP = 3.40 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)

.MODEL QMOD NPN (BF =5)

.MODEL RBKMOD RES (TC1 = 4e-4 TC2 = 1.13e-8)

.MODEL RDSMOD RES (TC1 = 6.80e-3 TC2 = 6.5e-6)

.MODEL RSMOD RES (TC1 = 2.95e-3 TC2 = -1e-6)

.MODEL RVTOMOD RES (TC1 = -2.22e-3 TC2 = -1.95e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF = -1)

.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1 VOFF = -3)

.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.85 VOFF = 2.15)

.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.15 VOFF = -2.85)

.ENDS

NOTE:

1. For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records 1991.

9

RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE

TO-220AB

3 LEAD JEDEC TO-220AB PLASTIC PACKAGE

A

INCHES

MIN

MILLIMETERS

E

ØP

SYMBOL

MAX

0.180

0.052

0.034

0.055

0.019

0.610

0.160

0.410

0.030

MIN

4.32

1.22

0.77

1.15

0.36

14.99

-

MAX

4.57

NOTES

A₁

A

0.170

0.048

0.030

0.045

0.014

0.590

-

Q

H₁

A

1.32

-

1

b

0.86

3, 4

TERM. 4

D

b

1.39

2, 3

1

45^o

E₁

c

0.48

2, 3, 4

D₁

D

15.49

4.06

-

L₁

D

1

b₁

E

0.395

-

10.04

-

10.41

0.76

-

L

b

E

-

c

1

e

0.100 TYP

0.200 BSC

0.235

2.54 TYP

5.08 BSC

5

-

60^o

e

1

2

e

3

1

J₁

H

0.255

0.110

0.550

0.150

0.153

0.112

5.97

6.47

2.79

13.97

3.81

3.88

2.84

1

e₁

J

0.100

0.530

0.130

0.149

0.102

2.54

13.47

3.31

6

-

1

L

LEAD NO. 1

LEAD NO. 2

LEAD NO. 3

TERM. 4

-

GATE

L

2

-

1

DRAIN

ØP

Q

3.79

SOURCE

DRAIN

2.60

-

NOTES:

1. These dimensions are within allowable dimensions of Rev. J of

JEDEC TO-220AB outline dated 3-24-87.

2. Lead dimension and finish uncontrolled in L .

1

3. Lead dimension (without solder).

4. Add typically 0.002 inches (0.05mm) for solder coating.

5. Position of lead to be measured 0.250 inches (6.35mm) from bot-

tom of dimension D.

6. Position of lead to be measured 0.100 inches (2.54mm) from bot-

tom of dimension D.

7. Controlling dimension: Inch.

8. Revision 1 dated 1-93.

10

RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE

TO-251AA

3 LEAD JEDEC TO-251AA PLASTIC PACKAGE

E

A

INCHES

MIN

MILLIMETERS

SYMBOL

MAX

0.094

0.022

0.032

0.040

0.215

0.022

0.290

0.265

MIN

2.19

0.46

0.72

0.84

5.21

0.46

6.86

6.35

MAX

2.38

0.55

0.81

1.01

5.46

0.55

7.36

6.73

NOTES

b₂

A₁

TERM. 4

H₁

A

0.086

0.018

0.028

0.033

0.205

0.018

0.270

0.250

-

A

3, 4

SEATING

PLANE

1

D

b

3, 4

b

3

1

2

3, 4

c

3, 4

b₁

D

E

e

-

L₁

L

c

b

0.090 TYP

0.180 BSC

2.28 TYP

4.57 BSC

5

-

e

1

2

3

H

0.035

0.045

0.375

0.090

0.89

1.14

9.52

2.28

1

J₁

e

J

0.040

0.355

0.075

1.02

9.02

1.91

6

-

1

e₁

L

2

1

NOTES:

LEAD NO. 1

LEAD NO. 2

LEAD NO. 3

TERM. 4

-

GATE

1. These dimensions are within allowable dimensions of Rev. C of

JEDEC TO-251AA outline dated 9-88.

DRAIN

SOURCE

DRAIN

2. Solder finish uncontrolled in this area.

3. Dimension (without solder).

4. Add typically 0.002 inches (0.05mm) for solder plating.

5. Position of lead to be measured 0.250 inches (6.35mm) from bot-

tom of dimension D.

6. Position of lead to be measured 0.100 inches (2.54mm) from bot-

tom of dimension D.

7. Controlling dimension: Inch.

8. Revision 2 dated 10-95.

11

RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE

TO-252AA

SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE

INCHES

MIN

MILLIMETERS

A

E

A₁

SYMBOL

MAX

0.094

0.022

0.032

0.040

0.215

-

MIN

2.19

0.46

0.72

0.84

5.21

4.83

0.46

6.86

6.35

MAX

2.38

0.55

0.81

1.01

5.46

-

NOTES

H₁

b₂

A

0.086

0.018

0.028

0.033

0.205

0.190

0.018

0.270

0.250

-

SEATING

PLANE

A

4, 5

1

b

4, 5

D

b

4

1

2

3

L

2

4, 5

2

L

1

3

c

0.022

0.290

0.265

0.55

7.36

6.73

4, 5

b₁

b

D

E

e

-

L₁

e

c

e₁

J₁

0.090 TYP

0.180 BSC

2.28 TYP

4.57 BSC

7

-

0.265

(6.7)

e

1

TERM. 4

H

0.035

0.045

0.115

-

0.89

1.14

2.92

-

1

J

0.040

0.100

0.020

0.025

0.170

1.02

2.54

0.51

0.64

4.32

-

1

L

-

L₃

0.265 (6.7)

b₃

L

4, 6

3

2

1

2

3

0.040

-

1.01

-

0.070 (1.8)

NOTES:

0.118 (3.0)

1. These dimensions are within allowable dimensions of Rev. B of

JEDEC TO-252AA outline dated 9-88.

BACK VIEW

2. L and b dimensions establish a minimum mounting surface for

3

0.063 (1.6)

0.090 (2.3)

0.063 (1.6)

0.090 (2.3)

terminal 4.

3. Solder finish uncontrolled in this area.

4. Dimension (without solder).

MINIMUM PAD SIZE RECOMMENDED FOR

SURFACE-MOUNTED APPLICATIONS

5. Add typically 0.002 inches (0.05mm) for solder plating.

6. L is the terminal length for soldering.

1

7. Position of lead to be measured 0.090 inches (2.28mm) from bottom

of dimension D.

LEAD NO. 1

LEAD NO. 3

TERM. 4

-

GATE

SOURCE

DRAIN

8. Controlling dimension: Inch.

9. Revision 5 dated 10-95.

12

RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE

TO-252AA

16mm TAPE AND REEL

22.4mm

13mm

4.0mm

1.5mm

DIA. HOLE

2.0mm

1.75mm

C

L

16mm

50mm

330mm

8.0mm

16.4mm

USER DIRECTION OF FEED

GENERAL INFORMATION

1. USE "9A" SUFFIX ON PART NUMBER.

2. 2500 PIECES PER REEL.

COVER TAPE

3. ORDER IN MULTIPLES OF FULL REELS ONLY.

4. MEETS EIA-481 REVISION "A" SPECIFICATIONS.

Revision 5 dated 10-95

Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or speciﬁcations at

any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is

believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other

rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.

Sales Ofﬁce Headquarters

For general information regarding Harris Semiconductor and its products, call 1-800-4-HARRIS

UNITED STATES

EUROPE

SOUTH ASIA

NORTH ASIA

Harris Semiconductor

P. O. Box 883, Mail Stop 53-210 Mercure Center

Melbourne, FL 32902

TEL: 1-800-442-7747

(407) 729-4984

Harris Semiconductor

Harris Semiconductor H.K. Ltd.

13/F Fourseas Building

208-212 Nathan Road

Tsimshatsui, Kowloon

Hong Kong

Harris K.K.

Kojimachi-Nakata Bldg. 4F

5-3-5 Kojimachi

Chiyoda-ku, Tokyo 102 Japan

TEL: (81) 3-3265-7571

TEL: (81) 3-3265-7572 (Sales)

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2-724-2111

FAX: (407) 729-5321

TEL: (852) 723-6339

S E M I C O N D U C T O R

13


型号：	RLD03N06CLE
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	0.3A, 60V, ESD Rated, Current Limited, Voltage Clamped Logic Level N-Channel Enhancement-Mode Power MOSFETs 0.3A ， 60V ， ESD额定电流限制，钳位电压逻辑电平N沟道增强型功率MOSFET 晶体晶体管开关
文件：	总13页 (文件大小：192K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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