NM27C040V150 [FAIRCHILD]
OTP ROM, 512KX8, 150ns, CMOS, PQCC32, PLASTIC, LCC-32;
| 型号： | NM27C040V150 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | OTP ROM, 512KX8, 150ns, CMOS, PQCC32, PLASTIC, LCC-32 OTP只读存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1997
NM27C040
4,194,304-Bit (512K x 8) High Performance CMOS
EPROM
The NM27C040 is manufactured using Fairchild’s advanced
General Description
™
CMOS AMG EPROM technology.
The NM27C040 is a high performance, 4,194,304-bit Electri-
cally Programmable UV Erasable Read Only Memory. It is
organized as 512K words of 8 bits each. Its pin-compatibility
with byte-wide JEDEC EPROMs enables upgrades through
8 Mbit EPROMs. The “Don’t Care” feature on VPP during
read operations allows memory expansions from 1M to
8 Mbits with no printed circuit board changes.
Features
n High performance CMOS
— 120 ns access time
n Simplified upgrade path
— VPP is a “Don’t Care” during normal read operation
n Manufacturer’s identification code
n JEDEC standard pin configuration
— 32-pin DIP
The NM27C040 provides microprocessor-based systems
extensive storage capacity for large portions of operating
system and application software. Its 120 ns access time pro-
vides high speed operation with high-performance CPUs.
The NM27C040 offers a single chip solution for the code
storage requirements of 100% firmware-based equipment.
Frequently used software routines are quickly executed from
EPROM storage, greatly enhancing system utility.
— 32-pin PLCC
— 32-pin TSOP
Block Diagram
DS010836-1
™
AMG is a trademark of WSI, Inc.
© 1997 Fairchild Semiconductor Corporation
DS010836
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Connection Diagrams
DS010836-2
Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C040 pin.
Commercial Temperature Range
(0˚C to +70˚C)
Extended Temperature Range
(−40˚C to +85˚C)
=
±
%
VCC 5V 10
=
±
%
VCC 5V 10
Parameter/Order Number
NM27C040 Q, V, T 120
NM27C040 Q, V, T 150
NM27C040 Q, V, T 170
NM27C040 Q, V, T 200
Access Time (ns)
Parameter/Order Number
NM27C040 QE, VE, TE 150
NM27C040 QE, VE, TE 170
NM27C040 QE, VE, TE 200
Access Time (ns)
120
150
170
200
150
170
200
Package Types: NM27C040 Q, V, T XXX
=
=
Q
V
T
Quartz-Windowed Ceramic DIP
PLCC
TSOP
Military Temperature Range (−55˚C
to +125˚C)
=
•
•
All packages conform to the JEDEC standard.
=
±
%
VCC 5V 10
All versions are guaranteed to function for slower speeds.
Parameter/Order Number
NM27C040 QM 150
Access Time (ns)
150
200
NM27C040 QM 200
Pin Names
A0–A18
CE /PGM
OE
Addresses
Chip Enable/Program
Output Enable
O0–O7
XX
Outputs
Don’t Care (During Read)
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Absolute Maximum Ratings (Note 1)
Respect to Ground
VCC +10V to GND −0.6V
Storage Temperature
−65˚C to +150˚C
All Input Voltages except A9 with
Respect to Ground
Operating Range
−0.6V to +7V
−0.6V to +14V
Range
Commercial
Industrial
Temperature
VCC
+5V
+5V
Tolerance
VPP and A9 with Respect to Ground
VCC Supply Voltage with
Respect to Ground
±
±
0˚C to +70˚C
10%
10%
−40˚C to +85˚C
−0.6V to +7V
>
ESD Protection
2000V
All Output Voltages with
Read Operation
DC Electrical Characteristics
=
Over operating range with VPP VCC
Symbol
VIL
Parameter
Input Low Level
Test Conditions
Min
−0.5
2.0
Max
Units
0.8
V
V
VIH
Input High Level
VCC + 1
0.4
=
VOL
VOH
ISB1
ISB2
ICC
Output Low Voltage
Output High Voltage
VCC Standby Current (CMOS)
VCC Standby Current
VCC Active Current
VPP Supply Current
VPP Read Voltage
IOL 2.1 mA
V
=
IOH −2.5 mA
3.5
V
=
±
CE VCC 0.3V
100
1
µA
mA
mA
µA
V
=
CE VIH
=
=
=
=
f 5 MHz
CE OE VIL, I/O 0 mA
30
10
VCC
1
=
VPP VCC
IPP
VPP
ILI
VCC − 0.4
=
Input Load Current
VIN 5.5V or GND
−1
µA
µA
=
ILO
Output Leakage Current
VOUT 5.5V or GND
−10
10
AC Electrical Characteristics
=
Over operating range with VPP VCC
Symbol
Parameter
120
150
170
200
Units
Min
Max
120
120
50
Min
Max
150
150
50
Min
Max
170
170
50
Min
Max
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
Output Disable to
200
200
50
tCE
tOE
tDF
35
35
45
55
ns
(Note 2)
tOH
Output Float
Output Hold from Addresses
CE or OE , Whichever
Occurred First
(Note 2)
0
0
0
0
Capacitance
=
=
TA +25˚C, f 1 MHz (Note 2)
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Conditions
Typ
9
Max
15
Units
pF
=
VIN 0V
=
COUT
VOUT 0V
12
15
pF
AC Test Conditions
Output Load
Input Pulse Levels
0.45V to 2.4V
Timing Measurement Reference Level (Note 10)
1 TTL Gate and
Inputs
0.8V and 2V
=
CL 100 pF (Note 8)
Outputs
0.8V and 2V
Input Rise and Fall Times
≤5 ns
3
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AC Waveforms (Notes 6, 7, 9)
DS010836-4
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional op-
eration of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to t
ACC
− t
OE
after the falling edge of CE without impacting t .
ACC
Note 4: The t and t compare level is determined as follows:
DF CF
High to TRI-STATE®, the measured V
(DC) − 0.10V;
(DC) + 0.10V.
OH1
Low to TRI-STATE, the measured V
OL1
Note 5: TRI-STATE may be attained using OE or CE .
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on
every device between V and GND.
CC
Note 7: The outputs must be restricted to V
+ 1.0V to avoid latch-up and device damage.
CC
−400 µA.
C : 100 pF includes fixture capacitance.
=
=
Note 8: 1 TTL Gate: I
1.6 mA, I
OH
OL
L
Note 9:
V
may be connected to V except during programming.
CC
PP
Note 10: Inputs and outputs can undershoot to −2.0V for 20 ns Max.
Programming Waveform (Note 13)
DS010836-5
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Programming Characteristics (Notes 11, 12, 13, 14)
Symbol
tAS
tOES
tDS
Parameter
Address Setup Time
Conditions
Min
1
Typ
Max
Units
µs
OE Setup Time
1
µs
Data Setup Time
1
µs
tVPS
tVCS
tAH
VPP Setup Time
1
µs
VCC Setup Time
1
µs
Address Hold Time
0
µs
tDH
tDF
Data Hold Time
1
µs
=
=
Output Enable to Output Float Delay
Program Pulse Width
Data Valid from OE
CE /PGM
CE /PGM
X
X
0
60
105
100
30
ns
tPW
tOE
IPP
45
50
µs
ns
=
VPP Supply Current during
Programming Pulse
CE /PGM VIL
mA
ICC
TA
VCC Supply Current
30
30
mA
˚C
V
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise, Fall Time
Input Low Voltage
20
6.25
12.5
5
25
6.5
VCC
VPP
tFR
6.75
13.0
12.75
V
ns
V
VIL
−0.1
2.4
0.8
0.8
0.0
4.0
0.45
VIH
tIN
Input High Voltage
V
Input Timing Reference Voltage
Output Timing Reference Voltage
2.0
2.0
V
tOUT
V
Note 11: Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.
Note 12: must be applied simultaneously or before V and removed simultaneously or after V . The EPROM must not be inserted into or removed from a
V
CC
PP
PP
board with voltage applied to V or V
.
PP CC
Note 13: The maximum absolute allowable voltage which may be applied to the V pin during programming is 14V. Care must be taken when switching the V
PP PP
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across V , V to GND to suppress spurious
PP CC
voltage transients which may damage the device.
Note 14: During power up the CE /PGM pin must be brought high (≥V ) either coincident with or before power is applied to V
.
IH
PP
5
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Turbo Programming Algorithm Flow Chart
DS010836-6
FIGURE 1.
Read Mode
Functional Description
The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs. Chip
Enable (CE /PGM ) is the power control and should be used
for device selection. Output Enable (OE) is the output control
and should be used to gate data to the output pins, indepen-
dent of device selection. Assuming that addresses are
stable, address access time (tACC) is equal to the delay from
CE to output (tCE). Data is available at the outputs tOE after
the falling edge of OE, assuming that CE /PGM has been low
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table
1. It should be noted that all inputs for the six modes are at
TTL levels. The power supplies required are VCC and VPP
The VPP power supply must be at 12.75V during the three
programming modes, and must be at 5V in the other three
modes. The VCC power supply must be at 6.25V during the
three programming modes, and at 5V in the other three
modes.
.
and addresses have been stable for at least tACC-tOE
.
Standby Mode
The EPROM has a standby mode which reduces the active
power dissipation by over 99%, from of 65 mW to 0.55 mW.
The EPROM is placed in the standby mode by applying a
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Program Inhibit
Functional Description (Continued)
Programming multiple EPROMs in parallel with different data
is also easily accomplished. Except for CE/PGM all like in-
puts (including OE) of the parallel EPROMs may be com-
mon. A TTL low level program pulse applied to an EPROM’s
CE /PGM input with VPP at 12.75V will program that
EPROM. A TTL high level CE /PGM input inhibits the other
EPROMs from being programmed.
CMOS high signal to the CE/PGM input. When in standby
mode, the outputs are in a high impedance state, indepen-
dent of the OE input.
Output Disable
The EPROM is placed in output disable by applying a TTL
high signal to the OE input. When in output disable all cir-
cuitry is enabled, except the outputs are in a high impedance
state (TRI-STATE).
Program Verify
A verify should be performed on the programmed bits to de-
termine whether they were correctly programmed. The verify
Output OR-Typing
may be performed with VPP at 12.75V. VPP must be at VCC
,
Because the EPROM is usually used in larger memory ar-
rays, Fairchild has provided a 2-line control function that ac-
commodates this use of multiple memory connections. The
2-line control function allows for:
except during programming and program verify.
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window to
prevent unintentional erasure. Covering the window will also
prevent temporary functional failure due to the generation of
photo currents.
1. the lowest possible memory power dissipation, and
2. complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recom-
mended that CE /PGM be decoded and used as the primary
device selecting function, while OE be made a common con-
nection to all devices in the array and connected to the
READ line from the system control bus. This assures that all
deselected memory devices are in their low power standby
modes and that the output pins are active only when data is
desired from a particular memory device.
MANUFACTURER’S IDENTIFICATION CODE
The EPROM has a manufacturer’s identification code to aid
in programming. When the device is inserted in an EPROM
programmer socket, the programmer reads the code and
then automatically calls up the specific programming algo-
rithm for the part. This automatic programming control is only
possible with programmers which have the capability of
reading the code.
Programming
The Manufacturer’s Identification code, shown in Table 2,
specifically identifies the manufacturer and device type. The
code for NM27C040 is “8F08”, where “8F” designates that it
is made by Fairchild Semiconductor, and “08” designates a 4
Megabit (512K x 8) part.
CAUTION: Exceeding 14V on pin 1 (VPP) will damage the
EPROM.
Initially, and after each erasure, all bits of the EPROM are in
the “1’s” state. Data is introduced by selectively program-
ming “0’s” into the desired bit locations. Although only “0’s”
will be programmed, both “1’s” and “0’s” can be presented in
the data word. The only way to change a “0” to a “1” is by ul-
traviolet light erasure.
±
The code is accessed by applying 12V 0.5V to address pin
A9. Addresses A1–A8, A10–A18, and all control pins are
held at VIL. Address pin A0 is held at VIL for the manufactur-
er’s code, and held at VIH for the device code. The code is
read on the eight data pins, O0–O7. Proper code access is
The EPROM is in the programming mode when the VPP
-
±
only guaranteed at 25˚C 5˚C.
power supply is at 12.75V and OE is at VIH. It is required that
at least a 0.1 µF capacitor be placed across VPP, VCCto
ground to suppress spurious voltage transients which may
damage the device. The data to be programmed is applied 8
bits in parallel to the data output pins. The levels required for
the address and data inputs are TTL.
ERASURE CHARACTERISTICS
The erasure characteristics of the device are such that era-
sure begins to occur when exposed to light with wavelengths
shorter than approximately 4000 Angstroms (Ar). It should be
noted that sunlight and certain types of fluorescent lamps
have wavelengths in the 3000Ar–4000Ar range.
When the address and data are stable, an active low, TTL
program pulse is applied to the CE /PGM input. A program
pulse must be applied at each address location to be pro-
grammed. The EPROM is programmed with the Turbo Pro-
gramming Algorithm shown in Figure 1. Each Address is pro-
grammed with a series of 50 µs pulses until it verifies good,
up to a maximum of 10 pulses. Most memory cells will pro-
gram with a single 50 µs pulse. (The standard National
Semiconductor Algorithm may also be used but it will have
longer programming time.)
The recommended erasure procedure for the EPROM is ex-
posure to short wave ultraviolet light which has a wavelength
of 2537Ar. The integrated dose (i.e., UV intensity X exposure
time) for erasure should be minimum of 15W-sec/cm2.
The EPROM should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure.
An erasure system should be calibrated periodically. The dis-
tance from lamp to device should be maintained at one inch.
The erasure time increase as the square of the distance from
the lamp. (If distance is doubled the erasure time increases
by factor of 4.) Lamps lose intensity as they age. When a
lamp is changed, the distance has changed, or the lamp has
aged, the system should be checked to make certain full era-
sure is occurring. Incomplete erasure will cause symptoms
that can be misleading. Programmers, components, and
even system designs have been erroneously suspected
when incomplete erasure was the problem.
The EPROM must not be programmed with a DC signal ap-
plied to the CE /PGM input.
Programming multiple EPROM in parallel with the same data
can be easily accomplished due to the simplicity of the pro-
gramming requirements. Like inputs of the parallel EPROM
may be connected together when they are programmed with
the same data. A low level TTL pulse applied to the CE /PGM
input programs the paralleled EPROM.
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peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 µF ceramic
capacitor be used on every device between VCC and GND.
This should be a high frequency capacitor of low inherent in-
ductance. In addition, at least a 4.7 µF bulk electrolytic ca-
pacitor should be used between VCC and GND for each eight
devices. The bulk capacitor should be located near where
the power supply is connected to the array. The purpose of
the bulk capacitor is to overcome the voltage drop caused by
the inductive effects of the PC board traces.
Functional Description (Continued)
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, ICC
,
has three segments that are of interest to the system de-
signer: the standby current level, the active current level, and
the transient current peaks that are produced by voltage
transitions on input pins. The magnitude of these transient
current peaks is dependent of the output capacitance load-
ing of the device. The associated VCC transient voltage
Mode Selection
The modes of operation of the NM27C040 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs
are TTL levels except for VPP and A9 for device signature.
TABLE 1. Modes Selection
Pins
CE /PGM
OE
VPP
VCC
Outputs
Mode
Read
VIL
VIL
X
(Note 15)
X
5.0V
DOUT
Output Disable
Standby
X
VIH
X
5.0V
5.0V
High Z
High Z
DIN
VIH
VIL
X
X
Programming
Program Verify
Program Inhibit
VIH
VIL
VIH
12.75V
12.75V
12.75V
6.25V
6.25V
6.25V
DOUT
High Z
VIH
Note 15: X can be V or V
IL
H
TABLE 2. Manufacturer’s Identification Code
A0 A9 O7 O6 O5 O4 O3 O2
(12) (26) (21) (20) (19) (18) (17) (15) (14) (13) Data
Pins
O1
O0 Hex
Manufacturer
Code
VIL 12V
1
0
0
0
1
1
1
1
8F
Device Code
VIH 12V
0
0
0
0
1
0
0
0
08
Book
Extract
End
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THIS PAGE IS IGNORED IN THE DATABOOK
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Physical Dimensions inches (millimeters) unless otherwise noted
32-Lead EPROM Ceramic Dual-In-Line Package (Q)
Order Number NM27C040QXXX
Package Number J32AQ
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
32-Lead PLCC Package (V)
Order Number NM27C040VXXX
Package Number VA32A
11
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11
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
32-Lead TSOP Package
Order Number NM27C040TXXX
Package Number MBH32A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor
Corporation
Fairchild Semiconductor
Europe
Fairchild Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
Americas
Customer Response Center
Tel: 1-888-522-5372
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 8 141-35-0
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
English Tel: +44 (0) 1 793-85-68-56
Italy
Tel: +39 (0) 2 57 5631
Tel: +852 2737-7200
Fax: +852 2314-0061
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
PrintDate=1997/08/11 PrintTime=19:20:33 6769 ds010836 Rev. No. 3 cmserv Proof
12
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