NM24C16FTMT8 [FAIRCHILD]

EEPROM, 16KX1, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8;


型号：	NM24C16FTMT8
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	EEPROM, 16KX1, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件：	总7页 (文件大小：25K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Fairchild

Application Note 957

Interfacing the NM24C16

Serial EEPROM to the

8031 Microcontroller

8031 INTERFACE DESCRIPTION

INTRODUCTION

The interface to the 8031 uses 2 general purpose port lines. One

of the lines is used to drive the SCL input of the NM24C16, and the

other is used as an I/O port connected to the SDA line. The 8031

has very weak pull-ups on the output ports that provide a high

state.Whenan8031portbitissendingahigh,thebitcanbedriven

externally and used as an input.

This applications note describes an interface between the Fair-

child Semiconductor NM24C16 serial EEPROM and an 8031

microcontroller. The interface between the devices uses 2 of the

8031 general purpose I/O port lines. Software has been devel-

oped that demonstrates how the NM24C16 can be accessed

through the I/O port bits. The circuit and software has been bench

tested and is ready to be used in an end user application.

Port 1 of the 8031 provides the 2 I/O bits for the interface. Figure

1shows how the NM24C16 is connected to the 8031. The port bits

that were chosen for this interface are not especially significant.

Any 2 available port bits could be used as long as 1 can be

configured an output and 1 as an I /O with the weak pull-up.

Changes in the interface software to implement different port

placements would only require a change in the SDA and SCL port

definition at the top of the program.

NM24C16 DESCRIPTION

The NM24C16 is a 16k serial EEPROM that has a 2k by 8-bit

architecture. The NM24C16 uses the industry standard I²C serial

protocol for data transfers.

The I²C protocol allows several devices to share the same two

wire clock and data bus. Devices that are compatible with the

protocol fall into the categories of being either a master or a slave.

A master device controls the transfer of data, and a slave device

responds to the commands issued by a master. The NM24CXX

family of devices always fall into the category of slave devices

since they can not initiate data transfers.

10k

P1.0

P1.1

SDA V

SCL A0

The I²C protocol uses a clock (SCL) and a bidirectional data line

(SDA). When the NM24C16 is transmitting data an open drain

transistor is used to control the state of the SDA line. The SDA I/

O pulls the line low for a zero state, or places the line in high

impedance for a one state. An external pull-up resistor ensures a

“high” condition exists when the SDA line is in a high impedance

state.

8031

NM24C16

FIGURE 1. NM24C16 to 8031 Connections

SOFTWARE DESCRIPTION

Data is transfered back and forth by using predefined bit se-

quences. All transfers are initiated with a START condition (SDA

going low with SCL high) and terminated with a STOP condition

(SDA going high with SCL high). If an unexpected STOP is ever

detected the NM24C16 will return to the standby mode. Because

transitions of SDA when SCL is high have been defined as STOP

and START conditions, the SDA line must change only when SCL

is low while transfers are being performed.

The software listing demonstrates a byte read and byte write

operation. The read and write operations are implemented in

separate subroutines. Parameters to be passed into the subrou-

tines are stored in the SRAM portion of the 8031. The passed

parameters include address (hi-order and low-order) and data

(single byte) information. The variables are sometimes modified

during subroutine operation so they must be initialized immedi-

ately prior to a subroutine call. Expansions of the byte read and

write routines to implement sequential read and page write should

be straightforward.

DATA TRANSFERS

There are just two types of data transfers used on the NM24C16,

apagewriteoperation,andasequentialreadoperation.Bytewrite

and byte read operations are simply truncated versions of a page

write or sequential read.

The software also implements acknowledge (ACK) polling to

indicatewhenawriteoperationhascompleted.WhiletheNM24C16

isactuallychangingthestateoftheEEPROMbitsallinputpinsare

ignored. Once a write cycle has concluded the NM24C16 will

return an acknowledge when a valid slave address is issued. The

ACK polling routine repeatedly sends a slave address and check

to see if the X24C16 returns an acknowledge. A STOP condition

is issued once an ACK is received to return the NM24C16 to the

standby mode. Using acknowledge polling can significantly re-

duce the effective Write Cycle Time because the actual time

required is typically much less than the maximum specified in the

data sheet.

The page write allows up to 16 bytes in a single page to be altered

during a single write operation. It is important to note that all

addresses to be altered must reside in the same 16 byte page. A

byte write is the same as a page write with the data in a single

address being altered.

The sequential read operation will allow read operations starting

at a user defined address and then allow successive addresses to

be read as long as the user continues to indicate that the read

operation is to continue. The byte read is simply a sequential read

from only a single address.

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Althoughthisapplicationsnotedescribesaninterfacetothe8031,

the issues discussed can be used to implement an 8031 interface

to any general purpose microcontroller.

CONCLUSION

ThisapplicationsnotehasshownhowtheNM24C16caneasilybe

interfaced to the 8031 microcontroller. Interface resources are

minimal with only 2 I/O port pins and 200 bytes of code required.

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***************************************************************;

;*This code was developed to demonstrate how the NM24C16 serial EEPROM *

;*can be interfaced to the 8031 microcontroller. The software includes *

;*byte read and a byte write routines.

;*The 8031 interfaces to the NM24C16 by using 2 general purpose I/O *

;*port lines. Port 1 is used with one line driving the Nm24C16 SCL *

;*input and a second port line used in a bidirectional mode for SDA. *

;*The mainline was used to test the functionality of the subroutines. *

;*The subroutines can be copied directly into a customer’s program and *

;*be expected to operated as described. The final mainline only *

‘*performs a byte write, acknowledge polling and finaly a byte read. *

********************************************************

;***********************

;*BIT POSITION EQUATES *

;***********************

SDA

SCL

BIT

P1.0

P1.1

;SDA position in port 1

;SCL position in port 1

;*********************

;*VARIABLE REGISTERS *

;*********************

ADDLO

ADDHI

COUNT

TDATA

RWDATA

EQU

;low order address pointer

;high order address pointer

;loop counter

;scratch register

;read and write data register

;***************

;*RESET VECTOR *

;***************

ORG

LJMP

0000H

BEGIN

;reset vector to address 0100H

;initialize stack pointer

;************************

PROGRAM STARTING LOCATION *

;************************

ORG

BEGIN:

0100H

MOV

SP,#60H

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;***********

;*MAINLINE *

;***********

MOV

LCALL WRITE

LCALL POLL

LCALL READ

A,#001H

ADDHI,A

A,#023H

ADDLO,A

A,#096H

RWDATA,A

;write data 96H to address 0123H

;perform acknowledge polling

;read data from address 0123H

;wait until reset loop

DONE: LJMP

DONE

;*****************************

;*NM24C16 FUNCTIONAL ROUTINES *

;*****************************

;******************************************************;*

;*WRITE performs a byte write operation into the NM24C16. The routine *

;*expects the address to modify to be specified in the ADDLO and ADDHI *

;*variables. The new data value is specified in the RWDATA variable. *

;********************************************************

WRITE: LCALL

START

;issue START condition

;build slave address

MOV

A,ADDHI

ORL

LCALL SENDB

LCALL ACK

A,#0A0H

;send slave address

;get ACK from NM24C16

MOV

LCALL SENDB

LCALL ACK

A,ADDLO

;send low order address

;get ACK from NM24C16

MOV

A,RWDATA

LCALL SENDB

LCALL ACK

LCALL STOP

RET

;send data value to write

;get ACK from NM24C16

;issue STOP condition

;******************************************************;*

;*POLL performs acknowledge to determine when a write cycle has

;*completed. The routine repeatedly issues a dummy slave address and *

;*checks for an acknowledge from the NM24C16. Once the NM24C16

;*responds with an acknowledge the routine terminates.

;********************************************************

POLL: LCALL START ;issue a START condition

MOV A,#0A0H

LCALL SENDB

LCALL ACK

;send the dummy slave address

;look for acknowledge from NM24C16

;loop until acknowledge is received

;issue STOP condition

POLL

LCALL STOP

RET

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;******************************************************;*

;*READ perfoms a byte read from the address specified in the ADDHI *

;*and ADDLO variables. The data that is read is returned in the

;*variable RWDATA.

;********************************************************

READ:

MOV

LCALL

A,ADDHI

START

;issue a START condition

;issue slave address with R/W=0

ORL

LCALL SENDB

LCALL ACK

A,#0A0H

;send slave address

;get ACK from NM24C16

MOV

A,ADDLO

LCALL SENDB

LCALL ACK

LCALL START

;send low order address

;get ACK from NM24C16

;issue START condition

MOV

ORL

A,ADDHI

A,#0A1H

LCALL SENDB

LCALL ACK

LCALL READB

;issue slave address with R/W=1

;get ACK from NM24C16

;read data byte

MOV

SETB

RWDATA,A

SDA

;put data into RWDATA variable

;clock in a 1 (no acknowledge)

LCALL CLOCK

LCALL STOP

RET

;issue a STOP condition

;******************************************************;*

;*START issues a START condition to the NM24C16. The routine makes *

;*sure that both SDA and SCL are high. Then bring SDA low first *

;*followed by bringing SCL low.

;********************************************************

START: SETB

SDA

;make sure SDA and SCL are high

SETB

CLR

NOP

CLR

RET

SCL

SDA

;bring SDA low

;NOPs assure correct timing

SCL

;bring SCL low

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;******************************************************;*

;*STOP issues a STOP condition to the NM24C16. The routine makes *

;*sure that the SDA line is low before trying to issue the STOP. *

;*The routine then brings SCL high followed by bringing SDA high. *

;********************************************************

STOP:

SETB

CLR

SCL

SDA

;make sure SDA is low

;bring SCL high

;NOPs assure correct timing

NOP

SETB

RET

SDA

;bring SDA high

;******************************************************;*

;*CLOCK issues a clock pulse to the NM24C16. The state of SDA is *

;*sampled before the clock pulse is issued.

;********************************************************

CLOCK: MOV

C,SDA

;sample SDA and put state in carry flag

;bring SCL high

;NOPs assure correct timing

SETB

NOP

CLR

RET

SCL

;bring SCL low

;******************************************************;*

ACK allows the NM24C16 to send an acknowledge back to the 8031. *

;********************************************************

ACK:

SETB

SDA

;bring SDA high

;issue a clock pulse

LCALL CLOCK

RET

;******************************************************;*

;*SENDB sends a byte to the NM24C16. The routine receives the data *

;*to send in the A register.

;********************************************************

SENDB MOV

TDATA,A

;move data to send into TDATA

;8 bits to send

store 8 in down counter

;return data to send into A register

;send most significant bit first

;move bit to SDA port

;issue clock pulse

MOV

A,#8

COUNT,A

A,TDATA

NEXTR: RLC

MOV

SDA,C

LCALL CLOCK

DJNZ

RET

COUNT,NEXTR

;loop 8 times

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;******************************************************;*

;*READB reads a byte from the NM24C16. The routine returns the byte *

;*that is read in the A register.

;********************************************************

READB: MOV

A,#8

;8 bits to read

;store 8 in down counter

;issue clock pulse

MOV

COUNT,A

NEXTW: LCALL

CLOCK

RLC

DJNZ

RET

;store and shift data from SDA

;loop 8 times

COUNT,NEXTW

END

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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NM24C16FTMT8 [FAIRCHILD]

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