NM24C08FN [FAIRCHILD]
EEPROM, 1KX8, Serial, CMOS, PDIP8, PLASTIC, DIP-8;
| 型号： | NM24C08FN |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | EEPROM, 1KX8, Serial, CMOS, PDIP8, PLASTIC, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：35K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fairchild
Application Note 794
Using an EEPROM—
IIC Interface
NM24C02/03/04/05/08/09/
16/17
ration used by the IIC interface compared to that of the
MICROWIRE™ and SPI interface, reduced board space and pin
count allows the designer to have more creative flexibility while
reducing interconnecting cost.
INTRODUCTION
Fairchild Semiconductor’s NM24C EEPROMs are designed to
interface with Inter-Integrated Circuit (IIC) buses and hardware.
Fairchild’s electrically erasable programmable read only memo-
ries (EEPROMs) offer valuable security features (write protec-
tion), two write modes, three read modes and a wide variety of
memory sizes. Applications for the IIC bus and NM24C memories
are included in SANs (small-area networks), stereos, televisions,
automobiles and other scaled-down systems that don’t require
tremendous speeds but instead cost efficiency and design sim-
plicity.
OPERATING Fairchild SEMICONDUCTOR’S
NM24Cs
TheNM24CE2PROMsrequireonlysixsimpleoperatingcodesfor
transmittingorreceivingbitsofinformationoverthe2-wireIICbus.
These fields are explained in greater detail below and briefly
described hereafter: a start bit, a 7-bit slave address, a read/write
bit which defines whether the slave is a transmitter or receiver, an
acknowledge bit, message bits divided into 8-bit segments and a
stop bit.
IIC BACKGROUND
The IIC bus configuration is an amalgam of microcontrollers and
peripheral controllers. By definition: a device that transmits sig-
nalsontotheIICbusisthe“transmitter”andadevicethatreceives
signals is the “receiver”; a device that controls signal transfers on
thelineinadditiontocontrollingtheclockfrequencyisthe“master”
and a device that is controlled by the master is the “slave”. The
master can transmit or receive signals to or from a slave, respec-
tively, or control signal transfers between two slaves, where one
is the transmitter and the other is the receiver. It is possible to
combineseveralmasters,inadditiontoseveralslaves,ontoanIIC
bus to form a multimaster system. If more than one master
simultaneously tries to control the line, an arbitration procedure
decides which master gets priority. The maximum number of
devices connected to the bus is dictated by the maximum allow-
able capacitance on the lines, 400 pF, and the protocol’s address-
ing limit of 16k; typical device capacitance is 10 pF. Up to eight
E2PROMs can be connected to an IIC bus, depending on the size
of the memory device implemented.
For efficient and faster serial communication between devices,
the NM24C Family features page write and sequential read.
TheNM24C03/C05/C09/C16/C17Familyoffersasecurityfeature
in addition to standard features found in the NM24C02/C04/C08/
C16Family. Thesecurityfeatureisbeneficial inthatitallowsRead
Only Memory (ROM) to be implemented in the upper half of the
memory to prevent any future programming in that particular chip
section; the remaining memory that has not been write protected
can still be programmed. The security feature in the NM24C03/
C05/C09/C17 Family does not require immediate implementation
when the device is interfaced to the IIC bus, which gives the
designer the option to choose this feature at a later date. Table 1
displays the following parameters: memory content, write protect
and the maximum number of individual IIC E2PROMs allowed on
anIICbusatonetimeifthetotallinecapacitanceiskeptbelow400
pF.
CodeusedtointerfacetheNM24CswithFairchildSemiconductor’s
COP8™ Microcontroller Family is listed in a latter section of this
application note for further information to the reader.
Simplicity of the IIC system is primarily due to the bidirectional 2-
wire design, a serial data line (SDA) and serial clock line (SKL),
and to the protocol format. Because of the efficient 2-wire configu-
TABLE 1.
Number of
Part No.
Write Protect
Max.
256x8 Page Blocks
Feature
No
Parts
NM24C02
NM24C03
NM24C04
NM24C05
NM24C08
NM24C09
NM24C16
NM24C17
1
1
2
2
4
4
8
8
8
8
4
4
2
2
1
1
Yes
No
Yes
No
Yes
No
Yes
1
© 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Slave 1
(RAM)
Master 1
Data
Clock
Slave 2
(EEPROM)
Master 2
FIGURE 1. IIC-Bus Configurations
Slave address
Clock
Data
. . . . . . . .
B1 B2
B8 ACK
B8 ACK
n
1
1
1
t
t
t
HP BF
HS
FIGURE 2. IIC Bus Timing
Start Condition
—Clock and Data line high (Bus free)
—Change Data line from high to low
— After tHS(Min) = 4 µs the master supplies the clock
Acknowledge
—Transmitting device releases the Data line
—The receiving device pulls the Data line low during the ACK-clock if there is no error
—If there is no ACK, the master will generate a Stop Condition to abort the transfer
Stop Condition
—Clock line goes high
—After tHP(Min) = 4.7 µs the Data lines go high
—The master maintains the Data and Clock line high
—Next Start Condition after tFB(Min) = 4.7 µs is possible
2
www.fairchildsemi.com
START/STOP CONDITIONS
ARBITRATION
If both the data and clock lines are HIGH, the bus is not busy. To
attain control of the bus, a start condition is needed from a master;
and to release the lines, a stop condition is required.
Only in multimaster systems.
If more than one device are potential masters and more than one
desires access to the bus, an arbitration procedure takes place: if
a master transmits a HIGH level and another master transmits a
LOW level, the master with the LOW level will get the bus and the
other master will release the bus; and the clock line switches
immediately to the slave receiver mode. This arbitration could
carry on through many bits (address bits and data bits are used for
arbitration).
Start Condition: HIGH-to-LOW transition of the data line while
the clock line is in a HIGH state.
Stop Condition: LOW-to-HIGH transition of the data line while
the clock line is in a HIGH state.
The master always generates the start and stop conditions. After
the start condition the bus is in the busy state. The bus becomes
free after the stop condition.
FORMATS
There are three data transfer formats supported:
DATA BIT TRANSFER
After a start condition “S” one databit is transferred during each
clockpulse.ThedatamustbestableduringtheHIGH-periodofthe
clock. The data line can only change when the clock line is at a
LOW level.
—Master transmitter writes to slave receiver; no direction
change
—Master reads immediately after sending the address byte
—Combined format with multiple read or write tranfers.
Normally each data transfer is done with 8 data bits and 1
acknowledge bit (byte format with acknowledge).
ADDRESSING
The7-bitaddressofanIICdeviceandthedirectionofthefollowing
data is coded in the first byte after the start condition:
ACKNOWLEDGE
Each data transfer needs to be acknowledged. The master
generates the acknowledge clock pulse. The transmitter releases
the data line (SDA = HIGH) during the acknowledge clock pulse.
If there was no error detected, the receiver will pull down the SDA-
line during the HIGH period of the acknowledge clock pulse.
MSB
MSB
R/W
Slave Address
If a slave receiver is not able to acknowledge, the slave will keep
the SDA line HIGH and the master can then generate a STOP
condition to abort the transfer.
A “0” on the least significant bit indicates that the master will write
information to the selected Slave address device; a “1” indicates
that the master will read data from the slave.
If a master receiver keeps the SDA line HIGH, during the acknowl-
edge clock pulse the master signals the end of data transmission
and the slave transmitter release the data line to allow the master
to generate a STOP-condition.
Some slave addresses are reserved for future use. These are all
addresseswiththebitcombinations1111XXXand 0000XXX. The
address00000000isusedforageneralcall address, forexample,
toinitializeallI2Cdevices(refertoI2Cbusspecificationfordetailed
information).
3
www.fairchildsemi.com
Master Transmits to Slave, No Direction Change
S
Slave Address R W
"0" = WRITE
A
Data
A
Data
A
P
Data transferred
(in bytes + Acknowledge)
Master Reads Slave Immediately after First Byte
S
Slave Address R W
"1" READ
A
Data
A
Data
A
P
Data transferred
(in bytes + Acknowledge)
The master becomes a master receiver after first ACK
Combined Formats
S
Slave Address R W
A
Data
A
S
Slave Address R W
A
Data
A
P
Read or Write
Read or Write
n bytes Data + ACK
n bytes Data + ACK
S = Start Condition
A = Acknowledge
P = Stop Condition
FIGURE 3. IIC-Bus Transfer Formats
TIMING
µs; and the maximum fall time on SDA and SCL is 300 ns. Figure
4 shows the detailed timing requirements.
Themastercangenerateamaximumclockfrequencyof100KHz.
TheminimumLOWperiodisdefinedas4.7µs;theminimumHIGH
period width is 4 µs; the maximum rise time on SDA and SCL is 1
Symbol
fSCL
Parameter
Min
0
Max
Units
kHz
SCL Clock Frequency
100
tBUF
Time the Bus Must Be Free before a New Transmission
Can Start
4.7
µs
tHD:STA
Hold Time Start Condition. After this Period the First Clock
Pulse is Generated
4.0
µs
tLOW
The LOW Period of the Clock
4.7
4.7
µs
µs
tSU:STA
Setup Time for Start Condition
(Only Relevant for a Repeated Start Condition)
tHD:DAT
Data in Hold Time
5
µs
µs
0 (Note 1)
tSU:DAT
Setup Time Data
250
ns
µs
ns
µs
tr
tf
Rise Time of Both SDA and SCL Lines
Fall time of Both SDA and SCL Lines
Setup Time for Stop Condition
1
300
tSU:STO
4.7
Note 1: Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns) of the falling edge of SCL.
FIGURE 4. IIC-Bus Timing Requirements
4
www.fairchildsemi.com
+
+
+
4
3
5
6
8
V
DD
39k
NM24C02
2k BIT
7
4
COP820C
28-PIN
A0
1
A1
2
A2
3
+5V
23
FIGURE 5. IIC Bus EEPROM/µController Configuration Used for Sam ple Code
REMARKS
SOFTWARE TASKS
—The IIC bus, 2-wire serial interface generally requires a pull-
up resistor on the SDA line and the SCL line, depending on
whether TTL or CMOS hardware interfacing exists.
I. Write fixed values to E2PROM cells
II. Read values back from E2PROM and save in RAM locations
from COP
—IIC bus compatible µC’s or peripherals have OPEN DRAIN
Note:
IIC Bus Modes Used:
outputs at SDA and SCL.
Master
SDA →
SCL →
S→ DA
Slave Receiver
Slave Receiver
—COP800 does not have OPEN DRAIN outputs, but the “bus
requirements” can be met by switching SDA and SCL
connections into TRI-STATE® for the following cases:
Transmitter
Master Receiver
The bus is not accessed
SCL →
A slave has to send an acknowledge bit.
—MICROWIRE can not be used for I2C bus operations.
—Current sink capability on SDA and SCL must be 3 mA to
maintain “Low Level” (an IIC bus spec.).
5
www.fairchildsemi.com
.TITLE IIC - EEPROM ROUTINES
.INCLD COP800.INC
.CHIP 840
.LIST X ‘21
* * *TASK RELATED RAM - DECLARE* * *
EEADR
EEWRD
EEDAT1
EEDAT2
FLAG
= 002
= 003
= 004
= 005
= 010
= 012
= 013
= 014
= 015
= 0F0
;ADDRESS OF EEPROM
;WORD ADDRESS EEPR.
;DATA TO EECELL
;SECOND BYTE
;FLAG-WORD
;READ-DATA FROM EE
;SECOND BYTE
;THIRD BYTE
;FOURTH BYTE
;COUNTER FOR BITSHFT
EEREAD
BITCO
INIT:
LD SP,
#06F
LD B,
PORTLD
#00C
#00C
#EEDAT2
#034
#012
;INIT LS, LE FOR EE-
;OPERATIONS
LD [B+],
LD [B],
LD B,
LD [B-],
LD [B-],
LD [B-],
LD [B]
;INIT RAMS
;FIXEED VALUES FOR
;EEWRITE (2 BYTES)
;MIRROR OF #05
;MIRROR OF “A5”
#0A0
#025
;* * * * * * * * * * * * * * * * * * * * * * * * * * *
;EXAMPLE: IF ADDRESS BYTES IS “1010 01X THEN
;STORE:“X010 0101
*
*
;INTO RAM (X=0/1; WRITE/READ)
*
;* * * * * * * * * * * * * * * * * * * * * * * * * * *
LD PSW,
LD CNTRL,
LD FLAG,
#00
#00
#0
;LOAD PSW
;AND CNTRL REG.
.FORM
; * * * * * * * * * * * * * * * * * * *
; * * * * DO WRITE TO EE-PROM * * * *
; * * * * * * * * * * * * * * * * * * *
;(2 BYTE SUCCESSIVE WRITE)
SBIT 0,
LD B,
FLAG
PORTLD
;SET FLAG FOR WRITE
;POINT LPORT DAT REG.
;TO MODIFY “SDA, SCL”
;PREPARE FOR START
;CONDITION.
RBIT 2 [B],
JSR STACON
JSR WAIT
;AFTER WRITE TO EE.
;WAIT FOR > THAT 40
6
www.fairchildsemi.com
* * * * * * * * * * * * * * * *
;* * DO THE START CONDITION * *
;* * AND SHIFT OUT ADRESS * * *
;* * BYTE AND WORD-ADRESS * * *
* * * * * * * * * * * * * * * *
STACON:
RBIT 3,
LD B,
PORTLD
#EEADR
;FINISH START COND.
;PREPARE TO CLOCK
;OUT ADDRESS.
LOPA:
LD BITCO,
#008
;DO SETS OF 8 BITS
LOPA 1:
IFBIT 0, [B]
JP ONE,
;SWITCH SDA BEFORE
;SCL
RBIT 2,
JP CLK
PORTLD
PORTLD
;SET BIT LEVLE “0”
ONE:
SBIT 2,
JP CLK
;SET BIT LEVEL “1”
;ENSURE SAME BIT
;LENGTH
CLK:
SBIT 3,
NOP
PORTLD
;DO CLOCK PULSE
NOP
RBIT 3,
RBIT 2,
.FORM
PORTLD
PORTLD
;ENSURE>4USEC
;SWITCH ALSO SDA LOW
LD A, [B]
RRC A,
;ROTATE BYTE ONE
;BIT POS. RIGHT
;AND SAVE
;CHECK IF 8 BITS
;SHIFTED
X A, [B]
DRSZ BITCO
JP LOPA1,
LD A, [B+]
IFBIT 1,
JMP,
FLAG
GETDAT
;DECREMENT 8
;CHECK IF READ
;3RD BYTE IS NEXT?
;IF SO, THEN READ.
;GET ACKNOWLEDGED
;WHEN 8 BITS ARE
;SHIFTED.
CHECK IF READ.
;OR WRITE OPERATION.
;ON READ (HERE)
;AFTER EE-ADDRESS AND
;WORD ADDRESS ARE SHFT
JSR ACK,
FLAG
#04
IFBIT 0,
JP CEC1
IFBNE
JMP LOPA
RET
CEC1:
IFBNE
JMP LOPA
#06
;1ST AND 2ND DATA-
;BYTE (3RD + 4TH)
7
www.fairchildsemi.com
;NSEC TO PROPERLY
;ERASE WRITE.
LD B,
#EEDAT2
#078
#056
#0E0
#025
;INIT RAMS
LD [B-],
LD [B-],
LD [B-],
LD [B],
;ANOTHER 2 BYTES
;OF FIXED DATA
;MIRROR OF #07
;MIRROR OF “A5”
;TO MODIFY “SDA, SCL”
RBIT 2, [B],
JSR STACON,
JSR WAIT,
;PREPARE FOR START
;CONDITION.
;AFTER WRITE TO EE.
;WAIT FOR > THAN 40
;MSEC TO PROPERLY
;ERASE WRITE.
.FORM
;* * * * * * * * * * * * * * * * * *
;* * * * DO READ FROM EE-PROM * * * *
;* * * * * * * * * * * * * * * * * *
(READ 4 SUCCESSIVE BYTES)
RBIT 0
LD B,
LD [B-],
LD [B],
FLAG
#EEWRD
#0A0
;INDICATE READ
;INIT RAMS
;MIRROR OF #05
;MIRROR OF “A5”
#025
;* * * * * * * * * * * * * * * * * * *
;* * FIRST 2 BYTES SAME AS IF WRITE * *
;* * * * * * * * * * * * * * * * * * *
(IN TERMS OF TRNSMIT)
LD B,
RBIT 2 [B]
JSR STACON,
#PRTLD
PORTLD
;PREPARE
;FOR
;START COND.
;AND SHIFT 1ST
;2 BYTES
;PREPARE FOR
;ANOTHER START-
;CONDITION
SBIT 2,
NOP,
NOP,
SBIT 3,
SBIT 1,
PORTLD
FLAG
;SDA HIGH FIRST.
;INDICATE THAT
;3RD BYTE IS NEXT
;INIT RAMS
;MIRROR OF #05
;MIRROR OF “A5”
;PERFORM ANOTHER
;START
LD B,
LD [B-],
LD [B],
#EEWRD
#0A0
#0A5
RBIT 2, [B],
JSR STACON
RBIT 1,
PORTLD
FLAG
JMP INIT
JMP INIT
.FORM
;CLOSE THE LOOP WHEN
;FINISHED
8
www.fairchildsemi.com
STP:
SBIT 3,
PORTLD
PORTLD
;ESTABLISH STOP
;CONDITION
NOP,
SBIT 2,
RET,
.FORM
* * * * * * * * * * * * * * * * * * * *
;* * GET 8BIT OF DATA FROM EE-PROM * *
* * * * * * * * * * * * * * * * * * * *
GETDAT:
JSR ACK,
LD B,
JP
;GET ACKNOWLEDGEMENT
;POINT FIRST READ RAM
;AND READ IN
#EEREAD
GETDT1
GETDAT:
JSR ACK,
;ACKNOWLEDGEMENT TO EE-
;PROM WHEN 8 BITS
;ARE SHIFTED IN.
GETDAT1:
LD BITCO,
RBIT 2,
RBIT 2,
#008
PORTLC
PORTLD
;INIT BIT COUNTER
;BEFORE READING, PUT
;‘SDA’ INTO HIGH-Z
LOPB:
SBIT 3,
PORTLD
PORTLD
PORTLD
;DO CLOCK HIGH
;READ IN EEDATA
;IN SETS OF 8 BITS
RBIT 7, [B]
IFBIT 2,
SBIT 7, [B]
RBIT 3,
DRSZ BITCO,
JP SHFT
;DO CLOCK LOW
;CHECK IF 8 BITS
;ARE SHIFTED
LD A, [B+],
IFBNE
JMP GETDT,
SBIT 2,
;INCREMENT B
;CHECK IF 4 BYTES
;PUT L2=0
;WHEN TRUE, DO STOP
;CONDITION AND
;RETURN
#06
PORTLC
.FORM
SHFT:
LD A [B],
RRC A
;ROTATE BITS ONE
;POSITION RIGHT
X A, [B]
JP LOPB
* * * * * * * * * * * * * * * * * * * * * *
; * * SIMPLE ROUTING TO DO 40 MSEC DELAY * *
* * * * * * * * * * * * * * * * * * * * * *
9
www.fairchildsemi.com
WAIT:
LD OF 1
#0.20
#OFF
;SIMPLE WAIT LOOP
LOPD:
LD OF 2,
LOPC:
DRSZ OF2,
;TO PRODUCE>40SEC
;TIMEOUT
;TO PROPERLY PROGRAM
‘EEPROM. TIME REQUIRED
;TO ERASE/WRITE
SP LOPC,
DRSZOF1,
JP LOPD
RET
;THE EEPART
ACK1:
SBIT 2
JP ACLK
PORTLC
PORTLC
PORTLD
;INDICATE TO EE-PROM
;(PUT DATA LINE LOW)
ACK:
RBIT 2,
PUT DATA-LINE HI-Z
ACLK:
;AND GET ACKNOWLEDGE
;8 BITS ARE SHIFTED,
;DO A DUMMY CLOCK
SBIT 3,
NOP
NOP
NOP
RBIT 3,
PORTLD
PORTLC
;(FOR ACKNOWLEDGE)
SBIT 2,
RET
.END
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a)areintendedforsurgicalimplantintothebody,or(b)support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Americas
Fairchild Semiconductor
Europe
Fairchild Semiconductor
Hong Kong
Fairchild Semiconductor
Japan Ltd.
Customer Response Center
Tel. 1-888-522-5372
Fax:
Tel:
Tel:
Tel:
Tel:
+44 (0) 1793-856858
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
4F, Natsume Bldg.
Deutsch
English
Français
Italiano
+49 (0) 8141-6102-0
+44 (0) 1793-856856
+33 (0) 1-6930-3696
+39 (0) 2-249111-1
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
10
www.fairchildsemi.com
相关型号：
©2020 ICPDF网 联系我们和版权申明