NM24C05UFLZVN [FAIRCHILD]
I2C Serial EEPROM ; I2C串行EEPROM\n
| 型号： | NM24C05UFLZVN |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | I2C Serial EEPROM
|
| 文件： | 总13页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1999
NM24C04U/NM24C05U
4K-Bit Serial EEPROM
2-Wire Bus Interface
General Description
Functions
The NM24C04U/05U devices are 4K (4,096) bit serial interface
CMOS EEPROMs (Electrically Erasable Programmable Read-
OnlyMemory).ThesedevicesfullyconformtotheStandardI2C™
2-wire protocol which uses Clock (SCL) and Data I/O (SDA) pins
to synchronously clock data between the "master" (for example a
microprocessor) and the "slave" (the EEPROM device). In addi-
tion, the serial interface allows a minimal pin count packaging
designed to simplify PC board layout requirements and offers the
designer a variety of low voltage and low power options.
I I2C™ compatible interface
I 4,096 bits organized as 512 x 8
I Extended 2.7V – 5.5V operating voltage
I 100 KHz or 400 KHz operation
I Self timed programming cycle (6ms typical)
I "Programming complete" indicated by ACK polling
I NM24C05U: Memory "Upper Block" Write Protect pin
Features
NM24C05U incorporates a hardware "Write Protect" feature, by
which, the upper half of the memory can be disabled against
programming by connecting the WP pin to VCC. This section of
memory then effectively becomes a ROM (Read-Only Memory)
andcannolongerbeprogrammedaslongasWPpinisconnected
I The I2C™ interface allows the smallest I/O pincount of any
EEPROM interface
I 16 byte page write mode to minimize total write time per byte
to VCC
.
I Typical 200µA active current (ICCA)
I Typical 1µA standby current (ISB) for "L" devices and 0.1µA
standby current for "LZ" devices
Fairchild EEPROMs are designed and tested for applications requir-
ing high endurance, high reliability and low power consumption for a
continuously reliable non-volatile solution for all markets.
I Endurance: Up to 1,000,000 data changes
I Data retention greater than 40 years
Block Diagram
V
CC
V
SS
WP
H.V. GENERATION
TIMING &CONTROL
START
STOP
SDA
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
2
E
PROM
COMPARATOR
XDEC
ARRAY
SCL
A2
A1
WORD
ADDRESS
COUNTER
R/W
YDEC
CK
D
OUT
DATA REGISTER
D
IN
DS800008-1
I2C™ is a registered trademark of Philips Electronics N.V.
1
© 1999 Fairchild Semiconductor Corporation
NM24C04U/NM24C05U Rev. C.1
www.fairchildsemi.com
Connection Diagrams
Dual-in-Line Package (N), SO Package (M8), and TSSOP Package (MT8)
NC
A1
A2
1
2
3
4
8
7
6
5
V
CC
NC
SCL
NM24C04U
V
SDA
SS
DS800008-2
Top View
See Package Number N08E, M08A, and MTC08
Pin Names
A1,A2
Device Address Inputs
Ground
VSS
SDA
SCL
NC
Serial Data I/O
Serial Clock Input
No Connection
Power Supply
VCC
Dual-in-Line Package (N), SO Package (M8), and TSSOP Package (MT8)
NC
A1
A2
1
2
3
4
8
7
6
5
V
CC
WP
NM24C05U
SCL
V
SDA
SS
DS800008-3
Top View
See Package Number N08E, M08A, and MTC08
Pin Names
NC
No Connection
A1,A2
VSS
Device Address Inputs
Ground
SDA
SCL
WP
Serial Data I/O
Serial Clock input
Write Protect
VCC
Power Supply
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NM24C04U/NM24C05U Rev. C.1
Ordering Information
NM 24 XX
C
U
F
LZ
E
XX
Letter Description
Package
N
8-pin DIP
M8
MT8
8-pin SOIC
8-pin TSSOP
Temp. Range
None
0 to 70°C
V
E
-40 to +125°C
-40 to +85°C
Voltage Operating Range
SCL Clock Frequency
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
Blank
F
100KHz
400KHz
Ultralite
CS100UL Process
Density
04
05
4K
4K with Write Protect
C
CMOS Technology
W
Total Array Write Protect
Interface
24
IIC
NM
Fairchild Non-Volatile
Memory
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NM24C04U/NM24C05U Rev. C.1
Product Specifications
Operating Conditions
Ambient Operating Temperature
Absolute Maximum Ratings
Ambient Storage Temperature
–65°C to +150°C
6.5V to –0.3V
NM24C04U/05U
NM24C04UE/05UE
NM24C04UV/05UV
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltages
with Respect to Ground
Lead Temperature
Positive Power Supply
NM24C04U/05U
(Soldering, 10 seconds)
+300°C
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
ESD Rating
2000V min.
NM24C04UL/05UL
NM24C04ULZ/05ULZ
Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Limits
Typ
Units
Min
Max
(Note 1)
ICCA
Active Power Supply Current
fSCL = 400 KHz
fSCL = 100 KHz
0.2
1.0
mA
ISB
ILI
Standby Current
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
10
0.1
0.1
50
µA
µA
µA
V
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
1
ILO
VIL
VIH
VOL
–0.3
VCC x 0.3
VCC + 0.5
0.4
Input High Voltage
Output Low Voltage
VCC x 0.7
V
IOL = 3 mA
V
Low VCC (2.7V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Limits
Units
Min
Typ
Max
(Note 1)
ICCA
Active Power Supply Current fSCL = 400 KHz
fSCL = 100 KHz
0.2
1.0
mA
ISB
Standby Current
VIN = GND VCC = 2.7V - 4.5V
1
0.1
10
10
1
50
µA
µA
µA
or VCC
VCC = 2.7V - 4.5V
VCC = 4.5V - 5.5V
ILI
ILO
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND to VCC
VOUT = GND to VCC
0.1
0.1
1
1
µA
µA
V
VIL
VIH
VOL
–0.3
VCC x 0.3
VCC + 0.5
0.4
Input High Voltage
VCC x 0.7
V
Output Low Voltage
IOL = 3 mA
V
Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V (Note 2)
Symbol
CI/O
Test
Conditions
VI/O = 0V
Max Units
Input/Output Capacitance (SDA)
8
pF
CIN
Input Capacitance (A0, A1, A2, SCL)
VIN = 0V
6
pF
Note 1: Typical values are TA = 25°C and nominal supply voltage (5V).
Note 2: This parameter is periodically sampled and not 100% tested.
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www.fairchildsemi.com
NM24C04U/NM24C05U Rev. C.1
AC Conditions of Test
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10 ns
Input & Output Timing Levels VCC x 0.5
Output Load
1 TTL Gate and CL = 100 pF
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)
Symbol
Parameter
100 KHz
400 KHz
Units
Min
Max
Min
Max
fSCL
TI
SCL Clock Frequency
100
100
3.5
400
KHz
ns
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN
Pulse width)
50
tAA
SCL Low to SDA Data Out Valid
0.3
4.7
0.1
1.3
0.9
µs
µs
tBUF
Time the Bus Must Be Free before
a New Transmission Can Start
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4.0
4.7
4.0
4.7
0.6
1.5
0.6
0.6
µs
µs
µs
µs
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
tHD:DAT
tSU:DAT
tR
Data in Hold Time
0
0
µs
ns
µs
ns
µs
ns
ms
Data in Setup Time
250
100
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
0.3
tF
300
300
tSU:STO
tDH
4.7
0.6
50
300
tWR
(Note 3)
Write Cycle Time - NM24C04U/05U
- NM24C04U/05UL, NM24C04U/05ULZ
10
15
10
15
Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM24C04U/05U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
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NM24C04U/NM24C05U Rev. C.1
Bus Timing
t
t
R
F
t
HIGH
t
t
LOW
LOW
SCL
t
SU:STO
t
t
t
SU:DAT
SU:STA
HD:DAT
t
HD:STA
SDA
IN
t
BUF
t
t
AA
DH
SDA
OUT
DS800008-8
System Layout
Typical System Configuration
V
V
CC
CC
SDA
SCL
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter/
Receiver
Master
Transmitter
Slave
Receiver
DS800008-20
Note:
Due to open drain configuration of SDA, a bus-level pull-up resistor is called for, (typical value = 4.7kΩ)
Example of 16K of Memory on 2-Wire Bus
V
V
CC
Note:
The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.
The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.
It is recommended that the total line capacitance be less than 400pF
CC
SDA
SCL
V
V
V
V
CC
CC
CC
CC
NM24C02U/03U
NM24C02U/03U
NM24C04U/05U
NM24C08U/09U
A0 A1 A2
V
A0 A1 A2
V
A1 A2
V
A2 V
SS
SS
SS
SS
To V
CC
or V
SS
To V
CC
or V
SS
To V
CC
or V
To V
or V
SS
SS
CC
DS800008-9
Device
Address Pins
A1
Memory Size # of Page
Blocks
A0
A2
NM24C04U/05U
No Connect
ADR
ADR
4096 Bits
2
6
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NM24C04U/NM24C05U Rev. C.1
Device Operation Inputs (A1, A2)
Pin Descriptions
Device address pins A1 and A2 are connected to V
or V
SS
CC
Serial Clock (SCL)
to configure the EEPROM chip address. Table I shows the
active pins.
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA)
Table 1.
SDA is a bidirectional pin used to transfer data into and out of the
device. It is an open drain output and may be wire–ORed with any
number of open drain or open collector outputs.
Device
A0
A1
A2
Effects of Addresses
NM24C04U/05U
x
ADR ADR 22 = 4; 4*x (2x2K)** = 16K
*
Max # of devices on bus
** Number of page blocks per density
WP Write Protection (NM24C05U Only)
Under the Standard IIC protocol the maximum density address-
able using the three pin configuration of the IIC protocol is 16K.
Any combination of densities can be used up to this limit.
If tied to V , PROGRAM operations onto the upper half of the
CC
memory will not be executed. READ operations are possible. If
tied to V , normal operation is enabled, READ/WRITE over the
SS
entire memory is possible.
Background Information (IIC Bus)
As mentioned, the IIC bus allows synchronous bidirectional com-
munication between Transmitter/Receiver using the SCL (clock)
and SDA (Data I/O) lines. All communication must be started with
a valid START condition, concluded with a STOP condition and
acknowledged by the Receiver with an ACKNOWLEDGE condi-
tion.
Thisfeatureallowstheusertoassigntheupperhalfofthememory
as ROM which can be protected against accidental programming.
When write is disabled, slave address and word address will be
acknowledged but data will not be acknowledged.
Device Operation
As shown below, the EEPROMs on the IIC bus may be configured
in any manner required, the total memory addressed can not
exceed 16K (16,384 bits). EEPROM memory address program-
ming is controlled by 2 methods:
The NM24C04U/05U supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data onto the bus
as a transmitter and the receiving device as the receiver. The
device controlling the transfer is the master and the device that is
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the NM24C04U/05U will be considered a
slave in all applications.
• Hardware configuring the A1 and A2 pins (Device Address
pins) with pull-up or pull-down to VCC or VSS. All unused
pins must be grounded (tied to VSS).
• Software addressing the required PAGE BLOCK within the
device memory array (as sent in the Slave Address string).
Clock and Data Conventions
For devices with densities greater than 16K, a different protocol,
theExtendedIICprotocol,isused.RefertoNM24C32Udatasheet
(for example) for additional details.
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH are reserved for indicating
start and stop conditions. Refer to Figure 2 and Figure 3 on next
page.
Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]–[DEVICE ADDRESS]–[PAGE BLOCK AD-
DRESS]–[BYTE ADDRESS]
Start Condition
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
NM24C04U/05UcontinuouslymonitorstheSDAandSCLlinesfor
the start condition and will not respond to any command until this
condition has been met.
DEFINITIONS
WORD
PAGE
8 bits (byte) of data
16 sequential addresses (one byte
each) that may be programmed
during a 'Page Write' programming
cycle
Stop Condition
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the NM24C04U/05U to place the device
in the standby power mode.
PAGE BLOCK
2048 (2K) bits organized into 16
pages of addressable memory.
(8 bits) x (16 bytes) x (16 pages)
= 2048 bits
Write Cycle Timing
Acknowledge
MASTER
Any IIC device CONTROLLING the
transfer of data (such as a
microprocessor)
Acknowledge is a hardware convention used to indicate success-
ful data transfers. The transmitting device, either master or slave,
will release the bus after transmitting eight bits.
SLAVE
Device being controlled
(EEPROMs are always considered
Slaves)
During the ninth clock cycle the receiver will pull the SDA line to
LOW to acknowledge that it received the eight bits of data. Refer
to Figure 4.
TRANSMITTER
RECEIVER
Device currently SENDING data on
the bus (may be either a Master or
Slave).
Device currently RECEIVING data
on the bus (Master or Slave)
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NM24C04U/NM24C05U Rev. C.1
Write Cycle Timing (Figure 1)
SCL
SDA
8th BIT
WORD n
ACK
t
WR
STOP
CONDITION
START
CONDITION
DS800008-10
Note:
The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
Data Validity (Figure 2)
SDA
SCL
DATA STABLE
DATA
CHANGE
DS800008-11
Start and Stop Definition (Figure 3)
SDA
START
STOP
CONDITION
SCL
CONDITION
DS800008-12
Acknowledge Response from Receiver (Figure 4)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
DS800008-13
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NM24C04U/NM24C05U Rev. C.1
Refer to the following table for Slave Addresses string details:
Write Cycle Timing (Continued)
TheNM24C04U/05Udevicewillalwaysrespondwithanacknowl-
edge after recognition of a start condition and its slave address. If
both the device and a write operation have been selected, the
NM24C04U/05U will respond with an acknowledge after the
receipt of each subsequent eight bit byte.
Device
A0 A1 A2 Page Page Block
Blocks Addresses
NM24C04U/05U
P
A
A
2
00 01
A: Refers to a hardware configured Device Address pin
P: Refers to an internal PAGE BLOCK memory segment.
In the read mode the NM24C04U/05U slave will transmit eight bits
of data, release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.
All IIC EEPROMs use an internal protocol that defines a PAGE
BLOCK size of 2K bits (for Word addressess 0000 through 1111).
Therefore, address bits A0, A1, or A2 (if designated 'P') are used
to access a PAGE BLOCK in conjunction with the Word address
used to access any individual data byte (Word).
The last bit of the slave address defines whether a write or read
condition is requested by the master. A '1' indicates that a read
operation is to be executed, and a '0' initiates the write mode.
Device Addressing
Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier (see Figure 5). This
is fixed as 1010 for all EEPROM devices.
A simple review: After the NM24C04U/05U recognizes the start
condition, the devices interfaced to the IIC bus wait for a slave
address to be transmitted over the SDA line. If the transmitted
slave address matches an address of one of the devices, the
designated slave pulls the line LOW with an acknowledge signal
and awaits further transmissions.
Slave Addresses (Figure 5)
Device Type
Identifier
Device
Address
1
0
1
0
A2
A1
A0 R/W (LSB)
Page
NM24C04U/05U
Block Address
DS800008-14
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NM24C04U/NM24C05U Rev. C.1
Acknowledge Polling
Write Operations
Once the stop condition is issued to indicate the end of the host’s
write operation the NM24C04U/05U initiates the internal write
cycle. ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address for a write
operation. If the NM24C04U/05U is still busy with the write
operation no ACK will be returned. If the NM24C04U/05U has
completed the write operation an ACK will be returned and the
host can then proceed with the next read or write operation.
BYTE WRITE
For a write operation a second address field is required which is
awordaddressthatiscomprisedofeightbitsandprovidesaccess
to any one of the 256 bytes in the selected page of memory. Upon
receipt of the byte address the NM24C04U/05U responds with an
acknowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the
NM24C04U/05U begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress the
NM24C04U/05U inputs are disabled, and the device will not
respond to any requests from the master. Refer to Figure 6 for the
address, acknowledge and data transfer sequence.
Write Protection (NM24C05U Only)
Programming of the upper half of the memory will not take place
if the WP pin of the NM24C05U is connected to V . The
CC
NM24C05U will accept slave and byte addresses; but if the
memoryaccessediswriteprotectedbytheWPpin,theNM24C05U
will not generate an acknowledge after the first byte of data has
beenreceived,andthustheprogramcyclewillnotbestartedwhen
the stop condition is asserted.
PAGE WRITE
The NM24C04U/05U is capable of a sixteen byte page write
operation. It is initiated in the same manner as the byte write
operation; but instead of terminating the write cycle after the first
data byte is transferred, the master can transmit up to fifteen more
bytes. After the receipt of each byte, the NM24C04U/05U will
respond with an acknowledge.
After the receipt of each byte, the internal address counter
incrementstothenextaddressandthenextSDAdataisaccepted.
If the master should transmit more than sixteen bytes prior to
generating the stop condition, the address counter will "roll over"
andthepreviouslywrittendatawillbeoverwritten. Aswiththebyte
write operation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 7 for the address, acknowl-
edge, and data transfer sequence.
Byte Write (Figure 6)
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS
Bus Activity:
Master
DATA
SDA Line
A
C
K
A
C
K
A
C
K
Bus Activity:
NM24C04U/05U
DS800008-15
Page Write (Figure 7)
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
Bus Activity:
Master
WORD ADDRESS (n)
DATA n
DATA n + 1
DATA n + 15
SDA Line
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity:
NM24C04U/05U
DS800008-16
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NM24C04U/NM24C05U Rev. C.1
start condition and the slave address with the R/W bit set to one.
ThiswillbefollowedbyanacknowledgefromtheNM24C04U/05U
andthenbytheeightbitdata.Themasterwillnotacknowledgethe
transfer but does generate the stop condition, and therefore the
NM24C04U/05U discontinues transmission. Refer to Figure 9 for
the address, acknowledge and data transfer sequence.
Read Operations
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave
address is set to a one. There are three basic read operations:
current address read, random read, and sequential read.
Current Address Read
Sequential Read
Internally the NM24C04U/05U contains an address counter that
maintains the address of the last byte accessed, incremented by
one. Therefore, if the last access (either a read or write) was to
address n, the next read operation would access data from
address n + 1. Upon receipt of the slave address with R/W set to
one, the NM24C04U/05U issues an acknowledge and transmits
the eight bit byte. The master will not acknowledge the transfer
butdoesgenerateastopcondition,andthereforetheNM24C04U/
05U discontinues transmission. Refer to Figure 8 for the se-
quence of address, acknowledge and data transfer.
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The NM24C04U/05U continues to output data for each
acknowledge received. The read operation is terminated by the
master not responding with an acknowledge or by generating a
stop condition.
The data output is sequential, with the data from address n
followed by the data from n + 1. The address counter for read
operations increments all word address bits, allowing the entire
memory contents to be serially read during one operation. After
the entire memory has been read, the counter "rolls over" and the
NM24C04U/05U continues to output data for each acknowledge
received. Refer to Figure 10 for the address, acknowledge, and
data transfer sequence.
Random Read
Randomreadoperationsallowthemastertoaccessanymemory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to one, the master must first perform a
“dummy” write operation. The master issues the start condition,
slave address and then the byte address it is to read. After the
byte address acknowledge, the master immediately reissues the
Current Address Read (Figure 8)
S
T
S
T
O
P
SLAVE
ADDRESS
Bus Activity:
Master
A
R
T
SDA Line
A
C
K
NO
A
C
Bus Activity:
NM24C04U/05U
DATA
K
DS800008-17
Random Read (Figure 9)
S
T
A
R
T
S
S
T
T
A
R
T
SLAVE
ADDRESS
WORD
ADDRESS
SLAVE
Bus Activity:
Master
O
P
ADDRESS
SDA Line
A
C
K
A
C
K
A
C
K
NO
DATA n
A
C
K
Bus Activity:
NM24C04U/05U
DS800008-18
Sequential Read (Figure 10)
S
T
O
P
A
C
K
A
C
K
A
C
K
Bus Activity:
Slave
Master
Address
SDA Line
A
C
K
NO
A
C
DATA n +1
DATA n +1
DATA n + 2
DATA n + x
Bus Activity:
NM24C04U/05U
K
DS800008-19
11
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NM24C04U/NM24C05U Rev. C.1
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8
7
6
3
5
4
0.228 - 0.244
(5.791 - 6.198)
1
2
Lead #1
IDENT
0.150 - 0.157
0.053 - 0.069
(1.346 - 1.753)
(3.810 - 3.988)
0.010 - 0.020
(0.254 - 0.508)
0.004 - 0.010
(0.102 - 0.254)
x 45°
8° Max, Typ.
All leads
Seating
Plane
0.04
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
(0.102)
All lead tips
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020
(0.356 - 0.508)
Typ.
8-Pin Molded Small Outline Package (M8)
Package Number M08A
0.114 - 0.122
(2.90 - 3.10)
8
5
(7.72) Typ
(4.16) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
Land pattern recommendation
1
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0256 (0.65)
Typ.
Gage
plane
0.0075 - 0.0098
(0.19 - 0.30)
0°-8°
DETAIL A
Typ. Scale: 40X
0.0075 - 0.0098
(0.19 - 0.25)
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded Thin Shrink Small Outline Package
Package Number MTC08
12
www.fairchildsemi.com
NM24C04U/NM24C05U Rev. C.1
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
7
0.032 ± 0.005
(0.813 ± 0.127)
RAD
8
7
6
5
4
0.092
(2.337)
DIA
0.250 - 0.005
(6.35 ± 0.127)
Pin #1
IDENT
+
Pin #1 IDENT
1
Option 1
1
2
3
Option 2
0.280
MIN
0.040
(1.016)
Typ.
(7.112)
0.030
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
MAX
(0.762)
0.300 - 0.320
(7.62 - 8.128)
20° ± 1°
0.130 ± 0.005
(3.302 ± 0.127)
0.125 - 0.140
95° ± 5°
(3.175 - 3.556)
0.065
(1.651)
0.125
(3.175)
DIA
0.020
90° ± 4°
Typ
0.009 - 0.015
(0.229 - 0.381)
(0.508)
Min
0.018 ± 0.003
(0.457 ± 0.076)
NOM
+0.040
-0.015
0.325
0.100 ± 0.010
+1.016
-0.381
8.255
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a)areintendedforsurgicalimplantintothebody,or(b)support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
13
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NM24C04U/NM24C05U Rev. C.1
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