NC7WZ02 [FAIRCHILD]
TinyLogic UHS Dual 2-Input NOR Gate; TinyLogic UHS双2输入或非门
| 型号： | NC7WZ02 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | TinyLogic UHS Dual 2-Input NOR Gate |
| 文件： | 总8页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2000
Revised April 2003
NC7WZ02
TinyLogic UHS Dual 2-Input NOR Gate
General Description
Features
The NC7WZ02 is a dual 2-Input NOR Gate from Fairchild’s
Ultra High Speed Series of TinyLogic . The device is fabri-
cated with advanced CMOS technology to achieve ultra
high speed with high output drive while maintaining low
static power dissipation over a very broad VCC operating
■ Space saving US8 surface mount package
■ MicroPak leadless package
■ Ultra High Speed: tPD 2.4 ns typ into 50 pF at 5V VCC
■ High Output Drive: ±24 mA at 3V VCC
range. The device is specified to operate over the 1.65V to
5.5V VCC range. The inputs and output are high impedance
■ Broad VCC Operating Range: 1.65V to 5.5V
■ Matches the performance of LCX when operated at
3.3V VCC
when VCC is 0V. Inputs tolerate voltages up to 7V indepen-
dent of VCC operating voltage.
■ Power down high impedance inputs/output
■ Overvoltage tolerant inputs facilitate 5V to 3V
translation
■ Patented noise/EMI reduction circuitry implemented
Ordering Code:
Product
Order
Package Code
Number Top Mark
Package Description
Supplied As
Number
NC7WZ02K8X MAB08A
WZ02
P5
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel
NC7WZ02L8X MAC08A
(Preliminary)
8-Lead MicroPak, 1.6 mm Wide
5k Units on Tape and Reel
TinyLogic is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak is a trademark of Fairchild Semiconductor Corporation.
© 2003 Fairchild Semiconductor Corporation
DS500269
www.fairchildsemi.com
Logic Symbol
Connection Diagrams
IEEE/IEC
Pin Descriptions
(Top View)
Pin Names
An, Bn
Yn
Description
Inputs
Pin One Orientation Diagram
Output
Function Table
Y = A + B
Inputs
Output
AAA represents Product Code Top Mark - see ordering code
A
L
B
L
Y
H
L
Note: Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
L
H
L
Pad Assignments for MicroPak
H
H
L
H
L
H = HIGH Logic Level
L = LOW Logic Level
(Top Thru View)
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
)
−0.5V to +7V
−0.5V to +7V
−0.5V to +7V
)
Supply Voltage Operating (VCC
Supply Voltage Data Retention (VCC
Input Voltage (VIN
Output Voltage (VOUT
)
1.65V to 5.5V
1.5V to 5.5V
0V to 5.5V
)
)
DC Input Diode Current (IIK
)
)
@ VIN < −0.5V
−50 mA
)
0V to VCC
DC Output Diode Current (IOK
)
Operating Temperature (TA)
Input Rise and Fall Time (tr, tf)
VCC @ 1.8V ± 0.15V, 2.5V ± 0.2V
−40°C to +85°C
@ VOUT < −0.5V
−50 mA
± 50 mA
DC Output Current (IOUT
DC VCC/GND Current (ICC/IGND
Storage Temperature (TSTG
)
0 ns/V to 20 ns/V
0 ns/V to 10 ns/V
0 ns to 5 ns/V
250°C/W
)
± 100 mA
V
V
CC @ 3.3V ± 0.3V
CC @ 5.0V ± 0.5V
)
−65°C to +150°C
150°C
Junction Temperature under Bias (TJ)
Junction Lead Temperature (TL);
(Soldering, 10 seconds)
Thermal Resistance (θJA)
260°C
Note 1: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside datasheet specifi-
cations.
Power Dissipation (PD) @ +85°C
250 mW
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
Parameter
Units
Conditions
(V)
Min
Typ
Max
Min
Max
VIH
HIGH Level Input Voltage
1.65 to 1.95 0.75 VCC
0.75 VCC
0.7 VCC
V
V
2.3 to 5.5
1.65 to 1.95
2.3 to 5.5
1.65
2.3
0.7 VCC
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.25 VCC
0.3 VCC
0.25 VCC
0.3 VCC
VOH
1.55
2.2
2.9
4.4
1.29
1.9
2.4
2.3
3.8
1.65
2.3
1.55
2.2
2.9
4.4
1.29
1.9
2.4
2.3
3.8
V
V
V
V
V
IN = VIL
I
OH = −100µA
3.0
3.0
4.5
4.5
1.65
2.3
1.52
2.15
2.80
2.68
4.20
0.0
I
I
I
I
I
OH = −4 mA
OH = −8 mA
OH = −16 mA
OH = −24 mA
OH = −32 mA
3.0
3.0
4.5
VOL
LOW Level Output Voltage
1.65
2.3
0.1
0.1
0.1
0.1
0.24
0.3
0.4
0.55
0.55
±0.1
1
0.1
0.1
0.0
V
IN= VIH
I
OL = 100µA
3.0
0.0
0.1
4.5
0.0
0.1
1.65
2.3
0.08
0.10
0.15
0.22
0.22
0.24
0.3
I
OL = 4 mA
IOL
=
8 mA
3.0
0.4
I
I
I
OL = 16 mA
3.0
0.55
0.55
±1.0
10
OL = 24 mA
OL = 32 mA
4.5
IIN
Input Leakage Current
0 to 5.5
0.0
µA
µA
µA
V
VIN or VOUT = 5.5V
IN = 5.5V, GND
IN = 5.5V, GND
IOFF
ICC
Power Off Leakage Current
Quiescent Supply Current
1.65 to 5.5
1
10
V
3
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AC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
Figure
Symbol
Parameter
Units
Conditions
(V)
1.8 ± 0.15
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
0
Min
2.0
1.2
0.8
0.5
1.2
0.8
Typ
5.4
Max
9.8
5.4
3.8
3.0
4.6
3.7
Min
2.0
1.2
0.8
0.5
1.2
0.8
Max
10
Number
tPLH
,
Propagation Delay
tPHL
3.3
5.8
4.1
3.3
5.0
4.0
C
R
L = 15 pF,
Figures
1, 3
ns
2.5
L = 1 MΩ
2.0
tPLH,
tPHL
CIN
Propagation Delay
3.1
C
L = 50 pF,
L = 500Ω
Figures
1, 3
ns
2.4
R
Input Capacitance
Power Dissipation
Capacitance
2.5
pF
CPD
3.3
13.5
17.5
pF (Note 3)
Figure 2
5.0
Note 3: CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output
loading and operating at 50% duty cycle. (See Figure 2.) CPD is related to ICCD dynamic operating current by the expression:
I
CCD = (CPD)(VCC)(fIN) + (ICCstatic).
AC Loading and Waveforms
CL includes load and stray capacitance
Input PRR = 1.0 MHz; tW = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 3. AC Waveforms
Input = AC Waveform; tr = tf = 1.8 ns;
PRR = 10 MHz; Duty Cycle = 50%
FIGURE 2. ICCD Test Circuit
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4
Tape and Reel Specification
TAPE FORMAT for US8
Package
Tape
Section
Number
Cavities
125 (typ)
3000
Cavity
Status
Empty
Filled
Cover Tape
Status
Designator
Leader (Start End)
Carrier
Sealed
K8X
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
TAPE FORMAT for MicroPak
Package
Tape
Section
Number
Cavities
125 (typ)
3000
Cavity
Status
Empty
Filled
Cover Tape
Status
Designator
Leader (Start End)
Carrier
Sealed
L8X
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
5
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Tape and Reel Specification (Continued)
REEL DIMENSIONS inches (millimeters)
Tape
Size
A
B
C
D
N
W1
W2
W3
7.0
0.059
0.512
0.795
2.165 0.331 + 0.059/−0.000
0.567
W1 + 0.078/−0.039
(W1 + 2.00/−1.00)
8 mm
(177.8) (1.50) (13.00) (20.20) (55.00) (8.40 + 1.50/−0.00)
(14.40)
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6
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
Package Number MAB08A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
8-Lead MicroPak, 1.6 mm Wide
Package Number MAC08A
(Preliminary)
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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