MM74HC86MTC_12 [FAIRCHILD]
Quad 2-Input Exclusive OR Gate;
| 型号： | MM74HC86MTC_12 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad 2-Input Exclusive OR Gate 栅 |
| 文件： | 总7页 (文件大小：445K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2012
MM74HC86
Quad 2-Input Exclusive OR Gate
Description
Features
The MM74HC86 exclusive OR gate utilizes advanced
silicon-gate CMOS technology to achieve operating
speeds similar to equivalent LS-TTL gates, while
maintaining the low power consumption and high noise
immunity characteristic of standard CMOS integrated
circuits. These gates are fully buffered and have a
fanout of 10 LS-TTL loads. The 74HC logic family is
functionally as well as pin-out compatible with the
standard 74LS logic family. All inputs are protected from
damage due to static discharge by internal diode clamps
to VCC and ground.
.
.
.
.
.
Typical Propagation Delay: 9ns
Wide Operating Voltage Range: 2–6V
Low Input Current: 1mA Maximum
Low Quiescent Current: 20mA Max. (74 Series)
Output Drive Capability: 10 LS-TTL Loads
Table 1. Truth Table
Inputs
Outputs
A
L
B
L
Y(1)
L
L
H
L
H
H
H
H
H
L
Note:
1. Y A B AB AB
Figure 1.
Pin Assignments (Top View)
Ordering Information
Operating
Temperature Range
Part Number
Package
Packing Method
MM74HC86M
MM74HC86MX
MM74HC86MTC
MM74HC86MTCX
Note:
Tube
14-Lead, Small Outline Integrated Circuit
(SOIC), JEDEC MS-012, 0.150" Narrow
Tape & Reel
Tube
-40 to +85°C
14-Lead, Thin Shrink Small Outline Package
(TSSOP), JEDEC MO-153, 4.4mm Wide
Tape & Reel
2. Pb-Free package per JEDEC J-STD-020B.
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
Absolute maximum ratings are stress ratings only. Unless otherwise specified, all voltages are referenced to ground.
Symbol
VCC
Parameter
Min.
-0.5
-1.5
-0.5
Max.
7.0
Unit
V
Supply Voltage
VIN
DC Input Voltage
VCC +1.5
VCC +0.5
V
VOUT
IIK, IOK
IOUT
DC Output Voltage
Clamp Diode Current
DC Output Current, per Pin
V
±20
mA
mA
mA
°C
±25
±50
ICC
DC VCC or GND Current, per Pin
Storage Temperature Range
TSTG
TL
-65
+150
260
Lead Temperature (Soldering, 10 Seconds)
Power Dissipation(3, 4)
°C
PD
600
mW
Note:
3. Power dissipation temperature derating — plastic “N” package: -12 mW/°C from 65°C to 85°C.
4. S.O. package only 500mW.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Conditions
Min.
2
Max.
6
Unit
V
VCC
Supply Voltage
VIN, VOUT DC Input or Output Voltage
0
VCC
+85
1000
500
400
V
TA
Operating Temperature Range
Input Rise or Fall Times
-40
°C
VCC = 2.0V
VCC = 4.5V
VCC = 6.0V
tR, tF
ns
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
2
DC Electrical Characteristics(5)
TA=-40 to TA=-55 to
+85°C +125°C
TA=25°C
Symbol
VIH
Parameter
Condition
VCC (V)
Units
Typ.
Guaranteed Limit
2.0
4.5
6.0
2.0
4.5
6.0
1.5
3.15
1.5
3.15
4.2
1.5
Minimum HIGH Level
Input Voltage
3.15
4.2
V
V
4.2
0.5
0.5
0.5
Maximum LOW Level
Input Voltage
VIL
1.35
1.8
1.35
1.8
1.35
1.8
2.0
2.0
1.9
1.9
1.9
VIN = VIH or VIL,
|IOUT| ≤ 20µA
4.5
6.0
4.5
6.0
4.4
5.9
4.4
5.9
4.4
5.9
Minimum HIGH Level
Output Voltage
VOH
V
VIN = VIH or VIL,
|IOUT| ≤ 4.0mA
4.5
6.0
4.2
5.7
3.98
5.48
3.84
5.34
3.70
5.20
VIN = VIH or VIL,
|IOUT| ≤ 5.2mA
2.0
0
0.1
0.1
0.1
VIN = VIH or VIL,
|IOUT| ≤ 20µA
4.5
6.0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
Maximum LOW Level
Output Voltage
VOL
V
VIN = VIH or VIL,
|IOUT| ≤ 4.0mA
4.5
0.2
0.2
0.26
0.33
0.40
VIN = VIH or VIL,
|IOUT| ≤ 5.2mA
6.0
6.0
0.26
±0.1
0.33
±1.0
0.40
±1.0
IIN
ICC
Maximum Input Current VIN = VCC or GND
mA
mA
Maximum Quiescent
Supply Current
VIN = VCC or GND,
OUT = 0mA
6.0
2.0
20
40
I
Note:
5. For a power supply of 5V ±10%, the worst-case output voltages (VOH and VOL) occur for HC at 4.5V. Thus, the
4.5V values should be used when designing with this supply. Worst-case VIH and VIL occur at VCC = 5.5V and
4.5V, respectively. (The VIH values at 5V and 5.5V are 3.5V and 3.85V, respectively.) The worst-case leakage
current (IIN, ICC, and IOZ) occurs for CMOS at the higher voltage, so the 6.0V values should be used.
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
3
AC Electrical Characteristics
TA=-40 to TA=-55 to
TA=25°C
Unit
s
+85°C
+125°C
Symbol
Parameter
Conditions
VCC
Typ.
Guaranteed Limit
CL = 15pF,
tR = tF = 6ns
tPHL, tPLH Maximum Propagation Delay
5.0
2.0
4.5
6.0
2.0
4.5
6.0
12
60
12
10
30
8
20
ns
120
151
30
26
95
19
16
179
tPHL, tPLH Maximum Propagation Delay
24
20
75
15
13
36
30
ns
110
22
CL = 50pF,
tR = tF = 6ns
Maximum Output Rise and
Fall Time
tTLH, tTHL
ns
7
19
Power Dissipation
CPD
25
5
pF
pF
Capacitance (per Gate)(6)
CIN
Maximum Input Capacitance
10
10
10
Note:
6. CPD determines the no-load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic
current consumption, IS = CPD VCC f + ICC
.
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
4
Physical Dimensions
8.75
8.50
0.65
A
7.62
14
8
B
5.60
4.00
3.80
6.00
1.70
1.27
1
7
PIN ONE
INDICATOR
0.51
0.35
1.27
(0.33)
LAND PATTERN RECOMMENDATION
M
0.25
C B A
1.75 MAX
1.50
SEE DETAIL A
1.25
0.25
0.19
0.25
0.10
C
0.10
C
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
0.50
0.25
X 45°
R0.10
R0.10
8°
0°
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.36
0.90
0.50
SEATING PLANE
(1.04)
DETAIL A
SCALE: 20:1
Figure 2.
14-Lead, Small-Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
5
Physical Dimensions
0.43 TYP
0.65
1.65
6.10
0.45
12.00°TOP & BOTTOM
R0.09 min
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
R0.09min
1.00
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6
Figure 3.
14-Lead, Thin-Shrink Small-Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
6
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
7
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FAIRCHILD
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