MBR05S0L [FAIRCHILD]
Dual Mobile-Friendly PWM / PFM Controller; 双移动友好PWM / PFM控制器
| 型号： | MBR05S0L |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual Mobile-Friendly PWM / PFM Controller |
| 文件： | 总15页 (文件大小：387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2010
FAN5234
Dual Mobile-Friendly PWM / PFM Controller
Features
Description
The FAN5234 PWM controller provides high efficiency
and regulation with an adjustable output from 0.9V to
5.5V required to power I/O, chip-sets, memory banks, or
peripherals in high-performance notebook computers,
Wide Input Voltage Range for Mobile Systems:
2V to 24V
Excellent Dynamic Response with Voltage Feed-
Forward and Average-Current-Mode Control
PDAs,
and
internet
appliances.
Synchronous
rectification and hysteretic operation at light loads
contribute to a high efficiency over a wide range of
loads. The Hysteretic Mode of operation can be
disabled if PWM Mode is desired for all load levels.
Efficiency is further enhanced by using the MOSFET’s
Lossless Current Sensing on Low-Side MOSFET or
Precision Over-Current via Sense Resistor
VCC Under-Voltage Lockout
Power-Good Signal
RDS(ON) as a current-sense component.
Light-Load Hysteretic Mode Maximizes Efficiency
300KHz or 600KHz Operation
TSSOP16 Package
Feed-forward ramp modulation, average current mode
control, and internal feedback compensation provide
fast response to load transients. The FAN5234 monitors
these outputs and generates a PGOOD (power-good)
signal when the soft-start is completed and the output is
within ±10% of its set point. A built-in over-voltage
protection prevents the output voltage from going above
120% of the set point. Normal operation is automatically
restored when the over-voltage conditions cease.
Under-voltage protection latches the chip off when the
output drops below 75% of its set value after the soft-
start sequence is completed. An adjustable over-current
function monitors the output current by sensing the
voltage drop across the lower MOSFET.
Applications
Mobile PC Regulator
Handheld PC Power
Related Resources
Application Note — AN-6002 Component
Calculations and Simulation Tools for FAN5234
or FAN5236
Application Note — AN-1029 Maximum Power
Enhancement Techniques for SO-8 Power
MOSFET
Ordering Information
Operating
Part Number
Temperature
Range
Package
Packing Method
FAN5234MTCX
-10 to +85°C
16-Lead, Thin-Shrink Small-Outline Package (TSSOP)
Tape and Reel
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
www.fairchildsemi.com
Typical Application
VIN (BATTERY)
= 2 to 24V
VIN
C1
C5
C2
1
D1
VCC
+5
BOOT
11
4
15
+5
C4
Q1A
FAN5234
HDRV
14
13
R5
L1
ILIM
1.8V at 3.5A
SW
C6
R1
EN
Q1B
LDRV
3
7
R3
SS1
C3
10
PGND
ISNS
+5
9
FPWM
16
8
R2
12
AGND
R4
VSEN
VOUT
6
5
PGOOD
2
Figure 1. 1.18V Output Regulator
Block Diagram
Figure 2. Block Diagram
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
www.fairchildsemi.com
2
Pin Configuration
VIN
PGOOD
EN
FPWM
BOOT
HDRV
SW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ILIM
FA N5234
VOUT
VSEN
SS
ISNS
VCC
LDRV
PGND
AGND
Figure 3. Pin Configuration
Pin Definitions
Pin #
Name
Description
Input Voltage. Connect to main input power source (battery), also used to program
operating frequency for low input voltage operation (see Table 1).
1
VIN
Power-Good Flag. An open-drain output that pulls LOW when VSEN is outside of a ±10%
range of the 0.9V reference.
2
PGOOD
Enable. Enables operation when pulled to logic HIGH. Toggling EN resets the regulator
after a latched fault condition. This is a CMOS input whose state is indeterminate if left open.
3
4
5
EN
ILIM
Current Limit. A resistor from this pin to GND sets the current limit.
Output Voltage. Connect to output voltage. Used for regulation to ensure a smooth
transition during mode changes. When VOUT is expected to exceed VCC, tie this pin to VCC
VOUT
.
Output Voltage Sense. The feedback from the output. Used for regulation as well as
power-good, under-voltage, and over-voltage protection monitoring.
6
7
VSEN
SS
Soft-Start. A capacitor from this pin to GND programs the slew rate of the converter during
initialization, when this pin is charged with a 5µA current source.
Analog Ground. This is the signal ground reference for the IC. All voltage levels are
measured with respect to this pin.
8
AGND
PGND
LDRV
Power Ground. The return for the low-side MOSFET driver output. Connect to the gate of
the low-side MOSFET.
9
Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to the gate of the
low-side MOSFET.
10
Supply Voltage. This pin powers the chip as well as the LDRV buffers. The IC starts to
operate when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops
below 4.3V (UVLO falling).
11
VCC
Current-Sense Input. Monitors the voltage drop across the lower MOSFET or external
sense resistor for current feedback.
12
13
ISNS
SW
Switching Node. Return for the high-side MOSFET driver and a current-sense input.
Connect to source of high-side MOSFET and low-side MOSFET drain.
High-Side Drive. High-side (upper) MOSFET driver output. Connect to the gate of the high-
side MOSFET.
14
15
16
HDRV
BOOT
FPWM
BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 2.
Forced PWM Mode. When logic HIGH, inhibits the regulation from entering Hysteretic
Mode.
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
VCC Supply Voltage
Min.
Max.
6.5
Unit
V
VIN
VIN Supply Voltage
27
V
BOOT, SW, ISNS, HDRV Pins
BOOT to SW Pins
33
V
6.5
V
All Other Pins
-0.3
-10
-65
VCC+0.3
+150
+150
+300
V
TJ
TSTG
TL
Junction Temperature
Storage Temperature
ºC
ºC
ºC
Lead Soldering Temperature, 10 Seconds
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
Parameter
VCC Supply Voltage
Min.
Typ.
Max.
5.25
24
Unit
V
4.75
5.00
VIN
VIN Supply Voltage
V
TA
Ambient Temperature
-10
+85
112
°C
ΘJA
Thermal Resistance, Junction to Ambient
°C/W
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
www.fairchildsemi.com
4
Electrical Characteristics
Recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Power Supplies
LDRV, HDRV Open;
V
SEN Forced Above
850
1300
µA
IVCC
VCC Current
Regulation Point
Shutdown (EN-0)
5
15
30
µA
µA
VIN Pin = Input Voltage
Source
ISINK
VIN Current, Sinking
10
7
20
15
ISOURCE VIN Current, Sourcing
VIN Pin = GND
20
1
µA
µA
ISD
VIN Current, Shutdown
Rising VCC
Falling
4.30
4.10
0.1
4.55
4.27
4.75
4.50
0.5
VUVLO
UVLO Threshold
V
V
VUVLOH UVLO Hysteresis
Oscillator
VIN > 5V
VIN = 0V
VIN = 16V
VIN > 5V
255
510
300
600
2
345
690
fosc
Frequency
KHz
VPP
VRAMP
G
Ramp Amplitude
Ramp Offset
V
V
1.25
0.5
125
250
VIN ≥ 3V
Ramp / VIN Gain
mV/V
1V < VIN < 3V
Reference and Soft-Start
VREF Internal Reference Voltage
ISS
0.891
0.900
5
0.909
V
µA
V
Soft-Start Current
At Startup
VSS
Soft-Start Complete Threshold
1.5
PWM Converter
Load Regulation
I
V
OUT from 0 to 3A,
IN from 2 to 24V
-1
+1
%
ISEN
VSEN Bias Current
50
40
80
55
150
65
nA
VOUT Pin Input Impedance
KΩ
% of Set Point,
2µs Noise Filter
UVLOTSD Under-Voltage Shutdown
ISNS Over-Current Threshold
70
75
80
%
%
115
113
144
172
120
RILIM = 68.5KΩ, Figure 6
% of Set Point,
2µs Noise Filter
UVLO Over-Voltage Threshold
µA
Output Drivers
Sourcing
Sinking
8.0
3.2
8.0
1.5
15.0
4.0
HDRV Output Resistance
LDRV Output Resistance
Ω
Ω
Sourcing
Sinking
15.0
2.4
Continued on following page…
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
www.fairchildsemi.com
5
Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Power-Good Output and Control Pins
% of Set Point, 2µs
Noise Filter
Lower Threshold
86
92
%
%
% of Set Point, 2µs
Noise Filter
Upper Threshold
110
115
PGOOD Output Low
Leakage Current
IPGOOD = 4mA
VPULLUP = 5V
0.5
1
V
µA
Soft-Start Voltage, PGOOD
Enabled
%
VREF2
1.5
EN, FPWM Inputs
VINH
VINL
Input High
Input Low
2
V
V
0.8
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
www.fairchildsemi.com
6
Functional Description
Overview
The FAN5234 is a PWM controller intended for low-
voltage power applications in notebook, desktop, and
sub-notebook PCs. The output voltage of the controller
can be set in the range of 0.9V to 5.5V by an external
resistor divider.
When SS reaches 1.5V, the power-good outputs are
enabled and Hysteretic Mode is allowed. The converter
is forced into PWM Mode during soft-start.
Operation Mode Control
The mode-control circuit changes the converter’s mode
from PWM to Hysteretic and vice versa based on the
voltage polarity of the SW node when the lower
MOSFET is conducting and just before the upper
MOSFET turns on. For continuous inductor current, the
SW node is negative when the lower MOSFET is
conducting and the converters operate in fixed-
frequency PWM Mode, as shown in Figure 4. This
mode achieves high efficiency at nominal load. When
the load current decreases to the point where the
inductor current flows through the lower MOSFET in the
“reverse” direction, the SW node becomes positive and
the mode is changed to Hysteretic, which achieves
higher efficiency at low currents by decreasing the
effective switching frequency.
The synchronous buck converter can operate from an
unregulated DC source (such as a notebook battery),
with voltage ranging from 2V to 24V, or from a regulated
system rail. In either case, the IC is biased from a +5V
source. The PWM modulator uses an average-current-
mode control with input voltage feed-forward for
simplified feedback loop compensation and improved
line regulation. The controller includes integrated
feedback loop compensation that dramatically reduces
the number of external components.
Depending on the load level, the converter can operate
in fixed-frequency PWM Mode or in Hysteretic Mode.
Switch-over from PWM to Hysteretic Mode improves the
converters' efficiency at light loads and prolongs battery
To prevent accidental mode change or "mode chatter,"
the transition from PWM to Hysteretic Mode occurs
when the SW node is positive for eight consecutive
clock cycles (see Figure 4). The polarity of the SW node
is sampled at the end of the lower MOSFET conduction
time. At the transition between PWM and Hysteretic
Mode, both the upper and lower MOSFETs are turned
off. The SW node “rings” based on the output inductor
and the parasitic capacitance on the SW node and
settles out at the value of the output voltage.
run time. In Hysteretic Mode,
a comparator is
synchronized to the main clock to allow seamless
transition between the operational modes and reduced
channel-to-channel interaction.
The Hysteretic Mode of operation can be inhibited
independently using the FPWM pin if variable frequency
operation is not desired.
Oscillator
The boundary value of inductor current, where current
becomes discontinuous, is estimated by the following:
Table 1. Converter Operating Modes
Mode
fSW Converter Power
VIN Pin
Battery (>5V)
100KΩ to GND
GND
⎛
⎜
⎞
⎟
(V − V )V
Battery
300
2 to 24V
IN
OUT
OUT
I
=
(2)
⎜
⎜
⎝
⎟
⎟
⎠
LOAD(DIS)
2f
L
V
Fixed 300 300
Fixed 600 600
<5.5V Fixed
<5.5V Fixed
SW OUT IN
Hysteretic Mode
Conversely, the transition from Hysteretic Mode to
PWM Mode occurs when the SW node is negative for
eight consecutive cycles.
When VIN is from the battery, the oscillator ramp
amplitude is proportional to VIN, providing voltage feed-
forward control for improved loop response. When in
either of the fixed modes, oscillator ramp amplitude is
fixed. The operating frequency is determined according
to the connection on the VIN pin (see Table 1).
A sudden increase in the output current causes a
change from Hysteretic to PWM Mode. This load
increase causes an instantaneous decrease in the
output voltage due to the voltage drop on the output
capacitor ESR. If the load causes the output voltage (as
Initialization and Soft Start
Assuming EN is HIGH, FAN5234 is initialized when VCC
exceeds the rising UVLO threshold. Should VCC drop
below the UVLO threshold, an internal power-on reset
function disables the chip.
presented at VSEN) to drop below the hysteretic
regulation level (20mV below VREF), the mode is
changed to PWM on the next clock cycle.
In Hysteretic Mode, the PWM comparator and the error
amplifier that provide control in PWM Mode are
inhibited and the hysteretic comparator is activated. In
Hysteretic Mode the low-side MOSFET is operated as a
synchronous rectifier, where the voltage across
(VDS(ON)) is monitored and it is switched off when VDS(ON)
goes positive (current flowing back from the load),
allowing the diode to block reverse conduction.
The voltage at the positive input of the error amplifier is
limited by the voltage at the SS pin, which is charged
with 5mA current source. Once CSS has charged to VREF
(0.9V), the output voltage is in regulation. The time it
takes SS to reach 0.9V is:
0.9xCSS
t0.9
=
(1)
5
where t0.9 is in seconds if CSS is in µF.
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
www.fairchildsemi.com
7
VCORE
I L
PWMMode
1
Hysteret icMode
0
2
3
4
5
6
7
8
VCORE
Hysteret icMode
3
PWMMode
I L
0
1
2
4
5
6
7
8
Figure 4. Transitioning between PWM and Hysteretic Mode
The hysteretic comparator causes HDRV turn-on when
the output voltage (at VSEN) falls below the lower
threshold (10mV below VREF) and terminates the PFM
signal when VSEN rises over the higher threshold (5mV
above VREF).
Setting the Current Limit
A ratio of ISNS is also compared to the current
established when a 0.9V internal reference drives the
ILIM pin:
The switching frequency is primarily a function of:
⎛
⎜
⎞
⎟
(100 + R
)
11
SENSE
RLIM
=
x
(5)
⎜
⎜
⎝
⎟
⎟
⎠
Spread between the two hysteretic thresholds
ILOAD
ILOAD
RDS(ON )
Since the tolerance on the current limit is largely
dependent on the ratio of the external resistors, it is
fairly accurate if the voltage drop on the switching node
side of RSENSE is an accurate representation of the load
current. When using the MOSFET as the sensing
element, the variation of RDS(ON) causes proportional
variation in ISNS. This value varies from device to device
and has a typical junction temperature coefficient of
about 0.4%/°C (consult the MOSFET datasheet for
actual values), the actual current limit set point
decreases proportional to increasing MOSFET die
temperature. A factor of 1.6 in the current limit set point
should compensate for all MOSFET RDS(ON) variations,
assuming the MOSFET’s heat sinking keep its
operating die temperature below 125°C.
Output inductor and capacitor ESR
A transition back to PWM Continuous Conduction Mode
or (CCM) occurs when the inductor current rises
sufficiently to stay positive for eight consecutive cycles.
This occurs when:
ΔVHYSTERESIS
⎛
⎜
⎞
⎟
I
=
(3)
LOAD(CCM )
2 ESR
⎝
⎠
where ΔVHYSTERESIS = 15mV and ESR is the equivalent
series resistance of COUT
.
Due to different control mechanisms, the value of the
load current where transition into PWM operation takes
place is typically higher compared to the load level at
which transition into Hysteretic Mode occurs. Hysteretic
Mode can be disabled by setting the FPWM pin HIGH.
Q2
LDRV
Current Processing
The following discussion refers to Figure 6.
RSENSE
ISNS
The current through RSENSE resistor (ISNS) is sampled
shortly after Q2 is turned on. That current is held and
summed with the output of the error amplifier. This
effectively creates a current-mode control loop. The
resistor connected to the ISNS pin (RSENSE) sets the
gain in the current feedback loop. Equation 4 estimates
the recommended value of RSENSE as a function of the
maximum load current (ILOAD(MAX)) and the value of the
MOSFET RDS(ON). RSENSE must be kept higher than
700Ω even if the number calculated comes out less
than 700Ω:
PGND
Figure 5. Improving Current-Sensing Accuracy
I
LOAD(MAX) ×RDS(ON)
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
RSENSE
=
−100
(4)
150μA
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
www.fairchildsemi.com
8
S/H
V to I
0.17pf
17pf
RSENSE
ISNS
in+
in-
1.5M
ISNS
ISNS
300K
LDRV
VSEN
4.14K
PGND
TO
PW M
Reference
and
COM P
RILIM
SS
ILIM
CSS
0.9V
Soft-Start
2.5V
ILIM *11
I2 =
ILIM det.
ILIM
Figure 6. Current Limit / Summing Circuits
More accurate sensing can be achieved by using a
resistor (R1) instead of the RDS(ON) of the FET, as shown
in Figure 5. This approach causes higher losses, but
yields greater accuracy in both VDROOP and ILIMIT. R1 is a
low value (e.g. 10mΩ) resistor.
operating conditions. Since MOSFET switching time
can vary dramatically from type to type and with the
input voltage, the gate control logic provides adaptive
dead time by monitoring the gate-to-source voltages of
both upper and lower MOSFETs. The lower MOSFET
drive is not turned on until the gate-to-source voltage of
the upper MOSFET has decreased to less than
approximately 1V. Similarly, the upper MOSFET is not
turned on until the gate-to-source voltage of the lower
MOSFET has decreased to less than approximately 1V.
This allows a wide variety of upper and lower MOSFETs
to be used without concern for simultaneous conduction
or shoot-through.
Current limit (ILIMIT) should be set high enough to allow
inductor current to rise in response to an output load
transient. Typically, a factor of 1.2 is sufficient. Since
I
LIMIT is a peak current cut-off value, multiply ILOAD(MAX) by
the inductor ripple current (use 25%). For example, in
Figure 1 the target for ILIMIT would be:
I
LIMIT > 1.2 x 1.25 x 1.6 x 3.5A ≈8.5A
(6)
There must be a low-resistance, low-inductance path
between the driver pin and the MOSFET gate for the
adaptive dead-time circuit to work properly. Any delay
along that path subtracts from the delay generated by the
adaptive dead-time circuit and shoot-through may occur.
Duty Cycle Clamp
During severe load increase, the error amplifier output
can go to its upper limit, pushing a duty cycle to almost
100% for a significant amount of time. This could cause
a large increase of the inductor current and lead to a
long recovery from a transient over-current condition or
even to a failure at high input voltages. To prevent this,
the output of the error amplifier is clamped to a fixed
value after two clock cycles if severe output voltage
excursion is detected, limiting maximum duty cycle to:
Frequency Loop Compensation
Due to the implemented current-mode control, the
modulator has a single-pole response with -1 slope at
frequency determined by load. Therefore:
1
f
=
(8)
PO
2πROCO
V
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
2.4
VIN
OUT
DC
=
+
(7)
MAX
V
IN
where RO is load resistance and CO is load capacitance.
This is designed to not interfere with normal PWM
operation. When FPWM is grounded, the duty cycle
clamp is disabled and the maximum duty cycle is 87%.
For this type of modulator, type-2 compensation circuit
is usually sufficient. To reduce the number of external
components and simplify the design task, the PWM
controller has an internally compensated error amplifier.
Figure 7 shows a type two amplifier, its response, and
the responses of a current mode modulator and the
converter. The type-2 amplifier, in addition to the pole at
the origin, has a zero-pole pair that causes a flat gain
region at frequencies between the zero and the pole.
Gate Driver
The adaptive gate control logic translates the internal
PWM control signal into the MOSFET gate drive
signals, providing necessary amplification, level shifting,
and shoot-through protection. It also has functions that
help optimize the IC performance over a wide range of
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
www.fairchildsemi.com
9
Over-Current Sensing
C2
C1
If the circuit's current-limit signal (“ILIM det” in Figure 6)
is HIGH at the beginning of a clock cycle, a pulse-
skipping circuit is activated and HDRV is inhibited. The
circuit continues to pulse skip in this manner for the
next eight clock cycles. If at any time from the ninth to
the sixteenth clock cycle, the ILIM det is again reached,
the over-current protection latch is set, disabling the
chip. If ILIM det does not occur between cycles 9 and 16,
normal operation is restored and the over-current circuit
resets itself.
R2
R1
VIN
EA Out
REF
C
o
n
v
E
r
e
r
o
r
r
t
a
e
m
r
p
.
Modulator
18
14
PGOOD
1
2
8 CLK
0
I
L
f
f
f
P
P0
Z
V
Figure 7. Compensation
= 6kHz
OUT
1
f
f
=
=
(9)
Z
P
2πR2C1
3
1
= 600kHz
(10)
CH1 5.0V
CH2 100mV
M 10.0s
2πR2C2
CH3 2.0AW
This region is also associated with phase “bump” or
reduced phase shift. The amount of phase shift
reduction depends the width of the region of flat gain
and has a maximum value of 90°. To further simplify the
converter compensation, the modulator gain is kept
independent of the input voltage variation by providing
feed-forward of VIN to the oscillator ramp.
Figure 8. Over-Current Protection Waveforms
Over-Voltage / Under-Voltage Protection
Should the VSEN voltage exceed 120% of VREF (0.9V)
due to an upper MOSFET failure or for other reasons,
the over-voltage protection comparator forces LDRV
HIGH. This action actively pulls down the output voltage
and, in the event of the upper MOSFET failure,
eventually blows the battery fuse. As soon as the output
voltage drops below the threshold, the OVP comparator
is disengaged.
The zero frequency, the amplifier high-frequency gain,
and the modulator gain are chosen to satisfy most
typical applications. The crossover frequency appears
at the point where the modulator attenuation equals the
amplifier high-frequency gain. The system designer
must specify the output filter capacitors to position the
load main pole somewhere within one decade lower
than the amplifier zero frequency. With this type of
compensation, plenty of phase margin is achieved due
to zero-pole pair phase “boost.”
This OVP scheme provides a ‘soft’ crowbar function to
tackle severe load transients and does not invert the
output voltage when activated — a common problem for
latched OVP schemes.
Similarly, if an output short-circuit or severe load
transient causes the output to droop to less than 75% of
its regulation set point, the regulator shuts down.
Conditional stability may occur only when the main load
pole is positioned too much to the left side on the
frequency axis due to excessive output filter
capacitance. In this case, the ESR zero placed within
the 10kHz to 50kHz range gives some additional phase
boost. There is an opposite trend in mobile applications
to keep the output capacitor as small as possible.
Over-Temperature Protection
The chip incorporates an over-temperature protection
circuit that shuts the chip down when a die temperature
reaches 150°C. Normal operation is restored at die
temperature below 125°C with internal power on reset
asserted, resulting in a full soft-start cycle.
Protections
The converter output is monitored and protected
against extreme overload, short circuit, over-voltage,
and under-voltage conditions.
A sustained overload on an output sets the PGOOD pin
LOW and latches off the chip. Operation is restored by
cycling the VCC voltage or by toggling the EN pin.
If VOUT drops below the under-voltage threshold, the
chip shuts down immediately.
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
www.fairchildsemi.com
10
Design and Component Selection
Guidelines
Output Capacitor Selection
As an initial step, define operating input voltage range,
output voltage, and minimum and maximum load
currents for the controller.
The output capacitor serves two major functions in a
switching power supply. Along with the inductor, it filters
the sequence of pulses produced by the switcher and it
supplies the load transient currents. The output
capacitor requirements are usually dictated by ESR,
inductor ripple current (ΔI), and the allowable ripple
voltage (ΔV):
For the examples in the following discussion, select
components for:
VIN from 5V to 20V
VOUT = 1.8V at ILOAD(MAX) = 3.5A
ΔV
ΔI
(17)
ESR <
Setting the Output Voltage
ΔV 0.1V
= = 142mΩ
For this example, ESR(MAX)
=
The internal reference is 0.9V. The output is divided
down by a voltage divider to the VSEN pin (for example,
R1 and R2 in Figure 1). The output voltage therefore is:
ΔI 0.7A
In addition, the capacitor's ESR must be low enough to
allow the converter to stay in regulation during a load
step. The ripple voltage due to ESR for the converter in
Figure 1 is 100mVPP. Some additional ripple will appear
due to the capacitance value itself:
V
− 0.9V
0.9V
R2
OUT
=
(11)
R1
To minimize noise pickup on this node, keep the
resistor to GND (R2) below 2K; for example R2 at
1.82K, then choose R5:
ΔI
ΔV =
(18)
COUT ×8× fSW
1.82KΩ
×
0.9
1.8V − 0.9
=1.82K
which is only about 1.5mV for the converter in Figure 1
and can be ignored.
R5 =
(12)
The capacitor must also be rated to withstand the RMS
current, which is approximately 0.3 X (ΔI) or about
210mA for the converter in Figure 1. High-frequency
decoupling capacitors should be placed as close to the
loads as physically possible.
Output Inductor Selection
The minimum practical output inductor value keeps
inductor current just on the boundary of continuous
conduction at some minimum load. The industry
standard practice is to choose the ripple current to be
somewhere from 15% to 35% of the nominal current. At
light-load, the ripple current determines the point where
the converter automatically switches to Hysteretic Mode
to sustain high efficiency. The following equations help
to choose the proper value of the output filter inductor:
Input Capacitor Selection
The input capacitor should be selected by its ripple
current rating. The input RMS current at maximum load
current (IL) is:
ΔV
I
= I D −D2
(19)
OUT
(13)
ΔI = 2 −1
=
RMS
L
MIN
ESR
VOUT
where ΔI is the inductor ripple current, which is chosen
for 20% of the full load current and ΔVOUT is the
maximum output ripple voltage allowed:
where the converter duty cycle;D =
, which for
V
IN
the circuit in Figure 1, with VIN=6, calculates to
IRMS = 1.6A .
V
− V
V
OUT
IN
OUT
L =
×
(14)
Power MOSFET Selection
fSW × ΔI
VIN
Losses in a MOSFET are the sum of its switching (PSW
and conduction (PCOND) losses.
)
For this example, use:
VIN = 20V, VOUT = 1.8V
∆I = 20% x 3.5A = 0.7A
fSW = 300KHz.
In typical applications, the FAN5234 converter's output
voltage is low with respect to its input voltage.
Therefore, the lower MOSFET (Q2) is conducting the
full-load current for most of the cycle. Q2 should
therefore be selected to minimize conduction losses,
(15)
(16)
Therefore;
thereby selecting a MOSFET with low RDS(ON)
.
L ≈8µH
In contrast, the high-side MOSFET (Q1) has a shorter
duty cycle, and its conduction loss has less impact. Q1,
however, sees most of the switching losses, so Q1's
primary selection criteria should be gate charge.
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
www.fairchildsemi.com
11
High-Side Losses
Figure 9 shows a MOSFET's switching interval, with the
upper graph being the voltage and current on the drain-
to-source and the lower graph detailing VGS vs. time
with a constant current charging the gate. The x-axis
therefore is also representative of gate charge (QG).
CISS = CGD + CGS, and it controls t1, t2, and t4 timing.
CGD receives the current from the gate driver during t3
(as VDS is falling). The gate charge (QG) parameters on
the lower graph are either specified or can be derived
from MOSFET datasheets.
The driver’s impedance and CISS determine t2 while t3’s
period is controlled by the driver's impedance and QGD
Since most of tS occurs when VGS = VSP, use a constant
current assumption for the driver to simplify the
calculation of tS:
.
Q
I
Q
G(SW )
G(SW)
ts
=
=
⎛
⎜
⎞
⎟
V
− V
(23)
DRIVER
CC
SP
⎜
⎝
⎟
⎠
R
+ R
GATE
DRIVER
Assuming switching losses are about the same for both
the rising edge and falling edge, Q1's switching losses,
occur during the shaded time when the MOSFET has
voltage across it and current through it.
Most MOSFET vendors specify QGD and QGS. QG(SW)
can be determined as:
QG(SW) = QGD + QGS – QTH
(24)
These losses are given by:
PUPPER = PSW + PCOND
where:
(20)
where QTH is the gate charge required to get the
MOSFET to its threshold (VTH).
For the high-side MOSFET, VDS = VIN, which can be as
high as 20V in a typical portable application. Care
should be taken to include the delivery of the
MOSFET's gate power (PGATE) in calculating the power
dissipation required for the FAN5234:
V
×I
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
DS
L
P
=
× 2× ts
f
(21)
(22)
SW
SW
2
V
⎛
⎞
⎟
⎟
⎠
2
× R
OUT
OUT
⎜
⎜
⎝
P
=
×I
COND
DS(ON )
VIN
P
= Q × V × f
G CC SW
(25)
G
ATE
P
UPPER is the upper MOSFET's total losses and PSW and
PCOND are the switching and conduction losses for a
given MOSFET. RDS(ON) is at the maximum junction
temperature (TJ). tS is the switching period (rise or fall
time) and is t2+t3 in Figure 9.
where QG is the total gate charge to reach VCC
.
Low-Side Losses
Q2 switches on or off with its parallel Schottky diode
conducting; therefore, VDS≈0.5V. Since PSW is
proportional to VDS, Q2's switching losses are negligible
and Q2 is selected based on RDS(ON) only.
C
CGD
CISS
ISS
VDS
Conduction losses for Q2 are given by:
P
=
1−D
)
×I 2 ×R
DS(ON)
(26)
COND
OUT
where RDS(ON) is the RDS(ON) of the MOSFET at the
highest operating junction temperature and
ID
VOUT
D =
is the minimum duty cycle for the converter.
V
IN
QGS
QGD
4.5V
Since DMIN <20% for portable computers, (1-D)≈1 produces
a conservative result, simplifying the calculation.
VSP
VTH
The maximum power dissipation (PD(MAX)) is a function
of the maximum allowable die temperature of the low-
side MOSFET, the ΘJA, and the maximum allowable
ambient temperature rise:
QG(SW)
VGS
t1
t2
t3
t4
t5
Figure 9. Switching Losses and QG
(CISS = CGS || CGD
)
TJ(MAX) − TA(MAX)
P
=
(27)
D(MAX)
VIN
Θ
JA
5V
ΘJA depends primarily on the amount of PCB area that
can be devoted to heat sinking (see AN-1029 —
Maximum Power Enhancement Techniques for SO-8
Power MOSFET for MOSFET thermal information).
CGD
RGATE
RD
HDRV
SW
G
CGS
Figure 10. Drive Equivalent Circuit
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
www.fairchildsemi.com
12
Table 2. Build Of Materials for 1.8V, 3.5A Regulator
Description
Qty.
Ref.
Vendor
Part Number
1
2
1
2
2
2
1
1
1
2
1
1
1
C1
C2, C3
C4
AVX.
TPSV686*025#095
Capacitor 68μF, Tantalum, 25V, ESR 95mΩ
Capacitor 10nF, Ceramic
Capacitor 68μF, Tantalum, 6V, ESR 1.8Ω
Capacitor 0.1μF, Ceramic
Capacitor 330μF, Tantalum, 6V, ESR 100mΩ
1.82KΩ, 1% Resistor
Any
AVX.
TAJV686*006
C5
Any
C6
AVX.
TPSE337*006#0100
R1, R2
R3
Any
Any
1.3KΩ, 1% Resistor
R4
Any
100KΩ, 5% Resistor
R5
Any
56.2KΩ, 1% Resistor
Schottky Diode; 0.5A, 20V
Inductor 8.4μH, 6A
D1
Fairchild Semiconductor
Any
MBR05S0L
L1
Dual MOSFET with Schottky
PWM Controller
Q
Fairchild Semiconductor
Fairchild Semiconductor
FDS6986AS(1)
FAN5234
U1
Note:
1. If currents above 4A continuous are required, use single SO-8 packages. For more information, refer to the
Power MOSFET Selection Section and AN-6002 for design calculations.
Layout Considerations
Switching converters, even during normal operation,
produce short pulses of current that could cause
substantial ringing and be a source of EMI if layout
constrains are not observed.
Keep the wiring traces from the IC to the MOSFET gate
and source as short as possible and capable of
handling peak currents of 2A. Minimize the area within
the gate-source path to reduce stray inductance and
eliminate parasitic ringing at the gate.
There are two sets of critical components in a DC-DC
converter. The switching power components process
large amounts of energy at high rate and are noise
generators. The low-power components responsible for
bias and feedback functions are sensitive to noise.
Locate small critical components, like the soft-start
capacitor and current sense resistors, as close as
possible to the respective pins of the IC.
The
FAN5234
utilizes
advanced
packaging
A multi-layer printed circuit board is recommended.
Dedicate one solid layer for a ground plane. Dedicate
another solid layer as a power plane and break this
plane into smaller islands of common voltage levels.
technologies with lead pitches of 0.6mm. High-
performance analog semiconductors utilizing narrow
lead spacing may require special considerations in
PWB design and manufacturing. It is critical to maintain
proper cleanliness of the area surrounding these
devices. It is not recommended to use any type of rosin
or acid core solder, or the use of flux, in either the
manufacturing or touch up process as these may
contribute to corrosion or enable electro-migration and /
or eddy currents near the sensitive low-current signals.
When chemicals are used on or near the PWB, it is
suggested that the entire PWB be cleaned and dried
completely before applying power.
Notice all the nodes that are subjected to high dV/dt
voltage swing; such as SW, HDRV, and LDRV. All
surrounding circuitry tends to couple the signals from
these nodes through stray capacitance. Do not oversize
copper traces connected to these nodes. Do not place
traces connected to the feedback components adjacent
to these traces. It is not recommended to use high
density interconnect systems, or micro-vias, on these
signals. The use of blind or buried vias should be
limited to the low-current signals only. The use of
normal thermal vias is at the discretion of the designer.
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
www.fairchildsemi.com
13
Physical Dimensions
5.00±0.10
4.55
5.90
4.45 7.35
0.65
4.4±0.1
1.45
5.00
0.11
12°
MTC16rev4
Figure 11. 16-Lead, Thin-Shrink Outline Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
www.fairchildsemi.com
14
© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
www.fairchildsemi.com
15
相关型号：
MBR10-H
Board Connector, 10 Contact(s), 2 Row(s), Male, Right Angle, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator, Receptacle
AUK
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