M74HCT74MTCX [FAIRCHILD]
D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, 4.40 MM, MO-153, TSSOP-14;
| 型号： | M74HCT74MTCX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, 4.40 MM, MO-153, TSSOP-14 触发器 |
| 文件： | 总7页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1984
Revised January 1999
MM74HCT74
Dual D-Type Flip-Flop with Preset and Clear
tected from damage due to static discharge by internal
diode clamps to VCC and ground.
General Description
The MM74HCT74 utilizes advanced silicon-gate CMOS
technology to achieve operation speeds similar to the
equivalent LS-TTL part. It possesses the high noise immu-
nity and low power consumption of standard CMOS inte-
grated circuits, along with the ability to drive 10 LS-TTL
loads.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
This flip-flop has independent data, preset, clear, and clock
inputs and Q and Q outputs. The logic level present at the
data input is transferred to the output during the positive-
going transition of the clock pulse. Preset and clear are
independent of the clock and accomplished by a low level
at the appropriate input.
Features
■ Typical propagation delay: 20 ns
■ Low quiescent current: 40 µA maximum (74HCT Series)
■ Low input current: 1 µA maximum
■ Fanout of 10 LS-TTL loads
The 74HCT logic family is functionally and pin-out compati-
ble with the standard 74LS logic family. All inputs are pro-
■ Meta-stable hardened
Ordering Code:
Order Number Package Number
Package Description
MM74HCT74M
MM74HCT74SJ
M74HCT74MTC
MM74HCT74N
M14A
M14D
MTC14
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
Inputs
Outputs
PR
L
CLR
CLK
X
D
X
X
X
Q
Q
L
H
L
L
H
L
H
X
H
L
X
H
H
(Note 1) (Note 1)
H
H
H
H
H
H
↑
↑
L
H
L
H
L
L
H
X
Q0
Q0
Q0 = the level of Q before the indicated input conditions were established.
Note 1: This configuration is nonstable; that is, it will not persist when pre-
set and clear inputs return to their inactive (HIGH) level.
© 1999 Fairchild Semiconductor Corporation
DS005360.prf
www.fairchildsemi.com
Logic Diagram
www.fairchildsemi.com
2
Absolute Maximum Ratings(Note 2)
(Note 3)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
−0.5 to +7.0V
−1.5 to VCC +1.5V
−0.5 to VCC +0.5V
±20 mA
Min
Max Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
4.5
5.5
V
)
)
)
0
VCC
V
)
±25 mA
Operating Temperature Range (TA)
Input Rise or Fall Times
(tr, tf)
−40
+85
°C
)
±50 mA
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 4)
)
−65°C to +150°C
500
ns
Note 2: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
600 mW
500 mW
Note 3: Unless otherwise specified all voltages are referenced to ground.
S.O. Package only
Note 4: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
Lead Temperature (TL)
(Soldering 10 seconds)
260°C
DC Electrical Characteristics
V
= 5V ±10% (unless otherwise specified)
CC
T
= 25°C
T
= −40° to 85°C
T = −55 to 125°C
A
A
A
Symbol
Parameter
Conditions
Units
Typ
Guaranteed Limits
V
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
V
IH
V
Maximum LOW Level
Input Voltage
0.8
0.8
V
IL
V
Minimum HIGH Level
Output Voltage
V
= V or V
IH IL
OH
IN
|I
|I
|I
| = 20 µA
V
V
− 0.1
V
− 0.1
V − 0.1
CC
V
V
V
OUT
OUT
OUT
CC
CC
CC
| = 4.0 mA, V = 4.5V
4.2
5.2
3.98
4.98
3.84
3.7
CC
| = 4.8 mA, V = 5.5V
4.84
4.7
CC
V
Maximum LOW Level
Voltage
V
= V or V
IH IL
OL
IN
|I
|I
|I
| = 20 µA
0
0.1
0.1
0.1
0.4
V
V
OUT
OUT
OUT
| = 4.0 mA, V = 4.5V
0.2
0.2
0.26
0.26
0.33
0.33
±0.5
CC
| = 4.8 mA, V = 5.5V
0.4
V
CC
I
I
Maximum Input
Current
V
V
V
= V or GND,
±0.0.5
±1.0
µA
IN
IN
IH
CC
or V
IL
Maximum Quiescent
Supply Current
= V or GND
CC
CC
IN
I
= 0 µA
2.0
0.3
20
80
µA
OUT
V
= 2.4V or 0.5V (Note 5)
0.4
0.5
mA
IN
Note 5: This is measured per pin. All other inputs are held at V Ground.
CC
3
www.fairchildsemi.com
AC Electrical Characteristics
V
CC = 5V, TA = 25°C, CL = 15 pF, t = t = 6 ns
r f
Guaranteed
Limit
Symbol
Parameter
Maximum Operating
Conditions
Typ
Units
f
50
30
MHz
MAX
Frequency from Clock
to Q or Q
t
t
, t
Maximum Propagation
18
18
30
30
ns
ns
PHL PLH
Delay Clock to Q or Q
Maximum Propagation
Delay from Preset or
, t
PHL PLH
Clear to Q or Q
t
t
t
t
Minimum Removal Time,
Preset or Clear to Clock
Minimum Setup Time
Data to Clock
20
20
0
ns
ns
ns
ns
REM
S
Minimum Hold Time
Clock to Data
−3
H
Minimum Pulse Width
Clock, Preset or Clear
8
16
W
AC Electrical Characteristics
V
CC = 5.0V ± 10%, CL = 50 pF, t = t = 6 ns unless otherwise specified
r f
T
= 25°C
T = −40° to +85°C
A
A
Symbol
Parameter
Maximum Operating
Conditions
Units
Typ
Guaranteed Limits
f
27
21
MHz
ns
MAX
Frequency
t
t
, t
Maximum Propagation
Delay from Clock to
21
21
35
44
PHL PLH
Q or Q
, t
Maximum Propagation
Delay from Preset or
35
44
ns
PHL PLH
Clear to Q or Q
t
t
t
t
Minimum Removal Time
Preset or Clear to Clock
Minimum Setup Time
Data to Clock
20
20
0
25
25
0
ns
ns
ns
ns
ns
ns
pF
pF
REM
S
Minimum Hold Time
Clock to Data
−3
H
Minimum Pulse Width
Clock, Preset or Clear
Maximum Clock Input
Rise and Fall Time
Maximum Output
Rise and Fall Time
Power Dissipation
Capacitance (Note 6)
Maximum Input
9
16
500
15
20
500
19
W
t , t
r
f
t
, t
THL TLH
C
(per flip-flop)
10
5
PD
IN
C
10
10
Capacitance
2
Note 6:
= C
C
determines the no load dynamic power consumption, P = C
V
f + I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
I
V
f + I
.
S
PD CC
CC
www.fairchildsemi.com
4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
©2020 ICPDF网 联系我们和版权申明