LMV321 [FAIRCHILD]
General Purpose, Low Voltage, Rail-to-Rail Output Amplifiers; 通用，低电压，轨至轨输出放大器
| 型号： | LMV321 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | General Purpose, Low Voltage, Rail-to-Rail Output Amplifiers |
| 文件： | 总16页 (文件大小：537K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
LMV321, LMV358, LMV324
General Purpose, Low Voltage, Rail-to-Rail Output Amplifiers
Features at +2.7V
Description
The LMV321 (single), LMV358 (dual), and LMV324 (quad)
are a low cost, voltage feedback amplifiers that consume only
80µA of supply current per amplifier. The LMV3XX family
is designed to operate from 2.7V (±1.35V) to 5.5V (±2.75V)
supplies. The common mode voltage range extends below the
negative rail and the output provides rail-to-rail performance.
• 80µA supply current per channel
• 1.2MHz gain bandwidth product
• Output voltage range: 0.01V to 2.69V
• Input voltage range: -0.25V to +1.5V
• 1.5V/µs slew rate
• LMV321 directly replaces other industry standard LMV321
amplifiers; available in SC70-5 and SOT23-5 packages
• LMV358 directly replaces other industry standard LMV358
amplifiers; available in MSOP-8 and SOIC-8 packages
• LMV324 directly replaces other industry standard LMV324
amplifiers; available in TSSOP-14 and SOIC-14 packages
• Fully specified at +2.7V and +5V supplies
• Operating temperature range: -40°C to +125°C
The LMV3XX family is designed on a CMOS process and
provides 1.2MHz of bandwidth and 1.5V/µs of slew rate at a
low supply voltage of 2.7V. The combination of low power,
rail-to-rail performance, low voltage operation, and tiny pack-
age options make the LMV3XX family well suited for use in
personal electronics equipment such as cellular handsets,
pagers, PDAs, and other battery powered applications.
Frequency Response vs. C
L
Applications
C
= 200pF
• Low cost general purpose applications
• Cellular phones
C
R
= 200pF
= 225Ω
L
L
s
R
= 0
s
C
R
= 100pF
= 0
• Personal data assistants
• A/D buffer
• DSP interface
L
s
C
= 50pF
L
R
= 0
s
C
R
= 10pF
= 0
L
s
C
= 20pF
L
R
= 0
s
• Smart card readers
• Portable test instruments
• Keyless entry
C
= 2pF
L
+
-
Rs
R
= 0
s
CL 2kΩ
10kΩ
10kΩ
• Infrared receivers for remote controls
• Telephone systems
• Audio applications
• Digital still cameras
• Hard disk drives
0.01
0.1
1
10
Frequency (MHz)
Typical Application
• MP3 players
+Vs
6.8µF
+
0.01µF
+In
+
Out
LMV3XX
-
Rf
Rg
Rev. 1 November 2002
DATA SHEET
LMV321/LMV358/LMV324
Pin Assignments
LMV321
SOT23-5
SC70-5
+In
-Vs
-In
1
2
3
5
4
+Vs
Out
+In
-Vs
-In
1
2
3
5
4
+Vs
Out
+
–
+
–
LMV358
SOIC-8
MSOP-8
Out1
-In1
+In1
-Vs
1
2
3
4
8
7
6
5
+Vs
Out1
-In1
+In1
-Vs
1
2
3
4
8
7
6
5
+Vs
Out2
-In2
+In2
Out2
-In2
+In2
-
-
+
+
-
-
+
+
LMV324
TSSOP-14
SOIC-14
Out1
-In1
1
2
3
4
5
6
7
14 Out4
-In4
Out1
-In1
1
2
3
4
5
6
7
14 Out4
-In4
13
12 +In4
13
12 +In4
+In1
+Vs
+In1
+Vs
11
10
9
11
10
9
-Vs
-Vs
+In2
-In2
+In3
-In3
Out3
+In2
-In2
+In3
-In3
Out3
8
8
Out2
Out2
2
Rev. 1 November 2002
LMV321/LMV358/LMV324
DATA SHEET
Absolute Maximum Ratings
Parameter
Supply Voltages
Min.
0
Max.
+6
Unit
V
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature, 10 seconds
Input Voltage Range
–
+175
+150
+260
°C
°C
°C
V
-65
–
V -0.5 +V +0.5
-
s
s
Recommended Operating Conditions
Parameter
Operating Temperature Range
Power Supply Operating Range
Min.
-40
Max.
+125
5.5
Unit
°C
2.5
V
Electrical Specifications
(T = 25°C, V = +2.7V, G = 2, R = 10kΩ to V /2, R = 10kΩ, V
= V /2; unless otherwise noted)
cc
s
c
s
L
f
o (DC)
Parameter
Conditions
Min.
Typ.
Max.
Unit
AC Performance
Gain Bandwidth Product
Phase Margin
C = 50pF, R = 2kΩ to V /2
1.2
52
17
1.5
36
91
80
MHz
deg
L
L
s
Gain Margin
dB
Slew Rate
V = 1V
o
V/µs
nV/√Hz
dB
pp
Input Voltage Noise
Crosstalk: LMV358
LMV324
>50kHz
100kHz
100kHz
dB
DC Performance
1
Input Offset Voltage
1.7
8
7
mV
µV/°C
nA
Average Drift
2
Input Bias Current
<1
<1
65
80
2
Input Offset Current
nA
1
Power Supply Rejection Ratio
DC
50
dB
1
Supply Current (Per Channel)
120
1.3
µA
Input Characteristics
1
Input Common Mode Voltage Range LO
HI
0
-0.25
1.5
V
V
1
Common Mode Rejection Ratio
50
0.1
70
dB
Output Characteristics
1
Output Voltage Swing
R = 10kΩ to V /2; LO
0.01
2.69
V
V
L
s
1
R = 10kΩ to V /2; HI
2.6
L
s
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Notes:
1. Guaranteed by testing or statistical analysis at +25°C.
2. +IN and -IN are gates to CMOS transistors with typical input bias current of <1nA. CMOS leakage is too small to practically measure.
Rev. 1 November 2002
3
DATA SHEET
LMV321/LMV358/LMV324
Electrical Specifications
(T = 25°C, V = +5V, G = 2, R = 10kΩ to V /2, R = 10kΩ, V
= V /2; unless otherwise noted)
s
c
s
L
f
o (DC)
cc
Parameter
Conditions
Min.
Typ.
Max.
Unit
AC Performance
Gain Bandwidth Product
Phase Margin
C = 50pF, R = 2kΩ to V /2
1.4
73
12
1.5
33
91
80
MHz
deg
L
L
s
Gain Margin
dB
Slew Rate
V/µs
nV/√Hz
dB
Input Voltage Noise
Crosstalk: LMV358
LMV324
>50kHz
100kHz
100kHz
dB
DC Performance
1
Input Offset Voltage
1
6
7
mV
µV/°C
nA
Average Drift
2
Input Bias Current
<1
<1
65
70
100
2
Input Offset Current
nA
1
Power Supply Rejection Ratio
DC
50
50
dB
1
Open Loop Gain
dB
1
Supply Current (Per Channel)
150
3.6
µA
Input Characteristics
1
Input Common Mode Voltage Range LO
HI
0
-0.4
3.8
75
V
V
1
Common Mode Rejection Ratio
50
dB
Output Characteristics
Output Voltage Swing
R = 2kΩ to V /2; LO/HI
0.036 to 4.95
0.013
4.98
V
V
L
s
1
R = 10kΩ to V /2; LO
0.1
L
s
1
R = 10kΩ to V /2; HI
4.9
V
L
s
1
Short Circuit Output Current
sourcing; V = 0V
5
+34
mA
mA
o
sinking; V = 5V
10
-23
o
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Notes:
1. Guaranteed by testing or statistical analysis at +25°C.
2. +IN and -IN are gates to CMOS transistors with typical input bias current of <1nA. CMOS leakage is too small to practically measure.
Package Thermal Resistance
Package
θJA
5 lead SC70
5 lead SOT23
8 lead SOIC
8 lead MSOP
14 lead TSSOP
14 lead SOIC
331.4°C/W
256°C/W
152°C/W
206°C/W
100°C/W
88°C/W
4
Rev. 1 November 2002
LMV321/LMV358/LMV324
DATA SHEET
Typical Operating Characteristics
(T = 25°C, V = +5V, G = 2, R = 10kΩ to V /2, R = 10kΩ, V
= V /2; unless otherwise noted)
cc
s
c
s
L
f
o (DC)
Non-Inverting Freq. Response V = +5V
Inverting Frequency Response V = +5V
s
s
G = 2
G = 1
G = -2
G = -1
G = 10
G = -10
G = -5
G = 5
0.01
0.1
1
10
0.01
0.1
1
10
10
10
Frequency (MHz)
Frequency (MHz)
Non-Inverting Freq. Response V = +2.7V
s
Inverting Freq. Response V = +2.7V
s
G = 1
G = 2
G = -1
G = -2
G = 10
G = -10
G = 5
G = -5
0.01
0.1
1
10
0.01
0.1
1
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. C
Frequency Response vs. R
L
L
C
= 200pF
R
C
R
= 200pF
= 225Ω
L
L
s
= 0
s
C
R
= 100pF
= 0
L
s
R
= 100kΩ
R
= 1kΩ
L
L
C
= 50pF
= 0
L
R
s
C
R
= 10pF
= 0
L
s
C
= 20pF
R
L
R
= 10kΩ
= 0
L
s
C
R
= 2pF
L
+
-
Rs
= 0
s
R
= 2kΩ
L
CL 2kΩ
10kΩ
10kΩ
0.01
0.1
1
10
0.01
0.1
1
Frequency (MHz)
Frequency (MHz)
Small Signal Pulse Response
Large Signal Pulse Response
0.25
0.2
2.5
2
0.15
0.1
1.5
0.1
0.5
0
0.05
0
-0.05
-0.5
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
Time (µs)
Time (µs)
Rev. 1 November 2002
5
DATA SHEET
LMV321/LMV358/LMV324
Typical Operating Characteristics
(T = 25°C, V = +5V, G = 2, R = 10kΩ to V /2, R = 10kΩ, V
= V /2; unless otherwise noted)
s
c
s
L
f
o (DC)
cc
Input Voltage Noise
Total Harmonic Distortion
100
80
70
60
50
40
30
20
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 1V
pp
o
1
10
100
0.1
1000
1
10
100
Frequency (kHz)
Frequency (kHz)
Open Loop Gain & Phase vs. Frequency
0
100
80
R
L
= 2kΩ
= 50pF
L
C
-45
-90
Phase
60
-135
-180
-225
40
20
0
|Gain|
-270
-20
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
6
Rev. 1 November 2002
LMV321/LMV358/LMV324
DATA SHEET
Application Information
+
Rs
General Description
LMV3XX
The LMV3XX family are single supply, general purpose,
voltage-feedback amplifiers that are pin-for-pin compatible
and drop in replacements with other industry standard
LMV321, LMV358, and LMV324 amplifiers. The LMV3XX
family is fabricated on a CMOS process, features a rail-to-rail
output, and is unity gain stable.
-
CL 2kΩ
10kΩ
10kΩ
The typical non-inverting circuit schematic is shown in
Figure 2: Typical Topology for driving a
capacitive load
+Vs
6.8µF
3
2
1
0
+
C
= 50pF
s
L
-1
-2
-3
-4
-5
-6
-7
-8
-9
R
= 0
0.01µF
+In
+
C = 100pF
L
R
= 400Ω
s
Out
LMV3XX
C
= 200pF
s
L
R
= 450Ω
-
Rf
Rg
0.01
0.1
1
10
Frequency (MHz)
Figure 1.
Figure 3: Frequency Response vs C for unity
L
Figure 1: Typical Non-inverting configuration
gain configuration
Power Dissipation
Layout Considerations
The maximum internal power dissipation allowed is directly
related to the maximum junction temperature. If the maximum
junction temperature exceeds 150°C, some performance
degradation will occur. If the maximum junction temperature
exceeds 175°C for an extended time, device failure may occur.
General layout and supply bypassing play major roles in high
frequency performance. Fairchild has evaluation boards to
use as a guide for high frequency layout and as aid in device
testing and characterization. Follow the steps below as a
basis for high frequency layout:
Driving Capacitive Loads
• Include 6.8µF and 0.01µF ceramic capacitors
• Place the 6.8µF capacitor within 0.75 inches of
the power pin
• Place the 0.01µF capacitor within 0.1 inches of
the power pin
The Frequency Response vs C plot on page 4, illustrates the
L
response of the LMV3XX family. A small series resistance (R )
at the output of the amplifier, illustrated in Figure 2, will improve
stability and settling performance. R values in the Frequency
s
s
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce
parasitic capacitance
Response vs C plot were chosen to achieve maximum band-
width with less than 1dB of peaking. For maximum flatness,
L
use a larger R . As the plot indicates, the LMV3XX family
s
• Minimize all trace lengths to reduce series inductances
can easily drive a 200pF capacitive load without a series
resistance. For comparison, the plot also shows the LMV321
driving a 200pF load with a 225Ω series resistance.
Refer to the evaluation board layouts shown in Figure 5 on
page 8 for more information.
Driving a capacitive load introduces phase-lag into the output
signal, which reduces phase margin in the amplifier. The
unity gain follower is the most sensitive configuration. In a
unity gain follower configuration, the LMV3XX family
requires a 450Ω series resistor to drive a 200pF load. The
response is illustrated in Figure 3.
Rev. 1 November 2002
7
DATA SHEET
LMV321/LMV358/LMV324
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of this device:
Evaluation board schematics and layouts are shown in Figures
4 and 5.
Eval Bd
Description
Products
KEB013 Single Channel, Dual Supply,
SOT23-5 for buffer-style pinout
LMV321AS5X
KEB014 Single Channel, Dual Supply,
SC70-5 for buffer-style pinout
LMV321AP5X
KEB006 Dual Channel, Dual Supply,
8 lead SOIC
LMV358AM8X
LMV358AMU8X
LMV324AMTC14X
LMV324AM14X
KEB010 Dual Channel, Dual Supply,
8 lead MSOP
KEB012 Quad Channel, Dual Supply,
14 lead TSSOP
KEB018 Quad Channel, Dual Supply,
14 lead SOIC
Evaluation Board Schematic Diagrams
Figure 4a: LMV321 KEB013 schematic
Figure 4b: LMV321 KEB014 schematic
8
Rev. 1 November 2002
LMV321/LMV358/LMV324
DATA SHEET
Evaluation Board Schematic Diagrams (Continued)
Figure 4c: LMV358 KEB006/KEB010 schematic
Figure 4d: LMV324 KEB012/KEB018 schematic
Rev. 1 November 2002
9
DATA SHEET
LMV321/LMV358/LMV324
LMV321 Evaluation Board Layout
Figure 5a: KEB013 (top side)
Figure 5b: KEB013 (bottom side)
Figure 5c: KEB014 (top side)
Figure 5d: KEB014 (bottom side)
10
Rev. 1 November 2002
LMV321/LMV358/LMV324
DATA SHEET
LMV358 Evaluation Board Layout
Figure 5e: KEB006 (top side)
Figure 5f: KEB006 (bottom side)
Figure 5g: KEB010 (top side)
Figure 5h: KEB010 (bottom side)
Rev. 1 November 2002
11
DATA SHEET
LMV321/LMV358/LMV324
LMV324 Evaluation Board Layout
Figure 5i: KEB012 (top side)
Figure 5j: KEB012 (bottom side)
Figure 5k: KEB018 (top side)
Figure 5l: KEB018 (bottom side)
12
Rev. 1 November 2002
LMV321/LMV358/LMV324
DATA SHEET
LMV321 Package Dimensions
C
L
e
b
SOT23-5
2
SYMBOL
MIN
0.90
0.00
0.90
0.25
0.09
2.80
2.60
1.50
0.35
MAX
1.45
0.15
1.30
0.50
0.20
3.10
3.00
1.75
0.55
A
A1
A2
b
C
D
E
E1
L
C
C
L
E
L
E1
e1
D
e
e1
α
0.95 ref
1.90 ref
α
C
0
10
C
L
NOTE:
1. All dimensions are in millimeters.
Foot length measured reference to flat
foot surface parallel to DATUM ’A’ and lead surface.
2
A
A2
3. Package outline exclusive of mold flash & metal burr.
4. Package outline inclusive of solder plating.
5. Comply to EIAJ SC74A.
A1
6. Package ST 0003 REV A supercedes SOT-D-2005 REV C.
C
L
e
b
L
SC70
SYMBOL
MIN
MAX
e
0.65 BSC
D
b
E
HE
Q1
A2
A1
A
1.80
0.15
1.15
1.80
0.10
0.80
0.00
0.80
0.10
1.10
2.20
0.30
1.35
2.40
0.40
1.00
0.10
1.10
0.18
0.30
C
L
C
L
HE
E
Q1
c
L
C
D
C
L
NOTE:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating.
3. Dimensions are exclusive of mold flashing and metal burr.
4. All speccifications comply to EIAJ SC70.
A
A2
A1
Rev. 1 November 2002
13
DATA SHEET
LMV321/LMV358/LMV324
LMV358 Package Dimensions
SOIC
SOIC-8
MIN
SYMBOL
MAX
0.25
0.46
0.25
4.98
3.99
A1
B
C
D
E
e
0.10
0.36
0.19
4.80
3.81
1.27 BSC
D
7°
e
ZD
C
L
H
h
L
5.80
0.25
0.41
1.52
0
6.20
0.50
1.27
1.72
8
C
E
H
L
A
ZD
A2
0.53 ref
1.57
1.37
Pin No. 1
B
DETAIL-A
L
NOTE:
h x 45°
DETAIL-A
1. All dimensions are in millimeters.
2. Lead coplanarity should be 0 to 0.10mm (.004") max.
3. Package surface finishing:
A1
A2
α
A
(2.1) Top: matte (charmilles #18~30).
(2.2) All sides: matte (charmilles #18~30).
(2.3) Bottom: smooth or matte (charmilles #18~30).
C
4. All dimensions excluding mold flashes and end flash
from the package body shall not exceed o.152mm (.006)
per side(d).
02
MSOP
e
S
MSOP-8
SYMBOL
A
MIN
MAX
–
1.10
t1
A1
A2
D
D2
E
E1
E2
E3
E4
R
R1
t1
t2
b
b1
c
c1
01
02
03
L
L1
aaa
bbb
ccc
e
0.10
0.86
3.00
2.95
4.90
3.00
2.95
0.51
0.51
0.15
0.15
0.31
0.41
0.33
0.30
0.18
±0.05
±0.08
±0.10
±0.10
±0.15
±0.10
±0.10
±0.13
±0.13
+0.15/-0.06
+0.15/-0.06
±0.08
±0.08
+0.07/-0.08
±0.05
±0.05
+0.03/-0.02
±3.0°
±3.0°
±3.0°
±0.15
–
R1
E/2 2X
t2
– H –
R
Gauge
Plane
3
7
2
E1
0.25mm
01
L
03
– B –
E3
E4
L1
Detail A
b
ccc
A B C
1
2
Scale 40:1
c
c1
2
4
6
b1
Detail A
D2
A2
E2
Section A - A
0.15
3.0°
5
A
A
12.0°
12.0°
0.55
0.95 BSC
0.10
0.08
0.25
0.65 BSC
0.525 BSC
– A –
b
A
E1
E
bbb M A B C
A1
aaa
A
D
3
4
–
–
–
–
NOTE:
S
–
1
2
3
4
5
6
7
All dimensions are in millimeters (angle in degrees), unless otherwise specified.
Datums – B – and – C – to be determined at datum plane – H – .
Dimensions "D" and "E1" are to be determined at datum – H – .
Dimensions "D2" and "E2" are for top package and dimensions "D" and "E1" are for bottom package.
Cross sections A – A to be determined at 0.13 to 0.25mm from the leadtip.
Dimension "D" and "D2" does not include mold flash, protrusion or gate burrs.
Dimension "E1" and "E2" does not include interlead flash or protrusion.
14
Rev. 1 November 2002
LMV321/LMV358/LMV324
DATA SHEET
LMV324 Package Dimensions
7
6
– B –
e
TSSOP
N
5
(b)
2X E/2
TSSOP-14
8
SYMBOL
A
MIN
NOM
MAX
1.10
0.15
0.95
0.75
–
1.0 DIA
E1 E
c
c1
–
–
–
0.90
0.60
–
–
–
0.22
–
–
A1
A2
L
R
R1
b
0.05
0.85
0.50
0.09
0.09
0.19
0.19
0.09
0.09
0°
1.0
b1
1
2
3
ddd C B A
SECTION AA
2X
6
e /2
9
N/2 TIPS
1.0
–
0.30
0.25
0.20
0.16
8°
b1
c
ccc
D
c1
01
L1
aaa
bbb
ccc
ddd
e
A2
A
8
3
7
– A –
–
aaa C
1.0 REF
0.10
0.10
0.05
0.20
0.65 BSC
12° REF
12° REF
5.00
4.40
6.4 BSC
0.65 BSC
14
– C –
b
NX A1
(02)
(0.20)
M
bbb C B A
R1
02
03
D
– H –
R
GAGE
PLANE
4.90
4.30
5.10
4.50
E1
E
e
10
(03)
A
A
0.25
01
L
N
(L1)
NOTES:
1
2
3
4
5
All dimensions are in millimeters (angle in degrees).
Dimensioning and tolerancing per ASME Y14.5–1994.
Dimensions "D" does not include mold flash, protusions or gate burrs. Mold flash protusions or gate burrs shall not exceed 0.15 per side .
Dimension "E1" does not include interlead flash or protusion. Interlead flash or protusion shall not exceed 0.25 per side.
Dimension "b" does not include dambar protusion. Allowable dambar protusion shall be 0.08mm total in excess of the "b" dimension at maximum
material condition. Dambar connot be located on the lower radius of the foot. Minimum space between protusion and adjacent lead is 0.07mm
for 0.5mm pitch packages.
6
7
8
9
Terminal numbers are shown for reference only.
Datums – A – and – B – to be determined at datum plane – H – .
Dimensions "D" and "E1" to be determined at datum plane – H – .
This dimensions applies only to variations with an even number of leads per side. For variation with an odd number of leads per side, the "center"
lead must be coincident with the package centerline, Datum A.
10 Cross sections A – A to be determined at 0.10 to 0.25mm from the leadtip.
SOIC
SOIC-14
MIN
SYMBOL
MAX
.0098
.018
.0098
.344
A1
B
C
D
E
e
.0040
.014
.0075
.337
.150
.050 BSC
D
7°
e
ZD
C
L
.157
H
h
L
.2284
.0099
.016
.060
0
.2440
.0196
.050
.068
8
C
E
H
L
A
ZD
A2
0.20 ref
.062
.054
Pin No. 1
B
DETAIL-A
L
NOTE:
1. All dimensions are in inches.
h x 45°
DETAIL-A
2. Lead coplanarity should be 0 to 0.10mm (.004") max.
3. Package surface finishing:
A1
A
A2
α
(2.1) Top: matte (charmilles #18~30).
(2.2) All sides: matte (charmilles #18~30).
(2.3) Bottom: smooth or matte (charmilles #18~30).
C
4. All dimensions excluding mold flashes and end flash
from the package body shall not exceed o.152mm (.006)
per side (d).
Rev. 1 November 2002
15
DATA SHEET
LMV321/LMV358/LMV324
Ordering Information
Model
Part Number
LMV321AP5X
LMV321AS5X
LMV358AM8X
LMV358AMU8X
Package Container
Pack Qty
3000
LMV321
LMV321
LMV358
LMV358
SC70-5
SOT23-5
SOIC-8
Reel
Reel
Reel
Reel
Reel
Reel
3000
2500
MSOP-8
3000
LMV324 LMV324AMTC14X TSSOP
LMV324 LMV324AM14X SOIC
2500
2500
Temperature range for all parts: -40°C to +125°C.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN.
FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY
LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE
PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1.
Life support devices or systems are devices or systems which, (a) are intended for
surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury of the user.
2.
A critical component in any component of a life support device or system whose failure
to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
© 2002 Fairchild Semiconductor Corporation
相关型号：
LMV321A-Q1
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