KA393A_11 [FAIRCHILD]
Dual Differential Comparator;
| 型号： | KA393A_11 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual Differential Comparator |
| 文件： | 总7页 (文件大小：625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2011
KA393 / KA393A, KA2903
Dual Differential Comparator
Features
Description
The KA393 / KA393A / KA2903 series consists of two
independent voltage comparators designed to operate
from a single power supply over a wide voltage range.
.
.
.
Single Supply Operation: 2V to 36V
Dual Supply Operation: ±1V to ±18V
Allow Comparison of Voltages Near Ground
Potential
.
.
.
.
.
Low Current Drain: 800µA Typical
Compatible with all Forms of Logic
Low Input Bias Current: 25nA Typical
Low Input Offset Current: ±5nA Typical
Low Offset Voltage: ±1mV Typical
Figure 1. DIP Package Figure 2. SOIC Package
Figure 3. Block Diagram
Figure 4. Schematic
Ordering Information
Part Number
KA393
Operating Temperature Range
Package
Packing Method
Tube
0 to 70°C
0 to 70°C
0 to 70°C
0 to 70°C
-40 to 85°C
8-Lead DIP
KA393A
Tube
KA393DTF
KA393ADTF
KA2903DTF
Tape and Reel
Tape and Reel
Tape and Reel
8-Lead SOIC
© 2001 Fairchild Semiconductor Corporation
KA393 / KA2903 • Rev. 1.0.3
www.fairchildsemi.com
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
36
Unit
V
VCC
Power Supply Voltage
±18
VI(DIFF) Differential Input Voltage
36
V
VI
Input Voltage
-0.3
+36.0
V
Output Short Circuit to GND
Continuous
1040
8-DIP
8-SOIC
Power Dissipation,
TA = 25°C
PD
mW
480
+70
KA393 / KA393A
KA2903
0
TOPR
TSTG
RΘJA
Operating Temperature
Storage Temperature
°C
°C
-40
-65
+85
+150
120
8-DIP
Thermal Resistance,
Junction-to-Ambient
°C/W
8-SOIC
260
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
1000
2000
Electrostatic Discharge
Capability
ESD
V
© 2001 Fairchild Semiconductor Corporation
KA393 / KA2903 • Rev. 1.0.3
www.fairchildsemi.com
2
Electrical Characteristics
VCC = 5V and TA = 25°C, Unless otherwise specified.
Symbol
Parameter
Conditions
VO(P) =1.4V, RS =0Ω
Min.
Typ.
Max.
±5
Unit
±1
KA393
VCM= 0 to1.5V, TA= 0 to +70°C
±9
Input Offset
Voltage
VIO
mV
VO(P) =1.4V, RS =0Ω
±1
±5
65
±2
KA393A
VCM= 0 to1.5V, TA= 0 to +70°C
TA=25°C
±4
±50
IIO
Input Offset Current
Input Bias Current
nA
nA
V
TA= 0 to +70°C
TA=25°C
±150
250
IBIAS
VI(R)
ICC
TA= 0 to +70°C
TA=25°C
400
0
0
VCC-1.5
VCC-2.0
1.0
Input Common-Mode Voltage
Range
TA= 0 to +70°C
RL = ∞, VCC = 5V
RL = ∞, VCC = 30V
0.6
0.8
Supply Current
mA
2.5
VCC =15V, RL≥15KΩ,
(for Large VO(P-P) Swing)
VG
Voltage Gain
50
6
200
350
V/mV
ns
VI =TTL Logic Swing VREF =1.4V,
VRL =5V, RL =5.1KΩ
tLRES
Large Signal Response Time
tRES
Response Time
VRL =5V, RL =5.1KΩ
1.4
18
µs
ISINK
Output Sink Current
VI(-) ≥ 1V, VI(+) = 0V, VO(P) ≤ 1.5V
VI(-) ≥ 1V, VI(+) =0V
mA
160
400
700
VSAT
Output Saturation Voltage
mV
ISINK=4mA, TA= 0 to +70°C
VI(-) = 0V, VI(+) = 1V, VO(P) = 5V
VI(-) = 0V, VI(+) = 1V, VO(P) = 30V
0.1
nA
µA
IO(LKG) Output Leakage Current
1.0
KA2903
VO(P) =1.4V, RS =0Ω
VCM= 0 to1.5V, TA= -40 to +85°C
TA=25°C
±1
±9
±7
±15
VIO
Input Offset Voltage
Input Offset Current
Input Bias Current
mV
nA
nA
V
±5
±50
IIO
TA= -40 to +85°C
TA=25°C
±50
65
±200
250
IBIAS
VI(R)
ICC
TA= -40 to +85°C
TA=25°C
500
0
0
VCC-1.5
VCC-2.0
1.0
Input Common-Mode Voltage
Range
TA= -40 to +85°C
RL = ∞, VCC = 5V
RL = ∞, VCC = 30V
0.6
1.0
Supply Current
mA
2.5
VCC =15V, RL≥15KΩ,
(for Large VO(P-P) Swing)
VG
Voltage Gain
25
6
100
350
V/mV
ns
VI =TTL Logic Swing VREF =1.4V,
tLRES
Large Signal Response Time
VRL =5V, RL =5.1KΩ
tRES
Response Time
VRL =5V, RL =5.1KΩ
1.5
16
µs
ISINK
Output Sink Current
VI(-) ≥ 1V, VI(+) = 0V, VO(P) ≤ 1.5V
mA
V
I(-) ≥ 1V, VI(+) =0V
ISINK=4mA, TA= -40 to +85°C
I(-) = 0V, VI(+) = 1V, VO(P) = 5V
160
400
700
VSAT
Output Saturation Voltage
mV
V
0.1
nA
µA
IO(LKG) Output Leakage Current
VI(-) = 0V, VI(+) = 1V, VO(P) = 30V
1.0
© 2001 Fairchild Semiconductor Corporation
KA393 / KA2903 • Rev. 1.0.3
www.fairchildsemi.com
3
Typical Performance Characteristics
Figure 5. Supply Current vs. Supply Voltage
Figure 6. Input Current vs. Supply Voltage
Figure 7. Output Saturation Voltage
vs. Sink Current
Figure 8. Response Time for Various Input
Overdrive-Negative Transitions
Figure 9. Response Time for Various Input
Overdrive-Positive Transitions
© 2001 Fairchild Semiconductor Corporation
KA393 / KA2903 • Rev. 1.0.3
www.fairchildsemi.com
4
Physical Dimensions
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.51
0.33
0.10 C
x 45°
OPTION A - BEVEL EDGE
0.50
0.25
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
0.40
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
DETAIL A
SCALE: 2:1
Figure 10.8-Lead, Small-Outline Integrated Circuit (SOIC), JEDEC MS-012, .150" Narrow Body
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2001 Fairchild Semiconductor Corporation
KA393 / KA2903 • Rev. 1.0.3
www.fairchildsemi.com
5
Physical Dimensions
.400 10.15
.373 9.46
A
[
]
.036 [0.9 TYP]
(.092) [Ø2.337]
PIN #1
(.032) [R0.813]
PIN #1
.250±.005 [6.35±0.13]
B
TOP VIEW
OPTION 1
TOP VIEW
OPTION 2
.070 1.78
.310±.010 [7.87±0.25]
.045
[ ]
1.14
.130±.005 [3.3±0.13]
.210 MAX
[5.33]
7° TYP
7° TYP
C
.015 MIN
[0.38]
.140 3.55
.125 [3.17]
.021 0.53
.015 0.37
.300
[7.62]
[
]
.001[.025]
C
.100
[2.54]
.430 MAX
[10.92]
.060 MAX
[1.52]
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MS-001,
VARIATIONS BA
B. CONTROLING DIMENSIONS ARE IN INCHES
REFERENCE DIMENSIONS ARE IN MILLIMETERS
+.005
-.000
+0.127
-0.000
.010
0.254
[
]
C. DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED
.010 INCHES OR 0.25MM.
D. DOES NOT INCLUDE DAMBAR PROTRUSIONS.
DAMBAR PROTRUSIONS SHALL NOT EXCEED
.010 INCHES OR 0.25MM.
E. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M-1994.
N08EREVG
Figure 1. 8-Lead, DIP, JEDEC MS-001, .300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2001 Fairchild Semiconductor Corporation
KA393 / KA2903 • Rev. 1.0.3
www.fairchildsemi.com
6
© 2001 Fairchild Semiconductor Corporation
KA393 / KA2903 • Rev. 1.0.3
www.fairchildsemi.com
7
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