ITF87012SVT1 [FAIRCHILD]
Power Field-Effect Transistor, 6A I(D), 20V, 0.038ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, MO-193AA, PLASTIC, TSOP-6;
| 型号： | ITF87012SVT1 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Power Field-Effect Transistor, 6A I(D), 20V, 0.038ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, MO-193AA, PLASTIC, TSOP-6 开关 光电二极管 晶体管 |
| 文件： | 总13页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ITF87012SVT
TM
Data Sheet
July 2000
File Number 4810.3
6A, 20V, 0.035 Ohm, N-Channel,
2.5V Specified Power MOSFET
Features
• Ultra Low On-Resistance
- r
- r
- r
= 0.035Ω, VGS = 4.5V
DS(ON)
DS(ON)
DS(ON)
Packaging
= 0.038Ω, VGS = 4.0V
= 0.045Ω, VGS = 2.5V
TSOP-6
• 2.5 V Gate Drive Capability
• Small Profile Package
4
1
2
3
• Gate to Source Protection Diode
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.intersil.com
• Peak Current vs Pulse Width Curve
Symbol
• Transient Thermal Impedance Curve vs Board Mounting
Area
DRAIN(1)
DRAIN(2)
DRAIN(6)
DRAIN(5)
• Switching Time vs R
GS
Curves
Ordering Information
GATE(3)
SOURCE(4)
PART NUMBER
PACKAGE
TSOP-6 (SC-95)
BRAND
ITF87012SVT
012
NOTE: When ordering, use the entire part number. ITF87012SVT is
available only in tape and reel.
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
A
ITF87012SVT
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
20
20
V
V
V
DSS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
±12
GS
Drain Current
o
Continuous (T = 25 C, V
= 4.5V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
6.0
5.5
3.5
3.0
Figure 4
A
A
A
A
A
A
GS
D
D
o
Continuous (T = 25 C, V
A
GS
o
Continuous (T = 100 C, V
= 4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 2.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
A
GS
D
o
Continuous (T = 100 C, V
A
GS
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
16
W
mW/ C
D
o
o
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
-55 to 150
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
Package Body for 10s, See Techbrief TB370. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
NOTES:
o
o
1. T = 25 C to 125 C.
J
o
2
2
2. 62.5 C/W measured using FR-4 board with 0.40 in (258.1 mm ) copper pad at 2 second.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
SABER™ is a trademark of Analogy Inc., PSPICE® is a registered trademark of MicroSim Corporation.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
ITF87012SVT
o
Electrical Specifications T = 25 C, Unless Otherwise Specified
A
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
BV
DSS
I
= 250µA, V
= 0V (Figure 11)
= 0V
20
-
-
-
-
-
V
D
GS
I
V
= 20V, V
10
µA
uA
DSS
DS
GS
GS
I
V
= ±12V
-
±10
GSS
V
V
= V , I = 250µA (Figure 10)
0.5
-
1.5
V
Ω
Ω
Ω
GS(TH)
GS
DS
D
GS
GS
GS
r
I
I
I
= 6.0A, V
= 3.5A, V
= 3.0A, V
= 4.5V (Figures 8, 9)
= 4.0V (Figure 8)
= 2.5V (Figure 8)
-
-
-
0.028
0.029
0.037
0.035
0.038
0.045
DS(ON)
D
D
D
THERMAL SPECIFICATIONS
2
2
o
Thermal Resistance Junction to
Ambient
R
Pad Area = 0.40 in (258.1 mm ) (Note 2)
-
-
-
-
-
-
62.5
198.2
218.4
C/W
θJA
2
2
o
Pad Area = 0.0163 in (10.54 mm ) (Figure 20)
C/W
2
2
o
Pad Area = 0.0056 in (3.60 mm ) (Figure 20)
C/W
SWITCHING SPECIFICATIONS (V
Turn-On Delay Time
Rise Time
= 2.5V)
GS
t
V
V
R
= 10V, I = 3.0A
D
= 2.5V,
= 15 Ω
-
-
-
-
79
-
-
-
-
ns
ns
ns
ns
d(ON)
DD
GS
t
315
154
188
r
GS
(Figures 14, 18, 19)
Turn-Off Delay Time
Fall Time
t
d(OFF)
t
f
SWITCHING SPECIFICATIONS (V
Turn-On Delay Time
Rise Time
= 4.5V)
GS
t
V
V
R
= 10V, I = 6.0A
D
= 4.5V,
= 16 Ω
-
-
-
-
42
-
-
-
-
ns
ns
ns
ns
d(ON)
DD
GS
t
142
236
200
r
GS
(Figures 15, 18, 19)
Turn-Off Delay Time
Fall Time
t
d(OFF)
t
f
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 4.5V
= 0V to 2V
V
= 10V,
-
-
-
-
-
7.7
4.0
-
-
-
-
-
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
DD
= 5.5A,
I
I
D
Gate Charge at 2V
Q
g(2)
= 1.0mA
g(REF)
Threshold Gate Charge
Q
= 0V to 0.5V
(Figures 13, 16, 17)
0.30
1.1
g(TH)
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
gs
gd
Q
2.7
C
V
= 10V, V = 0V,
GS
-
-
-
655
227
118
-
-
-
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 12)
Output Capacitance
C
C
OSS
RSS
Reverse Transfer Capacitance
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
TYP
0.84
22
MAX
UNITS
V
V
I
I
I
= 5.5A
-
-
-
-
-
-
SD
SD
SD
SD
t
= 5.5A, dI /dt = 50A/µs
SD
ns
rr
Reverse Recovered Charge
Q
= 5.5A, dI /dt = 50A/µs
SD
6.1
nC
RR
2
ITF87012SVT
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
0
8
o
V
= 4.5V, R
θJA
= 62.5 C/W
GS
6
4
2
0
o
V
= 2.5V, R
50
= 218.4 C/W
GS
θJA
0
25
50
75
100
125
150
25
75
100
125
150
o
o
T , AMBIENT TEMPERATURE ( C)
T , AMBIENT TEMPERATURE ( C)
A
A
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
3
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
o
R
= 62.5 C/W
0.1
θJA
0.05
0.02
0.01
0.1
P
DM
t
1
0.01
0.001
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
PEAK T = P
x Z
x R + T
J
DM
θJA
θJA A
-5
-4
-3
-2
-1
0
1
2
3
10
10
10
10
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
100
o
o
R
= 62.5 C/W
θJA
T
= 25 C
A
FOR TEMPERATURES
ABOVE 25 C DERATE PEAK
o
CURRENT AS FOLLOWS:
150 - T
V
= 4.5V
= 2.5V
A
I = I
GS
25
125
V
GS
10
1
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-5
10
-4
10
-3
10
-2
10
-1
10
0
1
2
3
10
10
10
10
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
3
ITF87012SVT
Typical Performance Curves (Continued)
200
20
15
10
SINGLE PULSE
PULSE DURATION = 80µs
T
= MAX RATED
= 25 C
J
100
o
DUTY CYCLE = 0.5% MAX
T
A
V
= 15V
DD
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
o
5
0
T
= 150 C
LIMITED BY r
DS(ON)
J
o
T
= 25 C
J
o
R
= 62.5 C/W
10ms
θJA
o
T
= -55 C
J
1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
50
0.5
1.0
1.5
2.0
2.5
3.0
V
DS
V
, GATE TO SOURCE VOLTAGE (V)
GS
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. TRANSFER CHARACTERISTICS
20
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 4.5V
= 3V
GS
V
GS
15
80
60
40
20
I
= 6A
D
V
= 2.5V
GS
10
5
V
= 2V
GS
I
= 3A
D
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 1.5V
o
GS
T
= 25 C
A
0
0
0.5
1.0
1.5
2.0
1
2
3
4
5
V
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
, GATE TO SOURCE VOLTAGE (V)
DS
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
1.6
1.4
1.2
1.0
1.4
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 4.5V, I = 6A
V
= V , I = 250µA
DS
GS D
GS
D
1.2
1.0
0.8
0.6
0.4
0.8
0.6
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4
ITF87012SVT
Typical Performance Curves (Continued)
1.10
1500
I
= 250µA
D
C
= C + C
GS GD
ISS
1000
1.05
1.00
C
C
+ C
OSS
DS GD
C
= C
GD
0.95
0.90
RSS
100
50
V
= 0V, f = 1MHz
GS
-80
-40
0
40
80
120
160
0.1
1.0
, DRAIN TO SOURCE VOLTAGE (V)
10
20
o
T , JUNCTION TEMPERATURE ( C)
J
V
DS
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
500
5
V
= 2.5V, V = 10V, I = 3.0A
DD D
GS
V
= 10V
DD
400
300
200
4
3
2
1
0
t
r
t
f
WAVEFORMS IN
DESCENDING ORDER:
100
0
I
I
= 5.5A
= 3A
t
D
D
t
d(ON)
d(OFF)
0
2
4
6
8
10
0
10
20
30
40
50
R
, GATE TO SOURCE RESISTANCE (Ω)
Q , GATE CHARGE (nC)
GS
g
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
400
t
d(OFF)
V
= 4.5V, V = 10V, I = 6A
DD D
GS
300
200
t
f
t
r
100
0
t
d(ON)
0
10
20
30
40
50
R
, GATE TO SOURCE RESISTANCE (Ω)
GS
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5
ITF87012SVT
Test Circuits and Waveforms
V
DS
R
L
V
Q
DD
g(TOT)
V
DS
V
= 4.5V
GS
V
GS
+
-
Q
g(2)
V
DD
V
= 2V
V
GS
GS
DUT
V
= 0.5V
GS
I
g(REF)
0
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
t
t
ON
OFF
t
d(OFF)
t
R
L
d(ON)
t
t
f
V
r
DS
V
DS
+
90%
90%
V
GS
V
GS
-
0V
10%
10%
0
DUT
R
GS
90%
50%
V
GS
50%
PULSE WIDTH
10%
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. SWITCHING TIME WAVEFORM
Thermal Resistance vs Mounting Pad Area
The maximum rated junction temperature, T , and the thermal
resistance of the heat dissipating path determines the maximum
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
JM
allowable device power dissipation, P , in an application.
DM
o
Therefore the application’s ambient temperature, T ( C), and
A
2. The number of copper layers and the thickness of the board.
3. The use of external heat sinks.
o
thermal resistance R
( C/W) must be reviewed to ensure
θJA
that T is never exceeded. Equation 1 mathematically
represents the relationship and serves as the basis for
establishing the rating of the part.
JM
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the duty
cycle and the transient thermal response of the part, the
board and the environment they are in.
(T
– T )
JM
Z
A
(EQ. 1)
P
= ------------------------------
DM
θJA
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 20 defines the
In using surface mount devices such as the TSOP-6
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P
complex and influenced by many factors:
R
for the device as a function of the top copper
θJA
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
is
DM
6
ITF87012SVT
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
Displayed on the curve are R
θJA
values listed in the Electrical
Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
260
resistance and ultimately the power dissipation, P
.
DM
R
= 120.6- 18.9 * ln (AREA)
θJA
240
Thermal resistances corresponding to other copper areas can
be obtained from Figure 20 or by calculation using Equation 2.
o
2
220
200
218.4 C/W - 0.0056in
R
is defined as the natural log of the area times a coefficient
θJA
o
2
198.2 C/W - 0.0163in
added to a constant. The area, in square inches is the top
copper area including the gate and source pads.
180
160
(EQ. 2)
R
= 120.6 – 18.9 • ln(Area)
θJA
140
120
The transient thermal impedance (Z
θJA
) is also effected by
varied top copper board area. Figure 21 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
0.01
0.001
0.1
2
1.0
AREA, TOP COPPER AREA (in )
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA
200
COPPER BOARD AREA - DESCENDING ORDER
2
0.02 in
2
0.05 in
0.10 in
0.25 in
0.40 in
160
120
80
40
0
2
2
2
-1
0
1
2
3
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA
7
ITF87012SVT
PSPICE Electrical Model
.SUBCKT ITF87012SVT 2 1 3 ;
REV 25 Jan 2000
CA 12 8 11.00e-10
CB 15 14 9.50e-10
CIN 6 8 5.25e-10
LDRAIN
DPLCAP
10
5
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 5 DPLCAPMOD
DRAIN
2
RLDRAIN
DBREAK
RSLC1
51
RSLC2
+
5
ESLC
11
51
EBREAK 11 7 17 18 27.41
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
-
50
+
-
17
18
-
DBODY
RDRAIN
16
EBREAK
6
ESG
8
EVTHRES
+
21
+
-
19
8
MWEAK
LGATE
EVTEMP
RGATE
9
GATE
1
6
IT 8 17 1
+
-
18
22
MMED
20
LDRAIN 2 5 1.00e-9
LGATE 1 9 1.04e-9
LSOURCE 3 7 1.29e-10
MSTRO
8
RLGATE
DESD1
91
DESD2
LSOURCE
CIN
SOURCE
3
7
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RSOURCE
RLSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.00e-3
RGATE 9 20 118
RLDRAIN 2 5 10
RLGATE 1 9 9 10.4
RLSOURCE 3 7 1.29
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 17.00e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S2A
RBREAK
12
15
13
14
13
17
18
8
RVTEMP
19
-
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*175),2))}
.MODEL DBODYMOD D (IS = 3.48e-11 IKF = 0.15 XT I= 0.18 RS = 1.47e-2 TRS1 = 1.25e-3 TRS2 = 0 CJO = 3.67e-10 TT = 2.20e-8 M = 0.52)
.MODEL DBREAKMOD D (RS = 9.52e-2 TRS1 = 1.05e-3 TRS2 = 1.13e-6)
.MODEL DESD1MOD D (BV = 8.2 Tbv1= -1.87e-3 N= 12 RS = 20)
.MODEL DESD2MOD D (BV = 11.5 Tbv1= -2.01e-3 N= 8 RS = 20)
.MODEL DPLCAPMOD D (CJO = 4.91e-10 IS = 1e-30 M = 0.59)
.MODEL MMEDMOD NMOS (VTO = 1.10 KP = 2.60 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 118)
.MODEL MSTROMOD NMOS (VTO = 1.29 KP = 58 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 0.86 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1180 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 7.58e-4 TC2 = -1.43e-6)
.MODEL RDRAINMOD RES (TC1 = 2.21e-2 TC2 = 2.72e-5)
.MODEL RSLCMOD RES (TC1 = 1.21e-3 TC2 = 1.00e-5)
.MODEL RSOURCEMOD RES (TC1 = 1.00e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.01e-3 TC2 = -1.01e-6)
.MODEL RVTEMPMOD RES (TC1 = -8.40e-4 TC2 = 0)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.5 VOFF= -3.0)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.0 VOFF= -3.5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.5 VOFF= 0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= -1.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8
ITF87012SVT
SABER Electrical Model
REV 25 Jan 2000
template itf87012svt n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (is = 3.48e-11,ikf = 0.15,xti = 0.18,rs = 1.47e-2,trs1 = 1.25e-3,trs2 = 0,cjo = 3.67e-10,tt = 2.20e-8,m = 0.52)
dp..model dbreakmod = (rs = 9.52e-2,trs1 = 1.05e-3,trs2 = 1.13e-6)
dp..model desd1mod = (bv = 8.2,tbv1 = -1.87e-3,n1 = 12,rs = 20)
dp..model desd2mod = (bv = 11.5,tbv1 = -2.01e-3,n1 = 8,rs = 20)
dp..model dplcapmod = (cjo = 4.91e-10,is = 1e-30,m = 0.59)
m..model mmedmod = (type=_n, vto = 1.01,kp = 2.60,is = 1e-30,tox = 1)
LDRAIN
m..model mstrongmod = (type=_n, vto = 1.29, kp = 58, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 0.86, kp = 0.10, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -3.5, voff = -3.0)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3.0, voff = -3.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.5, voff = 0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -1.5)
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
RSLC2
ISCL
c.ca n12 n8 = 11.00e-10
c.cb n15 n14 = 9.50e-10
c.cin n6 n8 = 5.25e-10
DBREAK
11
50
-
RDRAIN
6
8
ESG
dp.dbody n7 n71 = model=dbodymod
dp.dbreak n72 n11 = model=dbreakmod
dp.desd1 n91 n9 = model=desd1mod
dp.desd2 n91 n7 = model=desd2mod
DBODY
EVTHRES
+
16
21
+
-
19
8
MWEAK
LGATE
EVTEMP
+
RGATE
GATE
1
6
dp.dplcap n10 n5 = model=dplcapmod
-
18
22
EBREAK
+
MMED
9
20
MSTRO
8
i.it n8 n17 = 1
17
18
-
RLGATE
DESD1
91
DESD2
LSOURCE
CIN
l.ldrain n2 n5 = 1.00e-9
l.lgate n1 n9 = 1.04e-9
l.lsource n3 n7 = 1.29e-10
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
S2A
14
13
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RBREAK
12
15
13
17
18
8
RVTEMP
19
S1B
S2B
res.rbreak n17 n18 = 1, tc1 = 7.58e-4, tc2 = -1.43e-6
res.rdrain n50 n16 = 2.00e-3, tc1 = 2.21e-2, tc2 = 2.75e-5
res.rgate n9 n20 = 118
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 10.4
res.rlsource n3 n7 = 1.29
res.rslc1 n5 n51 = 1e-6, tc1 = 1.21e-3, tc2 = 1.00e-5
res.rslc2 n5 n50 = 1e3
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
res.rsource n8 n7 = 17.00e-3, tc1 = 1.00e-3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -8.40e-4, tc2 = 0
res.rvthres n22 n8 = 1, tc1 = -2.01e-3, tc2 = -1.01e-6
spe.ebreak n11 n7 n17 n18 = 27.41
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/175))** 2))
}
}
9
ITF87012SVT
SPICE Thermal Model
REV 24 Jan 2000
ITF87012SVT
2
JUNCTION
th
Copper Area = 0.02 in
CTHERM1 th 8 1.10e-3
CTHERM2 8 7 5.00e-3
CTHERM3 7 6 7.00e-3
CTHERM4 6 5 9.00e-3
CTHERM5 5 4 1.10e-2
CTHERM6 4 3 4.00e-2
CTHERM7 3 2 3.00e-1
CTHERM8 2 tl 1.50
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
CTHERM1
8
7
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM7
CTHERM8
RTHERM1 th 8 0.25
RTHERM2 8 7 0.60
RTHERM3 7 6 1.25
RTHERM4 6 5 8.00
RTHERM5 5 4 10.00
RTHERM6 4 3 43.00
RTHERM7 3 2 48.00
RTHERM8 2 tl 50.00
6
5
SABER Thermal Model
2
Copper Area = 0.02 in
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 1.10e-3
ctherm.ctherm2 8 7 = 5.00e-3
ctherm.ctherm3 7 6 = 7.00e-3
ctherm.ctherm4 6 5 = 9.00e-3
ctherm.ctherm5 5 4 = 1.10e-2
ctherm.ctherm6 4 3 = 4.00e-2
ctherm.ctherm7 3 2 = 3.00e-1
ctherm.ctherm8 2 tl = 1.50
4
3
2
rtherm.rtherm1 th 8 = 0.25
rtherm.rtherm2 8 7 = 0.60
rtherm.rtherm3 7 6 = 1.25
rtherm.rtherm4 6 5 = 8.00
rtherm.rtherm5 5 4 = 10.00
rtherm.rtherm6 4 3 = 43.00
rtherm.rtherm7 3 2 = 48.00
rtherm.rtherm8 2 tl = 50.00
}
tl
CASE
TABLE 1. THERMAL MODELS
2
2
2
2
2
COMPONENT
CTHERM6
0.02 in
0.05 in
4.00e-2
3.50e-1
1.50dd
35
0.10 in
0.25 in
0.40 in
4.00e-2
3.00e-1
1.50
43
4.20e-2
4.00e-2
3.00e-1
1.50
27
4.00e-2
2.80e-1
1.50
27
CTHERM7
3.30e-1
1.50
35
CTHERM8
RTHERM6
RTHERM7
48
40
37
30
29
RTHERM8
50
45
42
45
37
10
ITF87012SVT
MO-193AA (TSOP-6)
6 LEAD JEDEC MO-193AA TSOP PLASTIC PACKAGE
(SIMILAR TO SSOT™-6)
A
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
MAX
NOTES
E
A
1
1
A
0.035
0.043
0.90
1.10
A
0.004
0.10
1
e
b
c
0.012
0.003
0.107
0.103
0.056
0.020
0.008
0.122
0.118
0.070
0.30
0.08
2.70
2.60
1.40
0.50
0.20
3.10
3.00
1.80
D
b
D
E
2
3
4
E
C
o
1
e
L
0.037 BSC
0.014 0.021
0.95 BSC
0.35 0.55
0.004in
0.10mm
L
NOTES:
o
0 -8
1. All dimensions are within the allowable dimensions of Rev. B of
JEDEC MO-193AA outline dated 10-99.
0.037
0.95
0.039
1.00
2. Dimension "D" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.006 inches (0.15mm) per side.
0.075
1.90
3. Dimension "E " does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 0.006 inches
(0.15mm) per side.
0.024
0.60
0.095
2.40
4. "L" is the length of terminal for soldering.
5. Controlling dimension: Millimeter.
6. Revision 2 dated 5-00.
MO-193AA (TSOP-6)
8mm TAPE AND REEL
USER DIRECTION OF FEED
4.0mm
2.0mm
1.75mm
1.5mm DIAMETER HOLE
C
L
3.5mm
8.0mm
4.0mm
COVER TAPE
13.0mm
13.0mm
178mm
60mm
9.0mm
GENERAL INFORMATION
1. 3000 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.
SSOT™-6 is a trademark of Fairchild Semiconductor.
11
ITF87012SVT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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EUROPE
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12
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