IRFP140 [FAIRCHILD]
31A, 100V, 0.077 Ohm, N-Channel Power MOSFET; 31A ， 100V ， 0.077 Ohm的N通道功率MOSFET
| 型号： | IRFP140 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 31A, 100V, 0.077 Ohm, N-Channel Power MOSFET |
| 文件： | 总7页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRFP140
January 2002
31A, 100V, 0.077 Ohm, N-Channel Power
MOSFET
Features
• 31A, 100V
This N-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
• r = 0.077Ω
DS(ON)
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA17421.
Ordering Information
Symbol
PART NUMBER
PACKAGE
BRAND
IRFP140
D
IRFP140
TO-247
NOTE: When ordering, include the entire part number.
G
S
Packaging
JEDEC STYLE TO-247
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
©2002 Fairchild Semiconductor Corporation
IRFP140 Rev. B
IRFP140
o
Absolute Maximum Ratings
T = 25 C, Unless Otherwise Specified
C
IRFP140
100
100
31
22
120
20
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
V
V
A
A
A
V
W
DS
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
DGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
D
o
T
= 100 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
180
1.2
D
o
W/ C
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
100
-55 to 175
mJ
C
AS
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
o
300
260
C
C
L
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 150 C.
J
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 0V, I = 250µA (Figure 10)
MIN
TYP
MAX
-
UNITS
V
Drain to Source Breakdown Voltage
Gate to Threshold Voltage
V
V
V
V
V
V
V
V
100
-
-
-
-
-
-
DSS
GS
GS
DS
DS
DS
GS
GS
DS
D
V
= V , I = 250µA
DS
2.0
4.0
25
V
GS(TH)
D
Zero Gate Voltage Drain Current
I
= Rated BV
, V
= 0V
-
µA
µA
A
DSS
DSS GS
o
= 0.8 x Rated BV , V
= 0V, T = 125 C
-
250
-
DSS GS
J
On-State Drain Current (Note 2)
Gate to Source Leakage
I
> I
=
r
, V
= 10V
31
D(ON)
D(ON) x DS(ON)MAX GS
20V
I
-
100
nA
Ω
GSS
Drain to Source On Resistance (Note 2)
Forward Transconductance (Note 2)
Turn-On Delay Time
r
= 10V, I = 19A (Figures 8, 9)
-
0.055 0.077
DS(ON)
D
g
≥ 50V, I = 19A (Figure 12)
9.3
14
15
72
40
50
38
-
S
fs
d(ON)
D
t
V
V
= 50V, I ≈ 28A, R
= 9.1Ω, R = 1.7Ω,
-
-
-
-
-
23
110
60
75
59
ns
ns
ns
ns
nC
DD
GS
D
GS
L
= 10V
Rise Time
t
r
MOSFET Switching Times are Essentially
Independent of Operating Temperature
Turn-Off Delay Time
t
d(OFF)
Fall Time
t
f
Total Gate Charge
Q
V
= 10V, I ≈ 27A, V
= 0.8 x Rated BV
,
DSS
g(TOT)
GS
D
DS
(Gate to Source + Gate to Drain)
I
= 1.5mA (Figure 14)
G(REF)
Gate Charge is Essentially Independent of Operating
Temperature
Gate to Source Charge
Gate to Drain “Miller” Charge
Input Capacitance
Q
Q
-
-
-
-
-
-
10
21
-
-
-
-
-
-
nC
nC
pF
pF
pF
nH
gs
gd
C
V
= 0V, V
GS DS
≈ 25V, f = 1.0MHz (Figure 11)
1275
550
160
5.0
ISS
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
Internal Drain Inductance
C
L
Measured between the
Contact Screw on Header Symbol Showing the
that is Closer to Source Internal Devices
Modified MOSFET
D
and Gate Pins and Center Inductances
of Die
D
L
Internal Source Inductance
L
Measured from the
Source Lead, 6mm
-
12.5
-
nH
S
D
(0.25in) From Header to
Source Bonding Pad
G
L
S
S
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
R
-
-
-
-
0.83
30
C/W
θJC
o
Free Air Operation
C/W
θJA
©2002 Fairchild Semiconductor Corporation
IRFP140 Rev. B
IRFP140
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
Modified MOSFET
Symbol Showing the
Integral Reverse P-N
Junction Diode
MIN
TYP
MAX
31
UNITS
Continuous Source to Drain Current
Pulse Source to Drain Current (Note 3)
I
-
-
-
-
A
A
SD
D
S
I
120
SDM
G
o
Source to Drain Diode Voltage (Note 2)
Reverse Recovery Time
Reverse Recovered Charge
NOTES:
V
T = 25 C, I = 31A, V
= 0V (Figure 13)
-
-
2.5
300
1.9
V
SD
J
SD
SD
SD
GS
o
t
T = 25 C, I
J
= 28A, dI /dt = 100A/µs
70
150
0.91
ns
µC
rr
SD
= 28A, dI /dt = 100A/µs
o
Q
T = 25 C, I
0.44
RR
J
SD
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
o
4. V
DD
= 25V, starting T = 25 C, L = 160µH, R = 50Ω, peak I = 31A.
J G AS
Typical Performance Curves Unless Otherwise Specified
1.2
1.0
0.8
0.6
0.4
0.2
0
40
32
24
16
8
0
25
50
75
100
125
150
175
125
o
0
25
50
75
100
175
150
o
T
, CASE TEMPERATURE ( C)
T
, CASE TEMPERATURE ( C)
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
10
1
0.5
0.2
0.1
P
0.1
DM
0.05
0.02
0.01
t
1
-2
t
10
2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
J
x Z
θJC
+ T
DM
C
-3
10
-5
-4
10
-3
10
-2
10
10
0.1
1
10
t , RECTANGULAR PULSE DURATION (s)
1
FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2002 Fairchild Semiconductor Corporation
IRFP140 Rev. B
IRFP140
Typical Performance Curves Unless Otherwise Specified (Continued)
3
50
40
30
20
10
0
10
OPERATION IN THIS
REGION IS LIMITED
V
= 7V
GS
V
= 10V
= 8V
GS
BY r
DS(ON)
V
GS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
10µs
2
10
100µs
V
= 6V
GS
1ms
10
1
V
= 5V
= 4V
GS
10ms
DC
o
T
T
= 25 C
C
J
= MAX RATED
SINGLE PULSE
V
GS
2
3
10
, DRAIN TO SOURCE VOLTAGE (V)
10
1
10
0
2
10
V
20
30
40
50
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
DS
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. OUTPUT CHARACTERISTICS
50
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
V
= 7.0V
GS
DUTY CYCLE = 0.5% MAX
V
≥ 50V
DS
V
= 10V
40
30
20
10
0
GS
V
= 8V
GS
10
1
V
= 6V
GS
o
o
T
= 25 C
T
= 175 C
J
J
V
= 5V
= 4V
GS
V
GS
0.1
0
2
4
6
8
10
0
1
2
3
4
5
V
, DRAIN TO SOURCE VOLTAGE (V)
V
, GATE TO SOURCE VOLTAGE (V)
DS
GS
FIGURE 6. SATURATION CHARACTERISTICS
FIGURE 7. TRANSFER CHARACTERISTICS
1.0
0.8
0.6
0.4
0.2
0
3.0
2.4
1.8
1.2
0.6
0
PULSE DURATION = 80µs
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
I
= 19A, V
= 10V
D
GS
V
= 10V
GS
V
= 20V
GS
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
o
0
25
50
, DRAIN CURRENT (A)
100
125
75
I
T , JUNCTION TEMPERATURE ( C)
J
D
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 9. NORMALIZED DRAINTO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 8. DRAINTO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
©2002 Fairchild Semiconductor Corporation
IRFP140 Rev. B
IRFP140
Typical Performance Curves Unless Otherwise Specified (Continued)
1.25
1.15
1.05
0.95
0.85
0.75
3000
2400
1800
1200
600
I
= 250µA
D
V
= 0V, f = 1MHz
GS
ISS
C
= C
+ C
GS
GD
C
C
= C
GD
RSS
OSS
≈ C + C
DS
GD
C
ISS
C
OSS
C
RSS
0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
o
0
2
5
10
20
50
100
T , JUNCTION TEMPERATURE ( C)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
J
FIGURE 10. NORMALIZED DRAINTO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
3
20
10
PULSE DURATION = 80µs
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
V
≥ 50V
DS
16
12
8
o
T
J
= 25 C
J
2
10
o
T
= 175 C
o
T
= 175 C
J
10
1
4
o
T
= 25 C
J
0
0
10
20
30
40
50
0
0.6
1.2
1.8
2.4
3.0
I
, DRAIN CURRENT (A)
V
, SOURCE TO DRAIN VOLTAGE (V)
D
SD
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT
FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20
I
= 34A
D
16
V
= 20V
DS
12
8
V
= 50V
DS
V
= 80V
DS
4
0
0
12
24
36
48
60
Q , GATE CHARGE (nC)
g
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
©2002 Fairchild Semiconductor Corporation
IRFP140 Rev. B
IRFP140
Test Circuits and Waveforms
V
DS
BV
DSS
t
P
L
V
DS
I
AS
VARY t TO OBTAIN
P
V
DD
+
R
REQUIRED PEAK I
AS
G
V
DD
-
V
GS
DUT
t
P
0
I
AS
0V
0.01Ω
t
AV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
r
V
DS
90%
90%
R
L
+
10%
10%
0
0
V
DD
R
G
-
90%
50%
DUT
V
GS
50%
PULSE WIDTH
10%
V
GS
FIGURE 17. SWITCHING TIME TEST CIRCUIT
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
V
DS
(ISOLATED
SUPPLY)
CURRENT
REGULATOR
V
DD
Q
g(TOT)
V
SAME TYPE
AS DUT
GS
Q
gd
12V
BATTERY
0.2µF
50kΩ
Q
gs
0.3µF
D
S
V
DS
G
DUT
0
0
I
G(REF)
I
G(REF)
0
V
DS
I CURRENT
D
SAMPLING
RESISTOR
I
CURRENT
SAMPLING
RESISTOR
G
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
©2002 Fairchild Semiconductor Corporation
IRFP140 Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
â
SMART START™
STAR*POWER™
Stealth™
VCX™
FAST
ACEx™
Bottomless™
CoolFET™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
FASTr™
FRFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
CROSSVOLT™
DenseTrench™
DOME™
POP™
Power247™
PowerTrenchâ
QFET™
EcoSPARK™
E2CMOSTM
TinyLogic™
QS™
EnSignaTM
TruTranslation™
UHC™
QT Optoelectronics™
Quiet Series™
SILENTSWITCHERâ
FACT™
FACT Quiet Series™
UltraFETâ
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITYARISING OUT OF THE APPLICATION OR USE OFANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFFAIRCHILDSEMICONDUCTORCORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
相关型号：
IRFP140PBF
Preferred for commercail-industrial applications where higher power levels preclude the use of TO-220 devices.
INFINEON
©2020 ICPDF网 联系我们和版权申明