HUFA75429D3S [FAIRCHILD]
N-Channel UltraFET MOSFETs 60V, 20A, 25mз; N沟道MOSFET的UltraFET 60V ， 20A ， 25mз
| 型号： | HUFA75429D3S |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | N-Channel UltraFET MOSFETs 60V, 20A, 25mз |
| 文件： | 总11页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2002
HUFA75429D3S
®
N-Channel UltraFET MOSFETs
60V, 20A, 25mΩ
General Description
Applications
These N-Channel power MOSFETs are manufactured us-
ing the innovative UltraFET process. This advanced pro-
•
•
Motor & Load Control
Powertrain Management
®
cess technology achieves very low on-resistance per silicon
area, resulting in outstanding performance. This device is
capable of withstanding high energy in the avalanche mode
and the diode exhibits very low reverse recovery time and
stored charge. It was designed for use in applications where
power efficiency is important, such as switching regulators,
switching convertors, motor drivers, relay drivers, low-volt-
age bus switches.
Features
•
•
•
175°C Maximum Junction Temperature
UIS Capability (Single Pulse and Repetitive Pulse)
Ultra-Low On-Resistance r
= 0.025Ω, V = 10V
GS
DS(ON)
DRAIN (FLANGE)
D
S
GATE
G
SOURCE
TO-252
MOSFET Maximum Ratings T = 25°C unless otherwise noted
A
Symbol
Parameter
Ratings
60
Units
V
V
Drain to Source Voltage
Gate to Source Voltage
V
V
DSS
GS
±20
Drain Current
o
20
4
A
A
Continuous (T = 25 C, V = 10V)
C
GS
I
D
o
o
Continuous (T = 125 C, V = 10V, R = 52 C/W)
θJA
C
GS
Pulsed
Figure 4
312
A
E
P
Single Pulse Avalanche Energy (Note 1)
Power dissipation
mJ
AS
125
W
D
o
o
Derate above 25 C
0.83
W/ C
o
T , T
Operating and Storage Temperature
-55 to 175
C
J
STG
Thermal Characteristics
o
R
R
R
Thermal Resistance Junction to Case TO-252
Thermal Resistance Junction to Ambient TO-252
Thermal Resistance Junction to Ambient TO-252, 1in copper pad area
1.2
100
52
C/W
θJC
θJA
θJA
o
C/W
2
o
C/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2002 Fairchild Semiconductor Corporation
Rev. A
Package Marking and Ordering Information
Device Marking
75429D3
Device
Package
TO-252
TO-252
Reel Size
330mm
Tube
Tape Width
16mm
Quantity
2500 units
75 units
HUFA75429D3ST
HUFA75429D3S
75429D3
N/A
Electrical Characteristics T = 25°C unless otherwise noted
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
= 250µA, V = 0V
60
-
-
-
-
V
VDSS
D
GS
V
= 55V, V = 0V
1
DS
GS
I
µA
V
V
= 45V
= 0V
DSS
GSS
o
DS
GS
T =150 C
-
-
-
-
250
±100
C
I
V
= ±20V
nA
GS
On Characteristics
V
Gate to Source Threshold Voltage
V
= V , I = 250µA
2
-
-
4
V
GS(TH)
GS
DS
D
I
I
= 20A, V = 10V
0.021 0.025
D
GS
r
Drain to Source On Resistance
Ω
= 20A, V = 10V,
DS(ON)
D
GS
-
0.043 0.054
o
T = 175 C
J
Dynamic Characteristics
C
C
C
Input Capacitance
-
-
-
1090
376
102
65
-
-
pF
pF
pF
nC
nC
nC
nC
nC
ISS
V
= 25V, V = 0V,
GS
DS
Output Capacitance
OSS
RSS
f = 1MHz
Reverse Transfer Capacitance
Total Gate Charge at 20V
Total Gate Charge at 10V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
-
Q
Q
Q
Q
Q
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
85
47
2.6
-
g(TOT)
g(10)
g(TH)
gs
GS
V
V
-
-
-
-
36
GS
GS
V
= 30V
DD
= 20A
I
2
D
I = 1.0mA
g
4
14
-
gd
Switching Characteristics (V = 10V)
GS
t
t
t
t
t
t
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
74
ns
ns
ns
ns
ns
ns
ON
10
39
52
33
-
-
d(ON)
-
V
V
= 30V, I = 20A
r
DD
GS
D
= 10V, R = 11Ω
Turn-Off Delay Time
Fall Time
-
-
GS
d(OFF)
f
Turn-Off Time
128
OFF
Drain-Source Diode Characteristics
I
I
I
I
= 20A
= 10A
-
-
-
-
-
-
-
-
1.25
1.0
55
V
V
SD
SD
SD
SD
V
Source to Drain Diode Voltage
SD
t
Reverse Recovery Time
= 20A, dI /dt = 100A/µs
ns
nC
rr
SD
Q
Reverse Recovered Charge
= 20A, dI /dt = 100A/µs
83
RR
SD
Notes:
1: Starting T = 25°C, L = 1.56mH, I = 20A
J
AS
©2002 Fairchild Semiconductor Corporation
Rev. A
Typical Characteristics T = 25°C unless otherwise noted
A
1.2
25
1.0
20
0.8
15
0.6
10
0.4
5
0
0.2
0
0
25
50
75
100
150
175
125
o
25
50
75
100
125
o
150
175
T
, CASE TEMPERATURE ( C)
C
T
, CASE TEMPERATURE ( C)
C
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
0.01
PEAK T = P
x Z
x R
+ T
θJC C
J
DM
θJC
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
Figure 3. Normalized Maximum Transient Thermal Impedance
600
100
o
T
= 25 C
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
V
= 10V
CURRENT AS FOLLOWS:
GS
175 - T
150
C
I = I
25
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
Figure 4. Peak Current Capability
©2002 Fairchild Semiconductor Corporation
Rev. A
Typical Characteristics T = 25°C unless otherwise noted
A
500
500
If R = 0
= (L)(I )/(1.3*RATED BV
t
- V
DD
)
AV
AS
DSS
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV
t
- V ) +1]
DD
AV
AS
DSS
100µs
100
100
o
STARTING T = 25 C
J
1ms
OPERATION IN THIS
AREA MAY BE
10
10
LIMITED BY r
DS(ON)
10ms
o
SINGLE PULSE
STARTING T = 150 C
J
T
= MAX RATED
J
o
T
= 25 C
C
1
0.01
1
0.1
1
10
100
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
V
t , TIME IN AVALANCHE (ms)
DS
AV
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515.
Figure 6. Unclamped Inductive Switching
Capability
Figure 5. Forward Bias Safe Operating Area
50
50
PULSE DURATION = 80µs
V
= 10V
GS
DUTY CYCLE = 0.5% MAX
V
= 6V
= 5V
GS
V
= 15V
DD
40
30
20
10
0
40
30
20
10
0
V
= 7V
GS
V
GS
o
T
= 175 C
J
V
= 4.5V
o
GS
o
T
= 25 C
J
T
= 25 C
C
o
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
= -55 C
J
3
4
5
6
0
0.5
1.0
1.5
2.0
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
GS
DS
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
2.5
2.0
1.5
1.0
0.5
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= V , I = 250µA
DS D
GS
1.0
0.8
0.6
0.4
V
= 10V, I = 20A
D
GS
-80
-40
0
40
80
120
o
160
200
-80
-40
0
40
80
120
160
200
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 9. Normalized Drain to Source On
Resistance vs Junction Temperature
Figure 10. Normalized Gate Threshold Voltage vs
Junction Temperature
©2002 Fairchild Semiconductor Corporation
Rev. A
Typical Characteristics T = 25°C unless otherwise noted
A
1.2
1.1
1.0
0.9
3000
I
= 250µA
D
C
= C + C
GD
ISS
GS
1000
C
= C
GD
RSS
C
C
+ C
OSS
DS GD
100
50
V
= 0V, f = 1MHz
1
GS
-80
-40
0
40
80
120
o
160
200
0.1
10
60
T , JUNCTION TEMPERATURE ( C)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
J
Figure 11. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 12. Capacitance vs Drain to Source
Voltage
10
V
= 30V
DD
8
6
4
2
0
WAVEFORMS IN
DESCENDING ORDER:
I
I
= 20A
= 4A
D
D
0
10
20
Q , GATE CHARGE (nC)
30
40
g
Figure 13. Gate Charge Waveforms for Constant Gate Currents
Test Circuits and Waveforms
V
DS
BV
DSS
t
P
L
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
Figure 14. Unclamped Energy Test Circuit
Figure 15. Unclamped Energy Waveforms
©2002 Fairchild Semiconductor Corporation
Rev. A
Test Circuits and Waveforms (Continued)
V
DS
V
Q
g(TOT)
DD
R
L
V
DS
V
= 20V
GS
Q
V
g(10)
GS
+
-
V
DD
V
=10V
V
GS
GS
DUT
V
= 2V
GS
I
0
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
Figure 16. Gate Charge Test Circuit
Figure 17. Gate Charge Waveforms
V
DS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
R
L
t
t
f
r
V
DS
90%
90%
+
-
V
GS
V
DD
10%
10%
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
V
10%
GS
0
Figure 18. Switching Time Test Circuit
Figure 19. Switching Time Waveforms
©2002 Fairchild Semiconductor Corporation
Rev. A
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T , and the
thermal resistance of the heat dissipating path determines
125
100
75
JM
R
= 33.32 + 23.84/(0.268+Area)
θJA
the maximum allowable device power dissipation, P , in an
DM
application.
Therefore the application’s ambient
o
o
temperature, T ( C), and thermal resistance R
( C/W)
A
θJA
must be reviewed to ensure that T
is never exceeded.
JM
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(T
– T )
JM
A
(EQ. 1)
P
= -----------------------------
DM
50
RθJA
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
25
0.01
0.1
1
2
10
power dissipation ratings. Precise determination of P
complex and influenced by many factors:
is
AREA, TOP COPPER AREA (in )
DM
Figure 20. Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 20
defines the R
for the device as a function of the top
θJA
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 20 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
23.84
(0.268 + Area)
R
= 33.32 + ------------------------------------
(EQ. 2)
θJA
©2002 Fairchild Semiconductor Corporation
Rev. A
PSPICE Electrical Model
.SUBCKT HUFA75429D3S 2 1 3 rev February 2002
CA 12 8 1.9e-9
CB 15 14 1.9e-9
CIN 6 8 9.7e-10
LDRAIN
DPLCAP
5
DRAIN
2
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
5
51
ESLC
11
EBREAK 11 7 17 18 65
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
-
50
+
-
17
18
-
DBODY
RDRAIN
6
8
EBREAK
ESG
EVTHRES
+
16
21
EVTEMP 20 6 18 22 1
+
-
19
8
MWEAK
LGATE
EVTEMP
RGATE
GATE
1
+
6
-
IT 8 17 1
18
22
MMED
9
20
MSTRO
8
RLGATE
LGATE 1 9 3.54e-9
LDRAIN 2 5 1e-9
LSOURCE 3 7 2.21e-9
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLGATE 1 9 35.4
RLDRAIN 2 5 10
RLSOURCE 3 7 22.1
RLSOURCE
S1A
S2A
S2B
RBREAK
12
15
13
14
13
17
18
8
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RVTEMP
19
S1B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 6.5e-3
RGATE 9 20 2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
EGS
EDS
+
-
-
8
22
RVTHRES
RSOURCE 8 7 RSOURCEMOD 1.1e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*100),5))}
.MODEL DBODYMOD D (IS = 1.6e-12 N=1.02 RS = 8.1e-3 TRS1 = 3e-3 TRS2 = 2e-6 CJO = 1.43e-9 TT = 3e-8 M = 0.53 XTI=5.5)
.MODEL DBREAKMOD D (RS = 2e-1 TRS1 = 1e-3 TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 1.4e-9 IS = 1e-30 N = 10 M = 0.79)
.MODEL MmedMOD NMOS (VTO=3 KP=4.5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2)
.MODEL MstroMOD NMOS (VTO=3.6 KP=40 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=2.66 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2e1 RS=0.1)
.MODEL RBREAKMOD RES (TC1 =1.2e-3 TC2 = 1e-7)
.MODEL RDRAINMOD RES (TC1 = 1.2e-2 TC2 = 2.3e-5)
.MODEL RSLCMOD RES (TC1 = 8e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 8e-6)
.MODEL RVTEMPMOD RES (TC1 = -3e-3 TC2 = -2e-6)
.MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -1e-5)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8 VOFF= -3.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.5 VOFF= -8)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.1 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.1)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
Rev. A
SABER Electrical Model
REV February 2002
template HUFA75429D3S n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=1.6e-12,nl=1.02,rs=8.1e-3,trs1=3e-3,trs2=2e-6,cjo=1.43e-9,tt=3e-8,m=0.53,xti=5.5)
dp..model dbreakmod = (rs=2e-1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=1.4e-9,isl=10e-30,nl=10,m=0.79)
m..model mmedmod = (type=_n,vto=3,kp=4.5,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=3.6,kp=40,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.66,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-8,voff=-3.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-8)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.1,voff=0.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1.1)
c.ca n12 n8 = 1.9e-9
c.cb n15 n14 = 1.9e-9
c.cin n6 n8 = 9.7e-10
LDRAIN
DPLCAP
5
DRAIN
2
10
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RLDRAIN
RSLC1
51
RSLC2
ISCL
spe.ebreak n11 n7 n17 n18 = 65
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
DBREAK
11
50
-
RDRAIN
6
8
ESG
DBODY
EVTHRES
+
16
21
+
-
19
8
MWEAK
LGATE
EVTEMP
spe.evtemp n20 n6 n18 n22 = 1
RGATE
GATE
1
+
6
-
18
22
EBREAK
+
MMED
9
20
i.it n8 n17 = 1
MSTRO
17
18
-
RLGATE
LSOURCE
l.lgate n1 n9 = 3.54e-9
l.ldrain n2 n5 = 1e-9
l.lsource n3 n7 = 2.21e-9
CIN
SOURCE
3
8
7
RSOURCE
RLSOURCE
S1A
12
S2A
res.rlgate n1 n9 = 35.4
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 22.1
RBREAK
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
13
CB
CA
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
res.rbreak n17 n18 = 1, tc1=1.2e-3,tc2=1e-7
res.rdrain n50 n16 = 6.5e-3, tc1=1.2e-2,tc2=2.3e-5
res.rgate n9 n20 = 2
RVTHRES
res.rslc1 n5 n51 = 1e-6, tc1=8e-3,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.1e-2, tc1=1e-3,tc2=8e-6
res.rvthres n22 n8 = 1, tc1=-2e-3,tc2=-1e-5
res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=-2e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/100))** 5))}
}
©2002 Fairchild Semiconductor Corporation
Rev. A
SPICE Thermal Model
JUNCTION
th
REV 23 February 2002
HUFA75429D3S
CTHERM1 TH 6 2.49e-3
CTHERM2 6 5 7.6e-3
CTHERM3 5 4 7.8e-3
CTHERM4 4 3 8e-3
CTHERM5 3 2 1.3e-2
CTHERM6 2 TL 7.52e-2
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
6
RTHERM1 TH 6 6e-3
RTHERM2 6 5 1.4e-2
RTHERM3 5 4 9e-2
RTHERM4 4 3 1.8e-1
RTHERM5 3 2 3.1e-1
RTHERM6 2 TL 3.35e-1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
5
SABER Thermal Model
SABER thermal model HUFA75429D3S
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =2.49e-3
ctherm.ctherm2 6 5 =7.6e-3
ctherm.ctherm3 5 4 =7.8e-3
ctherm.ctherm4 4 3 =8e-3
ctherm.ctherm5 3 2 =1.3e-2
ctherm.ctherm6 2 tl =7.52e-2
4
3
2
rtherm.rtherm1 th 6 =6e-3
rtherm.rtherm2 6 5 =1.4e-2
rtherm.rtherm3 5 4 =9e-2
rtherm.rtherm4 4 3 =1.8e-1
rtherm.rtherm5 3 2 =3.1e-1
rtherm.rtherm6 2 tl =3.35e-1
}
tl
CASE
©2002 Fairchild Semiconductor Corporation
Rev. A
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