FST3345_08 [FAIRCHILD]

8-Bit Bus Switch; 8位总线开关
FST3345_08
型号: FST3345_08
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

8-Bit Bus Switch
8位总线开关

开关
文件: 总9页 (文件大小:434K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
March 2008  
FST3345 — 8-Bit Bus Switch  
Features  
Description  
The FST3345 switch provides eight-bits of high-speed  
CMOS TTL-compatible bus switching. The low on  
resistance of the switch allows inputs to be connected  
to outputs without adding propagation delay or  
generating additional ground bounce noise.  
ƒ
ƒ
ƒ
ƒ
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4Ω Switch Connection between Two Ports  
Minimal Propagation Delay through the Switch  
Low ICC  
Zero Bounce in Flow-through Mode  
Control Inputs Compatible with TTL Level  
The device is organized as an eight-bit switch with dual  
output enable inputs (OE and /OE). When /OE is LOW  
or OE is HIGH, the switch is ON and port A is  
connected to port B. When /OE is HIGH, and OE is  
LOW, the switch is OPEN and a high-impedance state  
exists between the two ports.  
Ordering Information  
Operating  
Part Number Temperature  
Range  
Packing  
Package  
Method  
20-Lead, Small Outline Integrated Circuit (SOIC), JEDEC  
MS-013, 0.300-inch Wide  
FST3345WMX -40 to +85°C  
Tape and Reel  
Tube  
20-Lead Quarter Size Outline Package (QSOP), JEDEC  
MO-137, 0.150-inch Wide  
FST3345QSC  
FST3345QSCX -40 to +85°C  
FST3345MTC -40 to +85°C  
FST3345MTCX -40 to +85°C  
-40 to +85°C  
20-Lead Quarter Size Outline Package (QSOP), JEDEC  
MO-137, 0.150-inch Wide  
Tape and Reel  
Tube  
20-Lead Thin Shrink Small Outline Package (TSSOP),  
JEDEC MO-153, 4.4mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC  
MO-153, 4.4mm Wide  
Tape and Reel  
All packages are lead free per JEDEC: J-STD-020B standard.  
The Fairchild switch family derives from and embodies Fairchild’s proven switch technology used for several years in its  
74LVX3L384 (FST3384) bus switch product.  
Logic Diagram  
2
9
18  
11  
B0  
A0  
A7  
B7  
1
19  
OE  
/OE  
Figure 1. Logic Diagram  
©1997 Fairchild Semiconductor Corporation  
FST3345 • Rev. 1.0.2  
www.fairchildsemi.com  
Pin Configuration  
VCC  
/OE  
OE  
A0  
1
2
3
4
20  
19  
18  
17  
B0  
B1  
B2  
B3  
A1  
A2  
A3  
5
6
16  
15  
A4  
A5  
A6  
B4  
B5  
B6  
7
8
14  
13  
12  
11  
9
A7  
10  
B7  
GND  
Figure 2. Pin Configuration  
Pin Descriptions  
Pin #  
Pin Names  
OE, /OE  
Description  
Bus Switch Enables  
Bus A  
1,19  
2,3,4,5,6,7,8,9  
A0,A1,A2,A3,A4,A5,A6,A7  
GND  
10  
Ground  
11,12,13,14,15,16,17,18  
20  
B7,B6,B5,B4,B3,B2,B1,B0  
VCC  
Bus B  
Supply Voltage  
Truth Table  
Input  
Function  
OE  
Don’t Care  
HIGH  
/OE  
LOW  
Connect  
Connect  
Don’t Care  
HIGH  
LOW  
Disconnect  
© 1997 Fairchild Semiconductor Corporation  
FST3345 • Rev. 1.0.2  
www.fairchildsemi.com  
2
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.  
In addition, extended exposure to stresses above the recommended operating conditions may affect device  
reliability. The absolute maximum ratings are stress ratings only.  
Symbol  
VCC  
Parameter  
Min.  
-0.5  
-0.5  
-0.5  
Max.  
7.0  
Unit  
V
Supply Voltage  
VS  
DC Switch Voltage  
DC Input Voltage(1)  
7.0  
V
VIN  
7.0  
V
IIK  
DC Input Diode Current, VIN < 0V  
DC Output Sink Current  
-50  
mA  
mA  
mA  
°C  
IOUT  
128  
±100  
+150  
ICC / IGND  
TSTG  
Note:  
DC VCC / GND Current  
Storage Temperature Range  
-65  
1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are  
observed.  
Recommended Operating Conditions  
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended  
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not  
recommend exceeding them or designing to Absolute Maximum Ratings.  
Symbol  
VCC  
Parameter  
Power Supply Operating  
Min.  
4.0  
0
Max.  
5.5  
5.5  
5.5  
5
Unit  
V
VIN  
Input Voltage  
V
VOUT  
Output Voltage  
0
V
Switch Control Input(2)  
Switch I/O  
0
tr, tf  
Input Rise and Fall Time  
ns/V  
°C  
0
DC  
+85  
TA  
Operating Temperature, Free Air  
-40  
Note:  
2. Unused control inputs must be held HIGH or LOW. They may not float.  
© 1997 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FST3345 • Rev. 1.0.2  
3
DC Electrical Characteristics  
Typical values are at VCC = 5.0V and TA = 25°C.  
TA=-40 to +85°C  
Symbol  
Parameter  
Conditions  
IIN = -18mA  
VCC (V)  
Units  
Min.  
Typ.  
Max.  
VIK  
VIH  
VIL  
IIN  
Clamp Diode Voltage  
High-Level Input Voltage  
Low-Level Input Voltage  
Input Leakage Current  
4.5  
-1.2  
V
V
4.0 to 5.5  
4.0 to 5.5  
5.5  
2.0  
0.8  
V
±1.0  
µA  
0 VIN 5.5V  
0 A, B VCC  
Off-state Leakage  
Current  
IOZ  
RON  
ICC  
5.5  
±1.0  
µA  
VIN = 0V, IIN = 64mA  
VIN = 0V, IIN = 30mA  
VIN = 2.4V, IIN = 15mA  
VIN = 2.4V, IIN = 15mA  
VIN = VCC or GND,  
4.5  
4.5  
4.5  
4.0  
4
4
7
7
Switch On Resistance(3)  
Ω
8
15  
20  
11  
Quiescent Supply Current  
Increase in ICC per Input  
5.5  
5.5  
3
µA  
I
OUT = 0  
One Input at 3.4V, Other  
Inputs at VCC or GND  
2.5  
mA  
ΔICC  
Note:  
3. Measured by the voltage drop between the A and B pins at the indicated current through the switch. On  
resistance is determined by the lower of the voltages on the A or B pins.  
AC Electrical Characteristics  
TA = -40 to +85°C, CL = 50pF, and RU = RD = 500Ω.  
VCC = 4.5 – 5.5V  
VCC = 4.0V  
Symbol  
Parameter  
Conditions  
Units  
Figure  
Min.  
Max.  
Min.  
Max.  
Propagation Delay  
Bus-to-Bus(4)  
Figure 3  
Figure 4  
tPHL, tPLH  
VIN = Open  
0.25  
0.25  
ns  
VIN = 7V for tPZL  
Figure 3  
Figure 4  
tPZH ,tPZL  
Output Enable Time  
Output Disable Time  
VIN = Open for  
1.5  
1.0  
6.5  
8.0  
7.0  
8.2  
ns  
ns  
tPZH  
VIN = 7V for tPLZ  
Figure 3  
Figure 4  
tPHZ, tPLZ  
VIN = Open for  
tPHZ  
Note:  
4. This parameter is guaranteed by design, but is not tested. The bus switch contributes no propagation delay  
other than the RC delay of the typical on resistance of the switch and the 50pF load capacitance when driven by  
an ideal voltage source (zero output impedance).  
Capacitance  
TA = +25°C, f = 1MHz. Capacitance is characterized, but not tested.  
Symbol  
CIN  
Parameter  
Conditions  
VCC = 5.0V  
Typ.  
Units  
pF  
Control Pin Input Capacitance  
Input/Output Capacitance  
4
5
CI/O  
VCC, /OE = 5.0V, OE = 0V  
pF  
© 1997 Fairchild Semiconductor Corporation  
FST3345 • Rev. 1.0.2  
www.fairchildsemi.com  
4
AC Loadings and Waveforms  
Notes: Input driven by 50Ω source terminated in 50Ω.  
CL includes load and stray capacitance.  
Input PRR = 1.0MHz, tw = 500ns.  
Figure 3. AC Test Circuit  
Figure 4. AC Waveforms  
© 1997 Fairchild Semiconductor Corporation  
FST3345 • Rev. 1.0.2  
www.fairchildsemi.com  
5
Physical Dimensions  
13.00  
12.60  
A
11.43  
20  
11  
B
9.50  
10.65 7.60  
10.00 7.40  
2.25  
1
PIN ONE  
INDICATOR  
10  
0.65  
0.51  
0.35  
1.27  
1.27  
M
0.25  
C B A  
LAND PATTERN RECOMMENDATION  
SEE DETAIL A  
2.65 MAX  
0.33  
0.20  
C
0.10  
C
0.30  
0.10  
SEATING PLANE  
0.75  
0.25  
X 45°  
NOTES: UNLESS OTHERWISE SPECIFIED  
(R0.10)  
(R0.10)  
A) THIS PACKAGE CONFORMS TO JEDEC  
MS-013, VARIATION AC, ISSUE E  
GAGE PLANE  
B) ALL DIMENSIONS ARE IN MILLIMETERS.  
C) DIMENSIONS DO NOT INCLUDE MOLD  
FLASH OR BURRS.  
0.25  
8°  
0°  
D) CONFORMS TO ASME Y14.5M-1994  
1.27  
0.40  
SEATING PLANE  
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L  
F) DRAWING FILENAME: MKT-M20BREV3  
(1.40)  
DETAIL A  
SCALE: 2:1  
Figure 5. 20-Lead, Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300-inch Wide  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify  
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically  
the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/  
© 1997 Fairchild Semiconductor Corporation  
FST3345 • Rev. 1.0.2  
www.fairchildsemi.com  
6
Physical Dimensions  
LAND PATTERN  
TOP VIEW  
RECOMMENDATION  
END VIEW  
SIDE VIEW  
DETAIL A  
Figure 6. 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150-inch Wide  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify  
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically  
the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/  
© 1997 Fairchild Semiconductor Corporation  
FST3345 • Rev. 1.0.2  
www.fairchildsemi.com  
7
Physical Dimensions  
Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify  
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically  
the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/  
© 1997 Fairchild Semiconductor Corporation  
FST3345 • Rev. 1.0.2  
www.fairchildsemi.com  
8
© 1997 Fairchild Semiconductor Corporation  
FST3345 • Rev. 1.0.2  
www.fairchildsemi.com  
9

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