FST3245MTCX_NL [FAIRCHILD]
8-Bit Bus Switch; 8位总线开关
| 型号： | FST3245MTCX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 8-Bit Bus Switch |
| 文件： | 总5页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1997
Revised March 2005
FST3245
8-Bit Bus Switch
General Description
Features
The Fairchild Switch FST3245 provides 8-bits of high-
speed CMOS TTL-compatible bus switching in a standard
’245 pin-out. The low on resistance of the switch allows
inputs to be connected to outputs without adding propaga-
tion delay or generating additional ground bounce noise.
■ 4 switch connection between two ports.
■ Minimal propagation delay through the switch.
■ Low lCC
.
■ Zero bounce in flow-through mode.
■ Control inputs compatible with TTL level.
The device is organized as an 8-bit switch. When OE is
LOW, the switch is ON and Port A is connected to Port B.
When OE is HIGH, the switch is OPEN and a high-imped-
ance state exists between the two ports.
Ordering Code:
Package
Order Number
Package Description
Number
FST3245WM
FST3245QSC
FST3245MTC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
MTC20
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
FST3245MTCX_NL
(Note 1)
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Diagram
Connection Diagram
Truth Table
Pin Descriptions
Pin Name
Description
Input OE
Function
Connect
OE
A
Bus Switch Enable
Bus A
L
H
Disconnect
B
Bus B
© 2005 Fairchild Semiconductor Corporation
DS500020
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Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 4)
Supply Voltage (VCC
)
0.5V to 7.0V
0.5V to 7.0V
0.5V to 7.0V
50mA
DC Switch Voltage (VS)
Power Supply Operating (VCC
Input Voltage (VIN
Output Voltage (VOUT
)
4.0V to 5.5V
0V to 5.5V
0V to 5.5V
DC Input Voltage (VIN) (Note 3)
DC Input Diode Current (lIK) VIN 0V
DC Output (IOUT) Sink Current
)
)
128mA
Input Rise and Fall Time (tr, tf)
Switch Control Input
DC VCC/GND Current (ICC/IGND
)
/
100mA
0nS/V to 5nS/V
0nS/V to DC
Storage Temperature Range (TSTG
)
65 C to 150
C
Switch I/O
Free Air Operating Temperature (TA)
40 C to 85 C
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 3: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 4: Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
T
40 C to 85
C
A
V
(V)
CC
Symbol
Parameter
Units
Conditions
Typ
(Note 5)
Min
Max
V
V
V
Clamp Diode Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
Input Leakage Current
OFF-STATE Leakage Current
Switch On Resistance
(Note 6)
4.5
4.0–5.5
4.0–5.5
5.5
1.2
V
V
V
A
A
I
18 mA
IK
IN
2.0
IH
IL
0.8
1.0
1.0
7
I
I
0
V
5.5V
I
IN
5.5
0
A, B
V
CC
OZ
R
4.5
4
4
V
V
V
V
V
0V, I
64 mA
30 mA
ON
IN
IN
IN
4.5
7
0V, I
IN
IN
IN
IN
4.5
8
15
20
3
2.4V, I
2.4V, I
15 mA
15 mA
IN
IN
4.0
11
I
Quiescent Supply Current
5.5
A
V
or GND, I
OUT
0
CC
CC
I
Increase in I per Input
5.5
2.5
mA
One Input at 3.4V
Other Inputs at V or GND
CC
CC
CC
Note 5: Typical values are at V
5.0V and T
25 C
CC
A
Note 6: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
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2
AC Electrical Characteristics
T
40 C to 85 C,
50pF, RU RD 500
A
C
L
Figure
Number
Symbol
Parameter
Units
Conditions
V
4.5 – 5.5V
V
4.0V
Max
CC
CC
Min
Max
Min
t
,t
Propagation Delay Bus to Bus
(Note 7)
0.25
0.25
ns
ns
V
OPEN
7V for t
Figures
1, 2
PHL PLH
I
t
, t
Output Enable Time
1.5
1.5
5.9
6.0
6.4
V
V
V
V
Figures
1, 2
PZH PZL
I
I
I
I
PZL
OPEN for t
PZH
t
, t
Output Disable Time
5.7
ns
7V for t
Figures
1, 2
PHZ PLZ
PLZ
OPEN for t
PHZ
Note 7: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage the source (zero output impedance).
Capacitance (Note 8)
Symbol
Parameter
Typ
Max
Units
Conditions
5.0V
C
C
Control Pin Input Capacitance
3
pF
V
V
IN
CC
Input/Output Capacitance
5
pF
, OE 5.0V
I/O
CC
Note 8: T
25 C, f 1 MHz, Capacitance is characterized but not tested.
A
AC Loading and Waveforms
Note: Input driven by 50 source terminated in 50
Note: C includes load and stray capacitance
L
Note: Input PRR 1.0 MHz t
500 ns
W
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
3
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Package Number MQA20
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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5
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