FSQ0465RU [FAIRCHILD]
Green-Mode Fairchild Power Switch (FPS) for Quasi-Resonant Operation - Low EMI and High Efficiency; 绿色模式飞兆功率开关( FPS )的准谐振操作 - 低EMI和高效率型号: | FSQ0465RU |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | Green-Mode Fairchild Power Switch (FPS) for Quasi-Resonant Operation - Low EMI and High Efficiency |
文件: | 总22页 (文件大小:3165K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
May 2009
FSQ0465RU
Green-Mode Fairchild Power Switch (FPS™) for
Quasi-Resonant Operation - Low EMI and High Efficiency
Features
Description
! Optimized for Quasi-Resonant Converters (QRC)
! Low EMI through Variable Frequency Control and AVS
A Quasi-Resonant Converter (QRC) generally shows
lower EMI and higher power conversion efficiency than a
(Alternating Valley Switching)
conventional hard-switched converter with a fixed
switching frequency. The FSQ-series is an integrated
Pulse-Width Modulation (PWM) controller and
SenseFET specifically designed for quasi-resonant
operation and Alternating Valley Switching (AVS). The
PWM controller includes an integrated fixed-frequency
oscillator, Under-Voltage Lockout (UVLO), Leading-
Edge Blanking (LEB), optimized gate driver, internal soft-
start, temperature-compensated precise current sources
for a loop compensation, and self-protection circuitry.
Compared with a discrete MOSFET and PWM controller
solution, the FSQ-series can reduce total cost,
component count, size, and weight; while simultaneously
increasing efficiency, productivity, and system reliability.
This device provides a basic platform for cost-effective
designs of quasi-resonant switching flyback converters.
! High-Efficiency through Minimum Voltage Switching
! Narrow Frequency Variation Range over Wide Load
and Input Voltage Variation
! Advanced Burst-Mode Operation for Low Standby
Power Consumption
! Simple Scheme for Sync-Voltage Detection
! Pulse-by-Pulse Current Limit
! Various Protection Functions: Overload Protection
(OLP), Over-Voltage Protection (OVP), Abnormal
Over-Current Protection (AOCP), Internal Thermal
Shutdown (TSD) with Hysteresis, Output Short
Protection (OSP)
! Under-Voltage Lockout (UVLO) with Hysteresis
! Internal Startup Circuit
! Internal High-Voltage Sense FET (650V)
! Built-in Soft-Start (17.5ms)
Applications
! Power Supply for LCD TV and Monitor, VCR, SVR,
STB, and DVD & DVD Recorder
! Adapter
Related Resources
Visit: http://www.fairchildsemi.com/apnotes/ for:
! AN-4134: Design Guidelines for Offline Forward
Converters Using Fairchild Power Switch (FPS™)
! AN-4137: Design Guidelines for Offline Flyback
Converters Using Fairchild Power Switch (FPS™)
! AN-4140: Transformer Design Consideration for
Offline Flyback Converters Using Fairchild Power
Switch (FPS™)
! AN-4141: Troubleshooting and Design Tips for
Fairchild Power Switch (FPS™) Flyback Applications
! AN-4145: Electromagnetic Compatibility for Power
Converters
! AN-4147: Design Guidelines for RCD Snubber of
Flyback Converters
! AN-4148: Audible Noise Reduction Techniques for
Fairchild Power Switch (FPS™) Applications
! AN-4150: Design Guidelines for Flyback Converters
Using FSQ-Series Fairchild Power Switch (FPS™)
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
Ordering Information
(1)
Maximum Output Power
(2)
Product
Number
Operating Current R
230V ±15%
85-265V
Replaces
Devices
(5)
DS(ON)
Max.
AC
(3)
AC
PKG.
Temp.
Limit
Open
Frame
Open
(3)
Adapter
Adapter
(4)
(4)
Frame
TO-
220F-6L
FSCM0465R
FSDM0465RE
FSQ0465RUWDTU
-25 to +85°C
1.8A
4.0Ω
50W
60W
28W
40W
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Notes:
1. The junction temperature can limit the maximum output power.
2. 230VAC or 100/115VAC with doubler.
3. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient temperature.
4. Maximum practical continuous power in an open-frame design at 50°C ambient.
5. Eco Status, RoHS.
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
2
Application Diagram
VO
AC
IN
VSTR
Drain
PWM
Sync
GND
VFB
VCC
FSQ0465 Rev. 00
Figure 1. Typical Flyback Application
Internal Block Diagram
VCC
Vstr
6
Sync
Drain
1
5
3
OSC
AVS
VCC
Vref
0.35/0.55
VBurst
V
CC good
VCC
Vref
8V/12V
Idelay
IFB
PWM
FB
4
3R
S
R
Q
Q
Gate
driver
Soft-
Start
LEB
250ns
R
t
< t
OSP
ON
after SS
LPF
V
OSP
AOCP
2
S
R
Q
V
SD
VOCP
(1.1V)
TSD
GND
Q
LPF
VCC
V
OVP
VCC good
FSQ0465 Rev.00
Figure 2. Internal Block Diagram
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
3
Pin Configuration
6. VSTR
5. Sync
4. FB
3. VCC
2. GND
1. Drain
FSQ0465 Rev.00
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Drain
GND
Description
1
2
SenseFET Drain. High-voltage power SenseFET drain connection.
Ground. This pin is the control ground and the SenseFET source.
Power Supply. This pin is the positive supply input, providing internal operating current for
both start-up and steady-state operation.
3
4
5
6
VCC
Feedback. This pin is internally connected to the inverting input of the PWM comparator. The
collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should
be placed between this pin and GND. If the voltage of this pin reaches 6V, the overload pro-
tection triggers, which shuts down the FPS.
FB
Sync. This pin is internally connected to the sync-detect comparator for quasi-resonant switch-
ing. In normal quasi-resonant operation, the threshold of the sync comparator is 1.2V/1.0V.
Sync
Vstr
Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link. At
startup, the internal high-voltage current source supplies internal bias and charges the exter-
nal capacitor connected to the VCC pin. Once VCC reaches 12V, the internal current source is
disabled. It is not recommended to connect Vstr and Drain together.
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA = 25°C, unless otherwise specified.
Symbol
Vstr
Parameter
Min.
500
Max.
Unit
V
Vstr Pin Voltage
Drain Pin Voltage
Supply Voltage
VDS
650
V
VCC
21
V
VFB
Feedback Voltage Range
Sync Pin Voltage
-0.3
-0.3
13.0
13.0
8.4
V
VSync
IDM
V
Drain Current Pulsed
A
Continuous Drain Switching
Current(6)
IDSW
TC = 25°C
3.8
A
EAS
PD
Single Pulsed Avalanche Energy(7)
Total Power Dissipation (TC=25°C)
Operating Junction Temperature
Operating Ambient Temperature
Storage Temperature
100
45
mJ
W
TJ
Internally limited
°C
°C
°C
TA
-25
-55
+85
TSTG
+150
Human Body Model,
JESD22-A114
2.0
2.0
kV
kV
ESD
Electrostatic Discharge
Charged Device Model,
JESD22-C101
Notes:
6. Repetitive peak switching current when inductor load is assumed : limited by maximum duty and maximum junction
temperature.
IDS
DMAX
fSW
7. L=45mH, IAS=2.1A, starting TJ=25°C.
Thermal Impedance
TA = 25°C unless otherwise specified.
Symbol
θJA
Parameter
Junction-to-Ambient Thermal Resistance(8)
Junction-to-Case Thermal Resistance(9)
Package
Value
50
Unit
°C/W
°C/W
TO-220F-6L
θJC
2.8
Notes:
8. Free standing with no heat-sink under natural convection.
9. Infinite cooling condition - refer to the SEMI G30-88.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSQ0465RU Rev. 1.0.0
5
Electrical Characteristics
TA = 25°C unless otherwise specified.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
SenseFET Section
BVDSS
IDSS1
IDSS2
RDS(ON)
COSS
td(on)
tr
Drain Source Breakdown Voltage
Zero-Gate-Voltage Drain Current 1
Zero-Gate-Voltage Drain Current 2
Drain-Source On-State Resistance
Output Capacitance
VCC=0V, ID=250µA
650
V
VDS=650V, VGS=0V, TC=25oC
VDS=520V, VGS=0V, TC=125oC
TJ=25°C, ID=0.5A
250
250
4.0
µA
µA
Ω
3.5
45
12
22
20
19
VGS=0V, VDS=25V, f=1MHz
VDD=325V, ID=3.5A
pF
ns
ns
ns
ns
Turn-On Delay Time
Rise Time
VDD=325V, ID=3.5A
td(off)
tf
Turn-Off Delay Time
VDD=325V, ID=3.5A
Fall Time
VDD=325V, ID=3.5A
Control Section
tON.MAX Maximum On Time
tB
TJ=25°C
8.8 10.0 11.2
13.5 15.0 16.5
6.0
µs
µs
µs
Blanking Time
TJ=25°C, Vsync=5V
TJ=25°C, Vsync=0V
tW
Detection Time Window
Initial Switching Frequency
Switching Frequency Variation(11)
fS
59.6 66.7 75.8 kHz
ΔfS
tAVS
-25°C < TJ < 85°C
±5
±10
%
On Time
4.0
µs
at VIN=240VDC, Lm=360μH
(AVS Triggered when VAVS
Spec. and tAVS < Spec.)
AVS Triggering
>
Threshold(11)
Feedback
VAVS
tSW
1.2
V
Voltage
Sync=500kHz Sine Input
VFB=1.2V, tON=4.0µs
Switching Time Variance by AVS(11)
13.5
20.5
µs
IFB
DMIN
Feedback Source Current
Minimum Duty Cycle
VFB=0V
VFB=0V
700 900 1100 µA
0
%
V
VSTART
VSTOP
tS/S
11
12
8.0
17.5
19
13
8.5
UVLO Threshold Voltage
After Turn-On
7.5
V
Internal Soft-Start Time
Over-Voltage Protection
With Free-Running Frequency
ms
V
VOVP
18
20
Burst-ModeSection
VBURH
0.45 0.55 0.65
0.25 0.35 0.45
200
V
V
VBURL
Burst-Mode Voltages
TJ=25°C, tPD=200ns(10)
Hysteresis
mV
Continued on the following page...
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
6
Electrical Characteristics (Continued)
TA = 25°C unless otherwise specified.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Protection Section
ILIMIT
VSD
IDELAY
tLEB
Peak Current Limit
TJ=25°C, di/dt=480mA/µs
VCC=15V
1.6
5.5
4
1.8
6.0
5
2.0
6.5
6
A
V
Shutdown Feedback Voltage
Shutdown Delay Current
Leading-Edge Blanking Time(11)
Threshold Time
VFB=5V
µA
ns
µs
250
1.2
tOSP
1.4
TJ= 25°C
Output Short Threshold Feedback
Protection(11) Voltage
OSP Triggered When tON < tOSP
VFB > VOSP and Lasts Longer
than tOSP_FB
,
VOSP
1.8
2.0
2.0
V
tOSP_FB
TSD
Feedback Blanking Time
2.5
3.0
µs
Shutdown Temperature
Hysteresis
+125 +140 +155
+60
Thermal
°C
Shutdown(11)
Hys
Sync Section
VSH1
1.0
0.8
1.2
1.0
230
4.7
4.4
1.4
1.2
Sync Threshold Voltage 1
Sync Delay Time(11)(12)
VCC = 15V, VFB=2V
VCC = 15V, VFB=2V
V
ns
V
VSL1
tsync
VSH2
VSL2
4.3
4.0
5.1
4.8
Sync Threshold Voltage 2
Low Clamp Voltage
ISYNC_MAX=800µA,
ISYNC_MIN=50µA
VCLAMP
0.0
0.4
0.8
V
Total Device Section
IOP
Operating Supply Current
VCC=13V
VCC=10V
(Before VCC Reaches VSTART
1
3
5
mA
µA
ISTART
Start Current
350 450 550
)
ICH
Startup Charging Current
VCC=0V, VSTR=Minimum 50V
0.65 0.85 1.00 mA
VSTR
Minimum VSTR Supply Voltage
26
V
Notes:
10. Propagation delay in the control IC.
11. Guaranteed by design; not tested in production.
12. Includes gate turn-on time.
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
7
Comparison Between FSDM0x65RNB and FSQ-Series
Function
FSDM0x65RE
FSQ-Series
FSQ-Series Advantages
! Improved efficiency by valley switching
! Reduced EMI noise
! Reduced components to detect valley point
Constant
Frequency PWM
Quasi-Resonant
Operation
Operation Method
! Valley switching
! Inherent frequency modulation
! Alternate valley switching
Frequency
Modulation
Reduced
EMI Noise
EMI Reduction
Hybrid Control
CCM or AVS
Based on Load ! Improves efficiency by introducing hybrid control
and Input Condition
Advanced
Burst-Mode
Operation
Burst-Mode
Operation
Burst-Mode
Operation
! Improved standby power by advanced burst-mode
! Improved reliability through precise AOCP
! Improved reliability through precise OSP
OLP, OVP,
AOCP, OSP
Strong Protections
TSD
OLP, OVP
145°C without
Hysteresis
140°C with 60°C
Hysteresis
! Stable and reliable TSD operation
! Converter temperature range
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
8
Typical Performance Characteristics
These characteristic graphs are normalized at TA= 25°C.
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 4. Operating Supply Current (IOP) vs. TA
Figure 5. UVLO Start Threshold Voltage
(VSTART) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 6. UVLO Stop Threshold Voltage
(VSTOP) vs. TA
Figure 7. Startup Charging Current (ICH) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 8. Initial Switching Frequency (fS) vs. TA
Figure 9. Maximum On Time (tON.MAX) vs. TA
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
9
Typical Performance Characteristics (Continued)
These characteristic graphs are normalized at TA= 25°C.
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 10. Blanking Time (tB) vs. TA
Figure 11. Feedback Source Current (IFB) vs. TA
1.2
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 12. Shutdown Delay Current (IDELAY) vs. TA
Figure 13. Burst-Mode High Threshold Voltage
(Vburh) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 14. Burst-Mode Low Threshold Voltage
(Vburl) vs. TA
Figure 15. Peak Current Limit (ILIM) vs. TA
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
10
Typical Performance Characteristics (Continued)
These characteristic graphs are normalized at TA= 25°C.
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 16. Sync High Threshold Voltage 1
(VSH1) vs. TA
Figure 17. Sync Low Threshold Voltage 1
(VSL1) vs. TA
1.2
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 18. Shutdown Feedback Voltage (VSD) vs. TA
Figure 19. Over-Voltage Protection (VOV) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 20. Sync High Threshold Voltage 2
(VSH2) vs. TA
Figure 21. Sync Low Threshold Voltage 2
(VSL2) vs. TA
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
11
2.1 Pulse-by-Pulse Current Limit: Because current-
mode control is employed, the peak current through the
SenseFET is limited by the inverting input of PWM
comparator (VFB*), as shown in Figure 23. Assuming
Functional Description
1. Startup: At startup, an internal high-voltage current
source supplies the internal bias and charges the
external capacitor (Ca) connected to the VCC pin, as
that the 0.9mA current source flows only through the
internal resistor (3R + R = 2.8k), the cathode voltage of
diode D2 is about 2.5V. Since D1 is blocked when the
feedback voltage (VFB) exceeds 2.5V, the maximum
illustrated in Figure 22. When VCC reaches 12V, the
FPS™ begins switching and the internal high-voltage
current source is disabled. The FPS continues its normal
switching operation and the power is supplied from the
auxiliary transformer winding unless VCC goes below the
voltage of the cathode of D2 is clamped at this voltage,
clamping VFB*. Therefore, the peak value of the current
stop voltage of 8V.
through the SenseFET is limited.
VDC
2.2 Leading-Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, a high-current spike
usually occurs through the SenseFET, caused by
primary-side capacitance and secondary-side rectifier
reverse recovery. Excessive voltage across the Rsense
CVCC
VCC
VSTR
resistor would lead to incorrect feedback operation in the
current-mode PWM control. To counter this effect, the
FPS employs a leading-edge blanking (LEB) circuit. This
circuit inhibits the PWM comparator for a short time
(tLEB) after the SenseFET is turned on Pulse-Width-
3
6
Istart
VREF
8V/12V
Vcc good
Modulation (PWM) Circuit
Internal
Bias
3. Synchronization: The FSQ-series employs a quasi-
resonant switching technique to minimize the switching
noise and loss. The basic waveforms of the quasi-
resonant converter are shown in Figure 25. To minimize
the MOSFET's switching loss, the MOSFET should be
turned on when the drain voltage reaches its minimum
value, which is indirectly detected by monitoring the VCC
FSQ0465 Rev.00
Figure 22. Startup Circuit
2. Feedback Control: FPS employs current-mode
control, as shown in Figure 23. An opto-coupler (such as
the FOD817A) and shunt regulator (such as the KA431)
are typically used to implement the feedback network.
Comparing the feedback voltage with the voltage across
the Rsense resistor makes it possible to control the
winding voltage, as shown in Figure 24.
Vds
switching duty cycle. When the reference pin voltage of
the shunt regulator exceeds the internal reference
voltage of 2.5V, the opto-coupler LED current increases,
pulling down the feedback voltage and reducing the duty
cycle. This typically happens when the input voltage is
increased or the output load is decreased.
VRO
VRO
VDC
TF
Vsync
Vovp (8V)
VCC
Idelay
VREF
IFB
VFB
VO
1.2V
SenseFET
OSC
4
1.0V
H11A817A
D1
D2
CB
3R
R
230ns Delay
+
VFB*
Gate
driver
MOSFET Gate
KA431
-
ON
ON
OLP
Rsense
VSD
FSQ0465 Rev.00
FSQ0465 Rev.00
Figure 24. Quasi-Resonant Switching Waveforms
Figure 23. Pulse-Width-Modulation (PWM) Circuit
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
12
The switching frequency is the combination of blank time
(t ) and detection time window (t ). In case of a heavy
tX
tB=15µs
B
W
load, the sync voltage remains flat after t and waits for
B
valley detection during t . This leads to a low switching
W
frequency not suitable for heavy loads. To correct this
drawback, additional timing is used. The timing
conditions are described in Figures 25, 26, and 27. When
IDS
IDS
the V
remains flat higher than 4.4V at the end of t
sync
B
VDS
which is instant t , the next switching cycle starts after
X
internal delay time from t . In the second case, the next
X
ingnore
switching occurs on the valley when the V
goes below
sync
4.4V
4.4V within t . Once V
detects the first valley in t , the
B
B
sync
Vsync
1.2V
1.0V
other switching cycle follows classical QRC operation.
FSQ0465 Rev.00
tX
tB=15µs
internal delay
Figure 27. After Vsync Finds First Valley
IDS
IDS
4. Protection Circuits: The FSQ-series has several self-
protective functions, such as Overload Protection (OLP),
Abnormal Over-Current Protection (AOCP), Over-
Voltage Protection (OVP), and Thermal Shutdown
(TSD). All the protections are implemented as auto-
restart mode. Once the fault condition is detected,
switching is terminated and the SenseFET remains off.
This causes VCC to fall. When VCC falls down to the
VDS
4.4V
Vsync
1.2V
1.0V
Under-Voltage Lockout (UVLO) stop voltage of 8V, the
protection is reset and the startup circuit charges the
VCC capacitor. When the VCC reaches the start voltage
FSQ0465 Rev.00
internal delay
of 12V, normal operation resumes. If the fault condition is
not removed, the SenseFET remains off and VCC drops
Figure 25. Vsync > 4.4V at tX
to stop voltage again. In this manner, the auto-restart can
alternately enable and disable the switching of the power
SenseFET until the fault condition is eliminated.
Because these protection circuits are fully integrated into
the IC without external components, reliability is
improved without increasing cost.
tX
tB=15µs
IDS
IDS
Fault
occurs
Fault
removed
Power
on
VDS
VDS
VCC
4.4V
Vsync
1.2V
1.0V
12V
8V
FSQ0465 Rev.00
internal delay
Figure 26. Vsync < 4.4V at tX
t
FSQ0465 Rev.00
Normal
operation
Fault
situation
Normal
operation
Figure 28. Auto Restart Protection Waveforms
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
13
4.1 Overload Protection (OLP): Overload is defined as
the load current exceeding its normal level due to an
unexpected abnormal event. In this situation, the
protection circuit should trigger to protect the SMPS.
However, even when the SMPS is in the normal
operation, the overload protection circuit can be
triggered during the load transition. To avoid this
undesired operation, the overload protection circuit is
designed to trigger only after a specified time to
determine whether it is a transient situation or a true
overload situation. Because of the pulse-by-pulse
current limit capability, the maximum peak current
through the SenseFET is limited, and therefore the
maximum input power is restricted with a given input
voltage. If the output consumes more than this maximum
power, the output voltage (VO) decreases below the set
3R
R
OSC
PWM
S
R
Q
Q
Gate
driver
LEB
200ns
Rsense
+
-
2
AOCP
FSQ0465 Rev.00
GND
VOCP
Figure 30. Abnormal Over-Current Protection
4.3 Output-Short Protection (OSP): If the output is
shorted, steep current with extremely high di/dt can flow
through the SenseFET during the LEB time. Such a
steep current brings high voltage stress on the drain of
SenseFET when turned off. To protect the device from
such an abnormal condition, OSP is included in the FSQ-
voltage. This reduces the current through the opto-
coupler LED, which also reduces the opto-coupler
transistor current, thus increasing the feedback voltage
(VFB). If VFB exceeds 2.5V, D1 is blocked and the 5µA
series. It is comprised of detecting V and SenseFET
FB
current source starts to charge CB slowly up to VCC. In
this condition, VFB continues increasing until it reaches
turn-on time. When the V is higher than 2V and the
FB
SenseFET turn-on time is lower than 1.2µs, the FPS
recognizes this condition as an abnormal error and shuts
down PWM switching until V
6V, when the switching operation is terminated, as
shown in Figure 29. The delay time for shutdown is the
time required to charge CFB from 2.5V to 6V with 5µA. A
reaches V
again. An
CC
start
abnormal condition output short is shown in Figure 31.
20 ~ 50ms delay time is typical for most applications.
Turn-off delay
Rectifier
Diode
Current
MOSFET
Drain
Current
FSQ 0465 Rev.00
VFB
ILIM
Overload protection
VFB
6.0V
0
Minimum turn-on time
D
Vo
2.5V
1.2µs
output short occurs
t12= Cfb*(6.0-2.5)/Idelay
0
Io
T1
T2
t
FSQ0465 Rev. 00
Figure 29. Overload Protection
0
Figure 31. Output Short Waveforms
4.2 Abnormal Over-Current Protection (AOCP): When
the secondary rectifier diodes or the transformer pins are
shorted, a steep current with extremely high di/dt can
flow through the SenseFET during the LEB time. Even
though the FSQ-series has overload protection, it is not
enough to protect the FSQ-series in that abnormal case,
since severe current stress is imposed on the SenseFET
until OLP triggers. The FSQ-series has an internal
AOCP circuit shown in Figure 30. When the gate turn-on
signal is applied to the power SenseFET, the AOCP
block is enabled and monitors the current through the
sensing resistor. The voltage across the resistor is
compared with a preset AOCP level. If the sensing
resistor voltage is greater than the AOCP level, the set
signal is applied to the latch, resulting in the shutdown of
the SMPS.
4.4 Over-Voltage Protection (OVP): If the secondary
side feedback circuit malfunctions or a solder defect
causes an opening in the feedback path, the current
through the opto-coupler transistor becomes almost
zero. Then, Vfb climbs up in a similar manner to the
overload situation, forcing the preset maximum current
to be supplied to the SMPS until overload protection is
activated. Because more energy than required is
provided to the output, the output voltage may exceed
the rated voltage before overload protection is activated,
resulting in the breakdown of the devices in the
secondary side. To prevent this situation, an over-voltage
protection (OVP) circuit is employed. In general, VCC is
proportional to the output voltage and the FSQ-series
uses VCC instead of directly monitoring the output
voltage. If VCC exceeds 19V, an OVP circuit is activated,
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
14
resulting in the termination of the switching operation. To
avoid undesired activation of OVP during normal
operation, VCC should be designed below 19V.
VO
Voset
VFB
4.5 Thermal Shutdown with Hysteresis (TSD): The
SenseFET and the control IC are built in one package.
This enables the control IC to detect the abnormally high
temperature of the SenseFET. If the temperature
exceeds approximately 140°C, the thermal shutdown
triggers IC shutdown. The IC recovers its operation when
the junction temperature decreases 60°C from TSD
temperature and VCC reaches startup voltage (Vstart).
0.55V
0.35V
IDS
5. Soft-Start: The FPS has an internal soft-start circuit
that increases PWM comparator inverting input voltage
with the SenseFET current slowly after it starts up. The
typical soft-start time is 17.5ms. The pulse width to the
power switching device is progressively increased to
establish the correct working conditions for transformers,
inductors, and capacitors. The voltage on the output
capacitors is progressively increased with the intention of
smoothly establishing the required output voltage. This
mode helps prevent transformer saturation and reduces
stress on the secondary diode during startup.
VDS
FSQ0465 Rev. 00
time
Switching
disabled
Switching
disabled
t1
t2 t3
t4
Figure 32. Waveforms of Burst Operation
7. Switching Frequency Limit: To minimize switching
loss and Electromagnetic Interference (EMI), the
MOSFET turns on when the drain voltage reaches its
minimum value in quasi-resonant operation. However,
this causes switching frequency to increases at light-load
conditions. As the load decreases or input voltage
increases, the peak drain current diminishes and the
switching frequency increases. This results in severe
switching losses at light-load condition, as well as
intermittent switching and audible noise. These problems
create limitations for the quasi-resonant converter
topology in a wide range of applications.
6. Burst Operation: To minimize power dissipation in
standby mode, the FPS enters burst-mode operation. As
the load decreases, the feedback voltage decreases. As
shown in Figure 32, the device automatically enters
burst-mode when the feedback voltage drops below
VBURL (350mV). At this point, switching stops and the
output voltages start to drop at a rate dependent on
standby current load. This causes the feedback voltage
to rise. Once it passes VBURH (550mV), switching
resumes. The feedback voltage then falls and the
process repeats. Burst-mode operation alternately
enables and disables switching of the power SenseFET,
thereby reducing switching loss in standby mode.
To overcome these problems, FSQ-series employs a
frequency-limit function, as shown in Figures 33 and
Figure 34. Once the SenseFET is turned on, the next
turn-on is prohibited during the blanking time (tB). After
the blanking time, the controller finds the valley within
the detection time window (tW) and turns on the
MOSFET, as shown in Figures 33 and Figure 34 (Cases
A, B, and C). If no valley is found during tW, the internal
SenseFET is forced to turn on at the end of tW (Case D).
Therefore, the devices have a minimum switching
frequency of 48kHz and a maximum switching frequency
of 67kHz.
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
15
8. AVS (Alternating Valley Switching): Due to the
quasi-resonant operation with limited frequency, the
switching frequency varies depending on input voltage,
load transition, and so on. At high input voltage, the
switching on time is relatively small compared to low
input voltage. The input voltage variance is small and the
switching frequency modulation width becomes small. To
improve the EMI performance, AVS is enabled when
input voltage is high and the switching on time is small.
tsmax=21μs
IDS
IDS
A
B
VDS
tB=15μs
ts
Internally, quasi-resonant operation is divided into two
categories; one is first-valley switching and the other is
second-valley switching after blanking time. In AVS, two
successive occurrences of first-valley switching and the
other two successive occurrences of second-valley
switching is alternatively selected to maximize frequency
modulation. As depicted in Figure 34, the switching
frequency hops when the input voltage is high. The
internal timing diagram of AVS is described in Figure 35.
IDS
IDS
VDS
tB=15μs
ts
IDS
IDS
fs
1
Assume the resonant period is 2μ s
15μs
1
C
VDS
67kHz
59kHz
17μs
tB=15μs
53kHz
1
48kHz
19μs
ts
AVS trigger point
Constant
frequency
1
Variable frequency within limited range
DCM
21μs
CCM
IDS
IDS
AVS region
VDS
D
D
C
B
A
tB=15μs
tW=6μs
VIN
FSQ0465 Rev.00
tsmax=21μs
FSQ0465 Rev. 00
Figure 34. Switching Frequency Range
Figure 33. QRC Operation with Limited Frequency
Vgate
Vgate continued 2 pulses
Vgate continued 2 pulses
Vgate continued another 2 pulses
1st valley switching
2nd valley switching
1st valley switching
GateX2
fixed
fixed
fixed
fixed
fixed fixed
One-shot
AVS
triggering
de-triggering
1st or 2nd is depend on GateX2
triggering
1st or 2nd is dependent on GateX2
VDS
tB
tB
tB
tB
tB
tB
GateX2: Counting Vgate every 2 pulses independent on other signals.
FSQ0465 Rev. 00
1st valley- 2nd valley frequency modulation.
Modulation frequency is approximately 17kHz.
Figure 35. Alternating Valley Switching (AVS)
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
16
PCB Layout Guide
Due to the combined scheme, FPS shows better noise
immunity than conventional PWM controller and
MOSFET discrete solutions. Furthermore, internal drain
current sense eliminates noise generation caused by a
sensing resistor. There are some recommendations for
PCB layout to enhance noise immunity and suppress the
noise inevitable in power-handling components.
There are typically two grounds in the conventional
SMPS: power ground and signal ground. The power
ground is the ground for primary input voltage and
power, while the signal ground is ground for PWM
controller. In FPS, those two grounds share the same
pin, GND. Normally the separate grounds do not share
the same trace and meet only at one point, the GND pin.
More, wider patterns for both grounds are good for large
currents by decreasing resistance.
Capacitors at the VCC and FB pins should be as close as
possible to the corresponding pins to avoid noise from
the switching device. Sometimes Mylar® or ceramic
capacitors with electrolytic for VCC is better for smooth
operation. The ground of these capacitors needs to
connect to the signal ground (not power ground).
Figure 36. Recommended PCB Layout
The cathode of the snubber diode should be close to the
Drain pin to minimize stray inductance. The Y-capacitor
between primary and secondary should be directly
connected to the power ground of DC link to maximize
surge immunity.
Because the voltage range of feedback and sync line is
small, it is affected by the noise of the drain pin. Those
traces should not draw across or close to the drain line.
When the heat sink is connected to the ground, it should
be connected to the power ground. If possible, avoid
using jumper wires for power ground and drain.
Mylar® is a registered trademark of DuPont Teijin Films.
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
17
Typical Application Circuit
Input Voltage
Range
Output Voltage
(Maximum Current)
Application
FPS™ Device
Rated Output Power
LCD Monitor
Power Supply
5.0V (2.0A)
14V (1.8A)
FSQ0465RU
85-265VAC
36W
Features
! Average efficiency of 25%, 50%, 75%, and 100% load conditions is higher than 80% at universal input
! Low standby mode power consumption (<1W at 230VAC input and 0.5W load)
! Reduce EMI noise through valley switching operation
! Enhanced system reliability through various protection functions
! Internal soft-start (17.5ms)
Key Design Notes
! The delay time for overload protection is designed to be about 23ms with C105 of 33nF. If faster/slower triggering of
OLP is required, C105 can be changed to a smaller/larger value (e.g. 100nF for 70ms).
! The input voltage of VSync must be between 4.7V and 8V just after MOSFET turn-off to guarantee hybrid control and
to avoid OVP triggering during normal operation.
! The SMD-type 100nF capacitor must be placed as close as possible to VCC pin to avoid malfunction by abrupt pul-
sating noises and to improve surge immunity.
1. Schematic
L201
5μH
FSQ0465 Rev.00
D201
MBRF10H100
T1
EER3016
14V, 1.8A
10
1
2
C202
1000μF
25V
C201
1000μF
25V
R103
51kΩ
1W
C104
3.3nF
630V
R102
75kΩ
8
D101
C103
100μF
400V
1N 4007
3
2
BD101
FSQ0465RU
2KBP06M
6
1
1
3
Vstr
Drain
Vcc
R105
100Ω 100nF 47μF
0.5W
SMD 50V
C106 C107
L202
5μH
5
4
D202
MBRF1060
Sync
5V, 2A
3
Vfb
4
7
4
GND
2
D102
UF 4004
C204
1000μF
10V
C203
2200μF
10V
C105
33nF
100V
C102
150nF
275VAC
R107
39kΩ
6
5
ZD101
1N4745A
C301
4.7nF
1kV
LF101
20mH
R108
33kΩ
R201
1kΩ
R101
2MΩ
1W
R204
8kΩ
R202
1.2kΩ
R203
18kΩ
C205
47nF
Optional components
IC301
FOD817A
IC201
KA431
C101
150nF
275VAC
RT1
5D-11
R205
8kΩ
F1
FUSE
250V
2A
Figure 37. Demo Circuit of FSQ0465RU
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
18
2. Transformer
Barrier tape
EER3019
1
10
9
N14V
1
Np/2
2
2
3
Np/2
Np/2
Na
4
7
5
6
Na
N5V
8
8
N14V
10
4
5
7
N5V
9
2
8
3
N5V
Np/2
6
TOP
BOT
Figure 38. Transformer Schematic Diagram of FSQ0465RU
3. Winding Specification
Barrier Tape
Position No Pin (s→f)
Bottom Np/2 3 → 2
Wire
Turns
Winding Method
TOP
BOT
Ts
0.35φ × 1
22
Solenoid Winding
-
-
-
-
-
1
Insulation: Polyester Tape t = 0.025mm, 2 Layers
N5V 8 → 9 0.4φ × 3(TIW) Solenoid Winding
Insulation: Polyester Tape t = 0.025mm, 2 Layers
N14V 10 → 8 0.4φ × 3(TIW) Solenoid Winding
Insulation: Polyester Tape t = 0.025mm, 2 Layers
N5V 7 → 6 0.4φ × 3(TIW) Solenoid Winding
Insulation: Polyester Tape t = 0.025mm, 2 Layers
Na 4 → 5 0.2φ × 1 Solenoid Winding
Insulation: Polyester Tape t = 0.025mm, 2 Layers
Np/2 2 → 1 0.35φ × 1 21 Solenoid Winding
Insulation: Polyester Tape t = 0.025mm, 2 Layers
3
-
-
-
5
3
6
5.0mm 2.0mm
1
1
-
2.0mm
Top
4. Electrical Characteristics
Pin
1 - 3
1 - 3
Specification
700µH ± 6%
Remarks
Inductance
Leakage
67kHz, 1V
15µH Maximum
Short all other pins
5. Core & Bobbin
! Core: EER3019 (Ae=137mm2)
! Bobbin: EER3019
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
19
6. Demo Board Part List
Part
Value
Note
Part
Value
Note
Resistor
C301
4.7nF/1kV
Ceramic Capacitor
R101
R102
R103
R105
1MΩ
75kΩ
51kΩ
100Ω
1W
1/2W
Inductor
Diode
L201
L202
5µH
5µH
5A Rating
5A Rating
1W
optional, 1/4W
1A, 1000V General-Purpose
Rectifier
R107
R108
R201
39kΩ
33kΩ
1kΩ
1/4W
1/4W
1/4W
D101
D102
IN4007
UF4004
1N4745A
1A, 400V Ultrafast Rectifier
1W 16V Zener Diode
(optional)
ZD101
R202
R203
R204
R205
1.2kΩ
18kΩ
8kΩ
1/4W
1/4W
1/4W
1/4W
D201
D202
MBRF10H100
MBRF1060
10A,100V Schottky Rectifier
10A,60V Schottky Rectifier
IC
8kΩ
IC101
IC201
IC202
FSQ0465RU
KA431 (TL431)
FOD817A
FPS™
Capacitor
Voltage Reference
Opto-Coupler
C101
C102
C103
C104
C105
C106
C107
150nF/275VAC
150nF/275VAC
100µF/400V
3.3nF/630V
33nF/50V
Box Capacitor
Box Capacitor
Fuse
Electrolytic Capacitor
Film Capacitor
Fuse
RT101
BD101
2A/250V
NTC
Ceramic Capacitor
SMD (1206)
5D-11
100nF/50V
47µF/50V
Bridge Diode
2KBP06M
Electrolytic Capacitor
Bridge Diode
Low-ESR Electrolytic
Capacitor
C201
C202
C203
1000µF/25V
1000µF/25V
2200µF/10V
Line Filter
Low-ESR Electrolytic
Capacitor
LF101
T1
20mH
Low-ESR Electrolytic
Capacitor
Transformer
Low-ESR Electrolytic
Capacitor
C204
C205
1000µF/10V
47nF/50V
EER3019
Ae=137mm2
Ceramic Capacitor
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
20
Package Dimensions
TO-220F-6L (Forming)
MKT-TO220A06revB
Figure 39. 6-Lead, TO-220 Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
21
© 2009 Fairchild Semiconductor Corporation
FSQ0465RU Rev. 1.0.0
www.fairchildsemi.com
22
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