FQU1P50 [FAIRCHILD]
500V P-Channel MOSFET; 500V P沟道MOSFET型号: | FQU1P50 |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | 500V P-Channel MOSFET |
文件: | 总9页 (文件大小:572K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
December 2000
TM
QFET
FQD1P50 / FQU1P50
500V P-Channel MOSFET
General Description
Features
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
•
•
•
•
•
•
-1.2A, -500V, R
= 10.5Ω @V = -10 V
DS(on) GS
Low gate charge ( typical 11 nC)
Low Crss ( typical 6.0 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
This advanced technology is especially tailored to minimize
on-state
resistance,
provide
superior
switching
performance, and withstand a high energy pulse in the
avalanche and commutation modes. These devices are
well suited for electronic lamp ballasts based on the
complementary half bridge topology.
S
!
D
●
●
G!
▶
▲
●
I-PAK
FQU Series
D-PAK
FQD Series
G
S
G
D
S
!
D
Absolute Maximum Ratings
T = 25°C unless otherwise noted
C
Symbol
Parameter
FQD1P50 / FQU1P50
Units
V
V
I
Drain-Source Voltage
-500
-1.2
DSS
- Continuous (T = 25°C)
Drain Current
A
D
C
- Continuous (T = 100°C)
-0.76
-4.8
A
C
I
(Note 1)
Drain Current
- Pulsed
A
DM
V
E
I
Gate-Source Voltage
± 30
110
V
GSS
AS
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Single Pulsed Avalanche Energy
Avalanche Current
mJ
A
-1.2
AR
E
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
3.8
mJ
V/ns
W
AR
dv/dt
-4.5
Power Dissipation (T = 25°C) *
2.5
P
A
D
Power Dissipation (T = 25°C)
38
W
C
- Derate above 25°C
Operating and Storage Temperature Range
0.3
W/°C
°C
T , T
-55 to +150
J
STG
Maximum lead temperature for soldering purposes,
1/8” from case for 5 seconds
T
300
°C
L
Thermal Characteristics
Symbol
Parameter
Typ
--
Max
3.29
50
Units
°C/W
°C/W
°C/W
R
R
R
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
θJC
θJA
θJA
--
--
110
* When mounted on the minimum pad size recommended (PCB Mount)
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
Elerical Characteristics
T = 25°C unless otherwise noted
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
V
= 0 V, I = -250 µA
GS D
Drain-Source Breakdown Voltage
-400
--
--
-
--
--
V
DSS
∆BV
Breakdown Voltage Temperature
Coefficient
DSS
J
I
= -250 µA, Referenced to 25°C
V/°C
D
/
I
∆T
V
V
V
V
= -500 V, V = 0 V
--
--
--
--
--
--
--
--
-1
µA
µA
nA
nA
DSS
DS
GS
Zero Gate Voltage Drain Current
= -400 V, T = 125°C
-10
DS
GS
GS
C
I
I
= -30 V, V = 0 V
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
-100
100
GSSF
DS
= 30 V, V = 0 V
GSSR
DS
On Characteristics
V
V
V
V
= V , I = -250 µA
Gate Threshold Voltage
-3.0
--
--
-5.0
10.5
--
V
Ω
S
GS(th)
DS
GS
DS
GS
D
R
Static Drain-Source
On-Resistance
DS(on)
= -10 V, I = -0.6 A
8.0
D
g
= -50 V, I = -0.6 A
(Note 4)
Forward Transconductance
--
1.12
FS
D
Dynamic Characteristics
C
C
C
Input Capacitance
--
--
--
270
40
350
50
pF
pF
pF
iss
V
= -25 V, V = 0 V,
GS
DS
Output Capacitance
oss
rss
f = 1.0 MHz
Reverse Transfer Capacitance
6.0
8.0
Switching Characteristics
t
t
t
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
--
--
--
--
--
--
--
9.0
25
27
30
11
30
60
65
70
14
--
ns
ns
d(on)
V
= -250 V, I = -1.5 A,
DD
D
r
R
= 25 Ω
G
ns
d(off)
f
(Note 4, 5)
ns
Q
Q
Q
nC
nC
nC
g
V
V
= -400 V, I = -1.5 A,
DS
D
2.0
5.6
= -10 V
gs
gd
GS
(Note 4, 5)
--
Drain-Source Diode Characteristics and Maximum Ratings
I
Maximum Continuous Drain-Source Diode Forward Current
--
--
--
--
--
--
--
-1.2
-4.8
-5.0
--
A
A
S
I
Maximum Pulsed Drain-Source Diode Forward Current
SM
V
t
V
V
= 0 V, I = -1.2 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
--
V
SD
GS
S
= 0 V, I = -1.5 A,
200
0.7
ns
µC
rr
GS
S
(Note 4)
dI / dt = 100 A/µs
Q
Reverse Recovery Charge
--
F
rr
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 138mH, I = -1.2A, V = -50V, R = 25 Ω, Starting T = 25°C
AS
DD
G
J
3. I ≤ -1.5A, di/dt ≤ 200A/µs, V ≤ BV
Starting T = 25°C
SD
DD
DSS,
J
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
Typical Characteristics
VGS
Top :
-15.0 V
-10.0 V
-8.0 V
-7.0 V
-6.5 V
-6.0 V
100
Bottom : -5.5 V
100
℃
150
-1
10
℃
25
※
Notes :
μ
※
Notes :
1. 250 s Pulse Test
℃
-55
1. VDS = -50V
2. 250 s Pulse Test
℃
2. TC = 25
μ
-2
-1
10
10
-1
100
101
2
4
6
8
10
10
-VGS , Gate-Source Voltage [V]
-VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
16
14
12
10
8
VGS = - 10V
VGS = - 20V
100
℃
150
℃
25
※
Notes :
1. VGS = 0V
※
℃
Note : T = 25
J
μ
2. 250 s Pulse Test
-1
6
10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
1
2
3
4
-ID , Drain Current [A]
-VSD , Source-Drain Voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
10
8
600
500
400
300
200
100
0
C
C
C
iss = Cgs + Cgd (Cds = shorted)
oss = Cds + Cgd
rss = C
VDS = -100V
VDS = -250V
gd
VDS = -400V
C
iss
6
Coss
※
Notes :
4
1. VGS = 0 V
2. f = 1 MHz
C
rss
2
※
Note : ID = -1.5 A
10
0
-1
10
100
101
0
2
4
6
8
12
-VDS, Drain-Source Voltage [V]
QG, Total Gate Charge [nC]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
Typical Characteristics (Continued)
1.2
1.1
1.0
2.5
2.0
1.5
1.0
0.5
0.0
※Notes :
1. VGS = 0 V
2. ID = -250 μA
0.9
0.8
※
Notes :
1. VGS = -10 V
2. ID = -0.75 A
-100
-50
0
50
100
150
200
-100
-50
0
50
100
150
200
TJ, Junction Temperature [oC]
T, Junction Temperature [oC]
J
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Operation in This Area
is Limited by R DS(on)
101
100
100 µs
1 ms
10 ms
DC
-1
10
※
Notes :
1. TC = 25 o
2. TJ = 150 o
3. Single Pulse
C
C
-2
10
100
101
102
103
25
50
75
100
125
150
℃
TC, Case Temperature [
]
-VDS, Drain-Source Voltage [V]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case Temperature
D = 0 .5
1 0 0
※
N o te s
:
℃
/W M a x .
1 . Z θ C (t)
=
3 .2 9
2 . D u ty F a c to r, D = t1 /t2
3 . T J M T C P D Z θ C (t)
0 .2
J
-
=
*
M
J
0 .1
0 .0 5
0 .0 2
PDM
1 0 -1
0 .0 1
t1
s in g le p u ls e
t2
1 0 -5
1 0 -4
1 0 -3
1 0 -2
1 0 -1
1 0 0
1 0 1
t1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
Gate Charge Test Circuit & Waveform
VGS
Same Type
50KΩ
as DUT
Qg
12V
200nF
-10V
300nF
VDS
VGS
Qgs
Qgd
DUT
-3mA
Charge
Resistive Switching Test Circuit & Waveforms
RL
t on
t off
VDS
td(on)
tr
td(off)
tf
VDD
VGS
VGS
RG
10%
DUT
-10V
90%
VDS
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
--------------------
BVDSS - VDD
L
1
2
2
----
EAS
=
LIAS
VDS
ID
t p
Time
VDD
VDS (t)
RG
VDD
ID (t)
DUT
-10V
IAS
t p
BVDSS
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
VDS
DUT
_
I SD
L
Driver
RG
Compliment of DUT
(N-Channel)
VDD
VGS
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
--------------------------
VGS
D =
Gate Pulse Period
10V
( Driver )
Body Diode Reverse Current
IRM
I SD
( DUT )
di/dt
IFM , Body Diode Forward Current
VSD
VDS
( DUT )
Body Diode
VDD
Forward Voltage Drop
Body Diode Recovery dv/dt
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
Package Dimensions
DPAK
6.60 ±0.20
5.34 ±0.30
2.30 ±0.10
0.50 ±0.10
(0.50)
(4.34)
(0.50)
MAX0.96
0.76 ±0.10
0.50 ±0.10
1.02 ±0.20
2.30 ±0.20
2.30TYP
2.30TYP
[2.30±0.20]
[2.30±0.20]
6.60 ±0.20
(5.34)
(5.04)
(1.50)
(2XR0.25)
0.76 ±0.10
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
Package Dimensions (Continued)
IPAK
2.30 ±0.20
0.50 ±0.10
6.60 ±0.20
5.34 ±0.20
(0.50)
(4.34)
(0.50)
MAX0.96
0.76 ±0.10
0.50 ±0.10
2.30TYP
2.30TYP
[2.30±0.20]
[2.30±0.20]
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
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not intended to be an exhaustive list of all such trademarks.
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MICROWIRE™
POP™
PowerTrench®
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Quiet Series™
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PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
INTERNATIONAL.
As used herein:
result in significant injury to the user.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
©2000 Fairchild Semiconductor International
Rev. A, January 2000
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