FQP630J69Z [FAIRCHILD]

Power Field-Effect Transistor, 9A I(D), 200V, 0.4ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-220, 3 PIN;
FQP630J69Z
型号: FQP630J69Z
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

Power Field-Effect Transistor, 9A I(D), 200V, 0.4ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-220, 3 PIN

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QFET N-CHANNEL  
FEATURES  
FQP630  
BV  
= 200V  
DSS  
Advanced New Design  
R
= 0.4Ω  
DS(ON)  
Avanced Rugged Technology  
Rugged Gate Oxide Technology  
Very Low Intrinsic Capacitances  
Excellent Switching Characteristics  
I = 9A  
D
TO-220  
R
: 0.55(Typ.)  
DS(ON)  
S-Correction Only  
1
2
3
1. Gate 2. Drain 3. Source  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Characteristics  
Drain-to-Source Voltage  
Continuous Drain Current (T = 25°C)  
Value  
200  
9
Units  
V
V
DSS  
C
I
A
D
Continuous Drain Current (T = 100°C)  
5.7  
36  
C
I
Drain Current-Pulsed  
V
J
DM  
V
Gate-to-Source Voltage  
Single Pulsed Avalanche Energy  
Avalanche Current  
±25  
162  
9
GS  
AS  
AR  
E
mJ  
A
I
E
Repetitive Avalanche Energy  
Peak Diode Recovery dv/dt  
7.8  
5.5  
mJ  
V/ns  
AR  
dv/dt  
Total Power Dissipation (T = 25°C)  
Linear Derating Factor  
78  
0.62  
W
W/°C  
C
P
D
Operating Junction and Storage  
Temperature Range  
T , T  
55 to +150  
J
STG  
°C  
Maximum Lead Temp. for Soldering  
Purposes, 1/8” from case for 5-seconds  
T
300  
L
THERMAL RESISTANCE  
Symbol  
Characteristics  
Junction-to-Case  
Case-to-Sink  
Typ.  
Max.  
Units  
R
0.5  
1.61  
θJC  
R
°C/W  
θCS  
R
Junction-to-Ambient  
62.5  
θJA  
REV. B  
1
1999 Fairchild Semiconductor Corporation  
FQP630  
QFET N-CHANNEL  
Test Conditions  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)  
C
Symbol  
BV  
Characteristics  
Min.  
200  
Typ.  
Max. Units  
Drain-Source Breakdown Votlage  
Breskdown Voltage Temp. Coeff.  
Gate Threshold Voltage  
0.20  
V
V
=0V, I =250µA  
DSS  
GS D  
BV/T  
V/°C I =250µA  
D
J
V
2.0  
4.0  
100  
100  
1
V
V
V
V
V
V
=5V, I =250µA  
GS(th)  
DS  
GS  
GS  
DS  
DS  
D
Gate-Source Leakage, Forward  
Gate-Source Leakage, Reverse  
=25V  
I
nA  
GSS  
DSS  
= 25V  
=200V  
I
Drain-to-Source Leakage Current  
µA  
10  
=160V, T =125°C  
C
Static Drain-Source  
On-State Resistance  
R
0.4  
V
V
=10V, I =4.5A  
DS(on)  
GS  
DS  
D
g
Forward Transconductance  
Input Capacitance  
4.4  
420  
85  
35  
8
S
=40V, I =4.5A  
fs  
D
C
550  
110  
45  
iss  
oss  
V
=0V, V =25V  
DS  
GS  
C
Output Capacitance  
Reverse Transfer Capacitance  
Turn-On Delay Time  
Rise Time  
pF  
ns  
f=1MHz  
C
rss  
t
30  
d(on)  
V
=100V, I =9A  
D
DD  
t
75  
47  
64  
19  
3
160  
110  
140  
25  
r
R =50Ω  
G
t
Turn-Off Delay Time  
Fall Time  
d(off)  
④ ⑤  
t
f
Q
Total Gate Charge  
g
V
=160V, V =10V  
GS  
DS  
Q
Gate-Source Charge  
Gate-Drain (Miller) Charge  
nC  
I =9A  
D
gs  
gd  
④ ⑤  
Q
9.5  
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS  
Symbol  
Characteristics  
Continuous Source Current  
Pulsed-Source Current  
Diode Forward Voltage  
Reverse Resovery Time  
Reverse Resovery Charge  
Min.  
Typ.  
Max. Units  
Test Conditions  
I
9
36  
1.5  
Integral reverse pn-diode  
in the MOSFET  
S
A
I
SM  
V
V
T =25°C, I =9A, V =0V  
J S GS  
SD  
150  
0.68  
ns  
µC  
T =25°C, I =9A, V =160V  
J
F
DD  
Q
rr  
di /dt=100A/µs  
F
Notes:  
Repetitive Rating: Pulse Width Limited by Maximum Junction Temperature  
L=3mH, I =9A, V =50V, R =25  
, Starting T =25°C  
AS  
DD  
G
J
I
9A, di/dt 300µs, V BV  
, Starting T =25°C  
SD  
DD  
DSS  
J
Pulse Test: Pulse Width  
300µs, Duty Cycle 2%  
Essentially Independent of Operating Temperature  
2
QFET N-CHANNEL  
FQP630  
Fig 1. Output Characteristics  
Fig 2. Transfer Characteristics  
VGS  
15.0 V  
10.0 V  
8.0 V  
7.0 V  
6.0 V  
5.5 V  
5.0 V  
Top :  
101  
100  
10-1  
1
10  
Bottom : 4.5 V  
0
10  
150¡É  
25¡É  
¡Ø Note :  
1. 250¥ìs Pulse Test  
2. TC = 25¡É  
¡Ø Note  
1. VDS = 40V  
2. 250¥ìs Pulse Test  
-55¡É  
-1  
10  
10-1  
100  
101  
2
4
6
8
10  
VDS, Drain-Source Voltage [V]  
VGS, Gate-Source Voltage [V]  
Fig 3. On-Resistance vs. Drain Current  
Fig 4. Source-Drain Diode Forward Voltage  
1.2  
0.9  
0.6  
0.3  
0.0  
101  
VGS = 10V  
VGS = 20V  
100  
¡Ø Note :  
1. VGS = 0V  
150¡É  
25¡É  
2. 250¥ìs Pulse Test  
¡Ø Note : T = 25¡É  
J
-1  
10  
0
4
8
12  
16  
20  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
1.4  
1.6  
1.8  
ID, Drain Current [A]  
VSD, Source-Drain voltage [V]  
Fig 5. Capacitance vs. Drain-Source Voltage  
Fig 6. Gate Charge vs. Gate-Source Voltage  
1200  
1000  
800  
600  
400  
200  
0
12  
10  
8
C
C
C
iss = Cgs + Cgd (Cds =shorted)  
oss = Cds + Cgd  
rss = Cgd  
VDS = 40V  
VDS = 100V  
VDS = 160V  
C
iss  
¡Ø Note ;  
1. VGS = 0 V  
2. F = 1 MHz  
Coss  
Crss  
6
4
2
¡Ø Note : I = 9A  
D
0
10-1  
100  
101  
0
5
10  
15  
20  
QG, Total Gate Charge [nC]  
VDS, Drain-Source Voltage [V]  
3
FQP630  
QFET N-CHANNEL  
Fig 7. Breakdown Voltage vs. Temperature  
Fig 8. On-Resistance vs. Temperature  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
1.2  
1.1  
1.0  
0.9  
0.8  
¡Ø Note :  
1. VGS = 0 V  
2. ID =250 ¥ìA  
¡Ø Note :  
1. VGS =10 V  
2. ID =4.5 A  
-100  
-50  
0
50  
100  
150  
200  
-100  
-50  
0
50  
100  
150  
200  
TJ, Junction Temperature [oC]  
TJ, Junction Temperature [oC]  
Fig 9. Max. Safe Operating Area  
Fig 10. Max. Drain Current vs. Case Temperature  
10  
Operation in This Area  
is Limited by R DS(on)  
102  
101  
100  
10-1  
8
6
4
2
0
100 µs  
1 ms  
10 ms  
DC  
¡ØNotes :  
1. TC = 25 o  
2. TJ = 150 o  
3. Single Pulse  
C
C
100  
101  
102  
25  
50  
75  
100  
125  
150  
[ C]  
°
TC, Case Temperature
VDS, Drain-Source Voltage [V]  
Fig 11. Thermal Response  
1 0 0  
D = 0 .5  
0 .2  
0 .1  
¡Ø N o t es  
:
1 . Z ¥ è J C(t ) = 1 .61 ¡É /W M ax .  
2 . D u ty Fac to r , D =t1 /t2  
3 . TJ M - T C = P D M * Z ¥ è J C(t )  
1 0 -1  
0 .0 5  
PDM  
0 .0 2  
0 .0 1  
t1  
s in g le p u ls e  
t2  
1 0 -2  
1 0 -5  
1 0 -4  
1 0 -3  
1 0 -2  
1 0 -1  
1 0 0  
1 0 1  
t1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]  
4
QFET N-CHANNEL  
FQP630  
Fig 12. Gate Charge Test Circuit & Waveform  
VGS  
Same Type  
50K  
as DUT  
Qg  
200nF  
12V  
10V  
300nF  
VDS  
VGS  
Qgs  
Qgd  
DUT  
3mA  
Charge  
Fig 13. Resistive Switching Test Circuit & Waveforms  
RL  
VDS  
90%  
VDS  
VDD  
RG  
( 0.5 rated VDS )  
10%  
Vin  
DUT  
10V  
td(on)  
tr  
td(off)  
tf  
t on  
toff  
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms  
BVDSS  
--------------------  
BVDSS -- VDD  
L
1
2
2
----  
EAS  
=
LL IAS  
VDS  
VDD  
BVDSS  
IAS  
ID  
RG  
ID (t)  
VDD  
VDS (t)  
DUT  
10V  
t p  
Time  
5
FQP630  
QFET N-CHANNEL  
Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms  
DUT  
+
VDS  
_
I S  
L
Driver  
RG  
Same Type  
as DUT  
VDD  
VGS  
• dv/dt controlled by RG  
• IS controlled by pulse period  
Gate Pulse Width  
--------------------------  
VGS  
D =  
Gate Pulse Period  
10V  
( Driver )  
IFM , Body Diode Forward Current  
I S  
di/dt  
( DUT )  
IRM  
Body Diode Reverse Current  
Body Diode Recovery dv/dt  
Vf  
VDS  
( DUT )  
VDD  
Body Diode  
Forward Voltage Drop  
6
TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is  
not intended to be an exhaustive list of all such trademarks.  
ACExª  
CoolFETª  
ISOPLANARª  
MICROWIREª  
POPª  
PowerTrenchª  
QSª  
UHCª  
VCXª  
CROSSVOLTª  
E2CMOSª  
FACTª  
FACT Quiet Seriesª  
Quiet Seriesª  
SuperSOTª-3  
SuperSOTª-6  
SuperSOTª-8  
TinyLogicª  
FAST¨  
FASTrª  
GTOª  
HiSeCª  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER  
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD  
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT  
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT  
RIGHTS, NOR THE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILDÕS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant into  
the body, or (b) support or sustain life, or (c) whose  
failure to perform when properly used in accordance  
with instructions for use provided in the labeling, can be  
reasonably expected to result in significant injury to the  
user.  
2. A critical component is any component of a life  
support device or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or  
In Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  

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