FQAF9N90 [FAIRCHILD]
900V N-Channel MOSFET; 900V N沟道MOSFET
| 型号： | FQAF9N90 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 900V N-Channel MOSFET |
| 文件： | 总8页 (文件大小：680K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2001
TM
QFET
FQAF9N90
900V N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supplies.
•
•
•
•
•
•
5.9A, 900V, R
= 1.3Ω @V = 10 V
DS(on) GS
Low gate charge ( typical 55 nC)
Low Crss ( typical 25 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
D
!
●
◀
▲
●
●
G!
TO-3PF
FQAF Series
G
D S
!
S
Absolute Maximum Ratings
T = 25°C unless otherwise noted
C
Symbol
Parameter
FQAF9N90
900
Units
V
V
I
Drain-Source Voltage
DSS
- Continuous (T = 25°C)
Drain Current
5.9
A
D
C
- Continuous (T = 100°C)
3.73
A
C
I
(Note 1)
Drain Current
- Pulsed
23.6
A
DM
V
E
I
Gate-Source Voltage
± 30
V
GSS
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Single Pulsed Avalanche Energy
Avalanche Current
900
mJ
A
AS
5.9
AR
E
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
11.3
mJ
V/ns
W
AR
dv/dt
4.0
P
Power Dissipation (T = 25°C)
113
D
C
- Derate above 25°C
Operating and Storage Temperature Range
0.91
W/°C
°C
T , T
-55 to +150
J
STG
Maximum lead temperature for soldering purposes,
T
300
°C
L
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
Parameter
Typ
--
Max
1.1
40
Units
°C/W
°C/W
R
R
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
θJC
θJA
--
©2001 Fairchild Semiconductor Corporation
Rev. A, March 2001
Electrical Characteristics
T = 25°C unless otherwise noted
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
V
= 0 V, I = 250 µA
GS D
Drain-Source Breakdown Voltage
900
--
--
--
--
V
DSS
∆BV
Breakdown Voltage Temperature
Coefficient
DSS
I
= 250 µA, Referenced to 25°C
1.0
V/°C
D
/
∆T
J
I
V
V
V
V
= 900 V, V = 0 V
--
--
--
--
--
--
--
--
10
100
100
-100
µA
µA
nA
nA
DSS
DS
GS
Zero Gate Voltage Drain Current
= 720 V, T = 125°C
DS
GS
GS
C
I
= 30 V, V = 0 V
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
GSSF
DS
I
= -30 V, V = 0 V
GSSR
DS
On Characteristics
V
V
V
V
= V , I = 250 µA
Gate Threshold Voltage
3.0
--
--
5.0
1.3
--
V
Ω
S
GS(th)
DS
GS
DS
GS
D
R
Static Drain-Source
On-Resistance
DS(on)
=10V,I =2.95 A
1.0
7.3
D
g
= 50 V, I = 2.95 A
(Note 4)
Forward Transconductance
--
FS
D
Dynamic Characteristics
C
C
C
Input Capacitance
--
--
--
2100
200
25
2700
260
33
pF
pF
pF
iss
V
= 25 V, V = 0 V,
GS
DS
Output Capacitance
oss
rss
f = 1.0 MHz
Reverse Transfer Capacitance
Switching Characteristics
t
t
t
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
--
--
--
--
--
--
--
45
100
135
80
100
210
280
170
72
ns
ns
d(on)
V
= 450 V, I = 8.6 A,
DD
D
r
R
= 25 Ω
G
ns
d(off)
f
(Note 4, 5)
(Note 4, 5)
ns
Q
Q
Q
55
nC
nC
nC
g
V
V
= 720 V, I = 8.6 A,
DS
D
12
--
= 10 V
gs
gd
GS
26
--
Drain-Source Diode Characteristics and Maximum Ratings
I
Maximum Continuous Drain-Source Diode Forward Current
--
--
--
--
--
--
--
5.9
23.6
1.4
--
A
A
S
I
Maximum Pulsed Drain-Source Diode Forward Current
SM
V
t
V
V
= 0 V, I = 5.9 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
--
V
SD
GS
S
= 0 V, I = 8.6 A,
720
7.6
ns
µC
rr
GS
S
(Note 4)
dI / dt = 100 A/µs
Q
Reverse Recovery Charge
--
F
rr
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 48.8mH, I = 5.9A, V = 50V, R = 25 Ω, Starting T = 25°C
AS
DD
G
J
3. I ≤ 8.6A, di/dt ≤ 200A/µs, V
≤ BV Starting T = 25°C
SD
DD
DSS, J
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2001 Fairchild Semiconductor Corporation
Rev. A, March 2001
Typical Characteristics
V
Top :
15.0GVS
10.0V
8.0V
7.0V
6.5V
6.0V
1
10
101
Bottom: 5.5 V
150oC
0
10
25oC
100
-55oC
※
※
Notes :
Notes :
μ
1. V = 50V
2. 250 s Pulse Test
1. 250 s Pulse Test
DS μ
-1
10
℃
2. TC = 25
-1
10
-1
10
0
10
1
10
2
4
6
8
10
VGS, Gate-Source Voltage [V]
VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
2.4
2.1
1.8
1.5
1.2
0.9
101
VGS = 10V
VGS = 20V
100
℃
150
℃
25
※
Notes :
1. V = 0V
GS μ
2. 250 s Pulse Test
※
℃
Note : T = 25
J
-1
10
0
5
10
15
20
25
30
0.2
0.4
0.6
0.8
1.0
1.2
1.4
ID, Drain Current [A]
VSD, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation with Source Current
and Temperature
4000
3000
2000
1000
0
12
10
8
C
iss = Cgs + Cgd (Cds = shorted)
Coss = Cds + C
gd
Crss = C
gd
VDS = 180V
VDS = 450V
C
iss
VDS = 720V
C
oss
6
4
C
rss
※
Notes :
1. VGS = 0 V
2. f = 1 MHz
2
※
Note: ID = 8.6 A
50
0
-1
1
10
10
100
0
10
20
30
40
60
QG, Total Gate Charge [nC]
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
©2001 Fairchild Semiconductor Corporation
Rev. A, March 2001
Typical Characteristics (Continued)
1.2
1.1
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
※Notes :
0.9
1. VGS = 0 V
※
Notes :
2. ID= 250 μA
1. VGS = 10 V
2. ID = 4.3 A
0.8
-100
-100
-50
0
50
100
150
200
-50
0
50
100
150
200
TJ, Junction Temperature [oC]
T, Junction Temperature [oC]
J
Figure 7. Breakdown Voltage Variation
vs Temperature
Figure 8. On-Resistance Variation
vs Temperature
6
5
4
3
2
1
0
102
Operation in This Area
is Limited by R DS(on)
10 µs
101
100
100 µs
1 ms
10 ms
DC
-1
10
※
Notes :
1. TC = 25 oC
2. T = 150 oC
J
3. Single Pulse
-2
10
10
102
0
1
10
3
10
25
50
75
100
125
150
℃
TC, Case Temperature [
]
VDS, Drain-Source Voltage [V]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs Case Temperature
1 0 0
D = 0 .5
※
N otes
1. Zθ (t)
2. D uJtCy Factor, D =t1/t2
:
℃
/W M ax.
=
1.1
0 .2
3. TJM
-
TC
=
P D M
*
Zθ JC (t)
0 .1
1 0 -1
0 .0 5
PDM
0 .0 2
t1
0 .0 1
t2
sin g le p u lse
1 0 -2
1 0-5
1 0-4
1 0-3
1 0-2
1 0-1
1 00
1 01
t1 , S qu a re W ave P u lse D u ra tion [se c]
Figure 11. Transient Thermal Response Curve
©2001 Fairchild Semiconductor Corporation
Rev. A, March 2001
Gate Charge Test Circuit & Waveform
VGS
Same Type
50Kꢀ
as DUT
Qg
12V
200nF
10V
300nF
VDS
VGS
Qgs
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
RL
VDS
90%
VDS
VDD
VGS
RG
10%
VGS
DUT
10V
td(on)
tr
td(off)
tf
t on
t off
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
--------------------
BVDSS - VDD
L
1
2
2
----
EAS
=
L IAS
VDS
I D
BVDSS
IAS
RG
VDD
ID (t)
VDD
VDS (t)
DUT
10V
t p
t p
Time
©2001 Fairchild Semiconductor Corporation
Rev. A, March 2001
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
DUT
VDS
_
I SD
L
Driver
RG
Same Type
as DUT
VDD
VGS
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
--------------------------
VGS
D =
Gate Pulse Period
10V
( Driver )
IFM , Body Diode Forward Current
I SD
di/dt
( DUT )
IRM
Body Diode Reverse Current
Body Diode Recovery dv/dt
VSD
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
©2001 Fairchild Semiconductor Corporation
Rev. A, March 2001
Package Dimensions
TO-3PF
5.50 ±0.20
3.00 ±0.20
15.50 ±0.20
ø3.60 ±0.20
(1.50)
0.85 ±0.03
2.00 ±0.20
2.00 ±0.20
2.00 ±0.20
2.00 ±0.20
3.30 ±0.20
4.00 ±0.20
+0.20
–0.10
0.75
5.45TYP
[5.45 ±0.30]
5.45TYP
[5.45 ±0.30]
+0.20
–0.10
0.90
©2001 Fairchild Semiconductor Corporation
Rev. A, March 2001
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
FAST®
PACMAN™
SuperSOT™-3
ACEx™
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOS™
EnSigna™
FASTr™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
POP™
PowerTrench®
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SLIENT SWITCHER®
SMART START™
Star* Power™
Stealth™
UltraFET®
VCX™
FACT™
FACT Quiet Series™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
©2001 Fairchild Semiconductor Corporation
Rev. H1
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