FM93CS06LVMT8
更新时间:2024-09-18 18:37:32
品牌:FAIRCHILD
描述:EEPROM, 16X16, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8
FM93CS06LVMT8 概述
EEPROM, 16X16, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8 EEPROM
FM93CS06LVMT8 规格参数
是否无铅: | 含铅 | 是否Rohs认证: | 不符合 |
生命周期: | Obsolete | 零件包装代码: | SOIC |
包装说明: | TSSOP, TSSOP8,.25 | 针数: | 8 |
Reach Compliance Code: | unknown | ECCN代码: | EAR99 |
HTS代码: | 8542.32.00.51 | 风险等级: | 5.92 |
最大时钟频率 (fCLK): | 0.25 MHz | 数据保留时间-最小值: | 40 |
耐久性: | 1000000 Write/Erase Cycles | JESD-30 代码: | R-PDSO-G8 |
JESD-609代码: | e0 | 长度: | 4.4 mm |
内存密度: | 256 bit | 内存集成电路类型: | EEPROM |
内存宽度: | 16 | 功能数量: | 1 |
端子数量: | 8 | 字数: | 16 words |
字数代码: | 16 | 工作模式: | SYNCHRONOUS |
最高工作温度: | 125 °C | 最低工作温度: | -40 °C |
组织: | 16X16 | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | TSSOP | 封装等效代码: | TSSOP8,.25 |
封装形状: | RECTANGULAR | 封装形式: | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
并行/串行: | SERIAL | 峰值回流温度(摄氏度): | NOT SPECIFIED |
电源: | 3/5 V | 认证状态: | Not Qualified |
座面最大高度: | 1.2 mm | 串行总线类型: | MICROWIRE |
最大待机电流: | 0.00001 A | 子类别: | EEPROMs |
最大压摆率: | 0.001 mA | 最大供电电压 (Vsup): | 5.5 V |
最小供电电压 (Vsup): | 2.7 V | 标称供电电压 (Vsup): | 3.3 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | AUTOMOTIVE | 端子面层: | Tin/Lead (Sn/Pb) |
端子形式: | GULL WING | 端子节距: | 0.65 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | NOT SPECIFIED |
宽度: | 3 mm | 最长写入周期时间 (tWC): | 15 ms |
写保护: | HARDWARE/SOFTWARE | Base Number Matches: | 1 |
FM93CS06LVMT8 数据手册
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PDF下载July 2000
FM93CS06
(MICROWIRE™ Bus Interface) 256-Bit Serial EEPROM
with Data Protect and Sequential Read
General Description
Features
FM93CS06 is a 256-bit CMOS non-volatile EEPROM organized
as 16 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compat-
ible to many of standard Microcontrollers and Microprocessors.
FM93CS06 offers programmable write protection to the memory
array using a special register called Protect Register. Selected
memory locations can be protected against write by programming
this Protect Register with the address of the first memory location
to be protected (all locations greater than or equal to this first
addressarethenprotectedfromfurtherchange). Additionally, this
address can be “permanently locked” into the device, making all
future attempts to change data impossible. In addition this device
features “sequential read”, by which, entire memory can be read
in one cycle instead of multiple single byte read cycles. There are
10 instructions implemented on the FM93CS06, 5 of which are for
memory operations and the remaining 5 are for Protect Register
operations. This device is fabricated using Fairchild Semiconduc-
torfloating-gateCMOSprocessforhighreliability,highendurance
and low power consumption.
I Wide VCC 2.7V - 5.5V
I Programmable write protection
I Sequential register read
I Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I No Erase instruction required before Write instruction
I Self timed write cycle
I Device status during programming cycles
I 40 year data retention
I Endurance: 1,000,000 data changes
I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
“LZ” and “L” versions of FM93CS06 offer very low standby current
makingthemsuitableforlowpowerapplications.Thisdeviceisoffered
in both SO and TSSOP packages for small space considerations.
Functional Diagram
VCC
CS
SK
INSTRUCTION
DECODER
CONTROL LOGIC
AND CLOCK
PRE
PE
INSTRUCTION
REGISTER
DI
GENERATORS
COMPARATOR
AND
WRITE ENABLE
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
ADDRESS
REGISTER
PROTECT
REGISTER
DECODER
EEPROM ARRAY
16
READ/WRITE AMPS
16
VSS
DATA IN/OUT REGISTER
16 BITS
DO
DATA OUT BUFFER
1
© 2000 Fairchild Semiconductor International
FM93CS06 Rev. C.1
www.fairchildsemi.com
Connection Diagram
Dual-In-Line Package (N)
8–Pin SO (M8) and 8–Pin TSSOP (MT8)
1
2
3
4
8
7
6
5
CS
SK
DI
VCC
PRE
PE
DO
GND
Top View
Package Number
N08E, M08A and MTC08
Pin Names
CS
SK
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
DI
DO
GND
PE
Program Enable
Protect Register Enable
Power Supply
PRE
VCC
Ordering Information
FM
93
CS XX LZ
E
XXX
Letter Description
Package
N
8-pin DIP
M8
MT8
8-pin SO
8-pin TSSOP
Temp. Range
None
0 to 70°C
V
E
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
4.5V to 5.5V
2.7V to 5.5V
LZ
2.7V to 5.5V and
<1µA Standby Current
Density
06
256 bits
C
CMOS
CS
Data protect and sequential
read
Interface
93
MICROWIRE
Fairchild Memory Prefix
2
www.fairchildsemi.com
FM93CS06 Rev. C.1
Absolute Maximum Ratings (Note 1)
Operating Conditions
Ambient Storage Temperature
-65°C to +150°C
Ambient Operating Temperature
FM93CS06
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltages
with Respect to Ground
+6.5V to -0.3V
FM93CS06E
FM93CS06V
Lead Temperature
(Soldering, 10 sec.)
+300°C
Power Supply (VCC
)
4.5V to 5.5V
ESD rating
2000V
DC and AC Electrical Characteristics VCC = 4.5V to 5.5V unless otherwise specified
SymbolParameter
Conditions
Min
Max
Units
ICCA
Operating Current
CS = VIH, SK=1.0 MHz
1
mA
ICCS
Standby Current
CS = VIL
50
-1
µA
µA
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
VIL
VIH
Input Low Voltage
Input High Voltage
-0.1
2
0.8
VCC +1
V
V
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
IOH = -400 µA
IOL = 10 µA
IOH = -10 µA
(Note 3)
0.4
0.2
1
2.4
VOL2
VOH2
Output Low Voltage
Output High Voltage
VCC - 0.2
fSK
SK Clock Frequency
SK High Time
MHz
ns
tSKH
0°C to +70°C
-40°C to +125°C
250
300
tSKL
tCS
SK Low Time
250
250
ns
ns
Minimum CS Low Time
(Note 4)
tCSS
tPRES
tDH
CS Setup Time
PRE Setup Time
DO Hold Time
PE Setup Time
DI Setup Time
50
50
ns
ns
ns
ns
ns
70
tPES
tDIS
50
100
tCSH
tPEH
tPREH
tDIH
CS Hold Time
PE Hold Time
PRE Hold Time
DI Hold Time
Output Delay
0
ns
ns
ns
ns
ns
250
50
20
tPD
500
500
tSV
CS to Status Valid
ns
tDF
CS to DO in Hi-Z
Write Cycle Time
CS = VIL
100
10
ns
tWP
ms
3
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FM93CS06 Rev. C.1
Absolute Maximum Ratings (Note 1)
Operating Conditions
Ambient Storage Temperature
-65°C to +150°C
Ambient Operating Temperature
FM93CS06L/LZ
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltages
with Respect to Ground
+6.5V to -0.3V
FM93CS06LE/LZE
FM93CS06LV/LZV
Lead Temperature
(Soldering, 10 sec.)
+300°C
Power Supply (VCC
)
2.7V to 5.5V
ESD rating
2000V
DC and AC Electrical Characteristics VCC = 2.7V to 4.5V unless otherwise specified. Refer to
page 3 for VCC = 4.5V to 5.5V.
SymbolParameter
Conditions
Min
Max
Units
ICCA
Operating Current
CS = VIH, SK= 250 KHz
1
mA
ICCS
Standby Current
L
CS = VIL
10
1
µA
µA
LZ (2.7V to 4.5V)
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
1
µA
VIL
VIH
Input Low Voltage
Input High Voltage
-0.1
0.8VCC
0.15VCC
VCC +1
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 10µA
IOH = -10µA
0.1VCC
V
0.9VCC
fSK
tSKH
tSKL
SK Clock Frequency
SK High Time
(Note 3)
0
1
1
250
KHz
µs
µs
SK Low Time
tCS
Minimum CS Low Time
(Note 4)
1
µs
tCSS
tPRES
tDH
CS Setup Time
PRE Setup Time
DO Hold Time
PE Setup Time
DI Setup Time
0.2
50
70
50
0.4
µs
ns
ns
ns
µs
tPES
tDIS
tCSH
tPEH
tPREH
tDIH
CS Hold Time
PE Hold Time
PRE Hold Time
DI Hold Time
Output Delay
0
ns
ns
ns
µs
µs
250
50
0.4
tPD
2
1
tSV
CS to Status Valid
µs
tDF
CS to DO in Hi-Z
Write Cycle Time
CS = VIL
0.4
15
µs
ms
tWP
Note 1: Stressabovethoselistedunder“AbsoluteMaximumRatings”maycausepermanentdamage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditionsabovethoseindicatedintheoperationalsectionsofthespecificationisnotimplied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Capacitance TA = 25°C, f = 1 MHz or 250
KHz(Note 5)
Note 2: Typical leakage values are in the 20nA range.
Note 3: TheshortestallowableSKclockperiod=1/fSK (asshownunderthefSK parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not
allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
SymbolTest
Typ Max Units
COUT
CIN
Output Capacitance
Input Capacitance
5
pF
pF
Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
5
Note 5: This parameter is periodically sampled and not 100% tested.
AC Test Conditions
VCC Range
VIL/VIH
Input Levels
0.3V/1.8V
VIL/VIH
VOL/VOH
Timing Level
0.8V/1.5V
IOL/IOH
Timing Level
2.7V ≤ VCC ≤ 5.5V
1.0V
10µA
(Extended Voltage Levels)
4.5V ≤ VCC ≤ 5.5V
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
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FM93CS06 Rev. C.1
Program Enable (PE)
Pin Description
This is an active high input pin to the device and is used to enable
operations, that are write in nature, to the memory array and to the
Protect register. When this pin is held high, operations that are
“write” in nature are enabled. When this pin is held low, operations
that are “write” in nature are disabled. This pin operates in
conjunctionwithPREpin. ReferTable1forfunctionalmatrixofthis
pin for various operations.
Chip Select (CS)
ThisisanactivehighinputpintoFM93CS06EEPROM(thedevice)
and is generated by a master that is controlling the device. A high
level on this pin selects the device and a low level deselects the
device. All serial communications with the device is enabled only
when this pin is held high. However this pin cannot be permanently
tied high, as a rising edge on this signal is required to reset the
internal state-machine to accept a new cycle and a falling edge to
initiateaninternalprogrammingafterawritecycle.Allactivityonthe
SK, DI and DO pins are ignored while CS is held low.
Microwire Interface
AtypicalcommunicationontheMicrowirebusismadethroughthe
CS, SK, DI and DO signals. To facilitate various operations on the
Memory array and on the Protect Register, a set of 10 instructions
are implemented on FM93CS06. The format of each instruction is
listed in Table 1.
Serial Clock (SK)
Thisisaninputpintothedeviceandisgeneratedbythemasterthat
is controlling the device. This is a clock signal that synchronizes the
communicationbetweenamasterandthedevice. Allinputinforma-
tion(DI)tothedeviceislatchedontherisingedgeofthisclockinput,
whileoutputdata(DO)fromthedeviceisdrivenfromtherisingedge
of this clock input. This pin is gated by CS signal.
Instruction
Each of the above 10 instructions is explained under individual
instruction descriptions.
Start Bit
Serial Input (DI)
This is a 1-bit field and is the first bit that is clocked into the device
whenaMicrowirecyclestarts.Thisbithastobe“1”foravalidcycle
to begin. Any number of preceding “0” can be clocked into the
device before clocking a “1”.
This is an input pin to the device and is generated by the master
that is controlling the device. The master transfers Input informa-
tion (Start bit, Opcode bits, Array addresses and Data) serially via
this pin into the device. This Input information is latched on the
rising edge of the SCK. This pin is gated by CS signal.
Opcode
Serial Output (DO)
This is a 2-bit field and should immediately follow the start bit.
These two bits (along with PRE, PE signals and 2 MSB of address
field) select a particular instruction to be executed.
This is an output pin from the device and is used to transfer Output
data via this pin to the controlling master. Output data is serially
shifted out on this pin from the rising edge of the SCK. This pin is
active only when the device is selected.
Address Field
This is a 6-bit field and should immediately follow the Opcode bits.
In FM93CS06, only the LSB 4 bits are used for address decoding
during READ, WRITE and PRWRITE instructions. During these
instructions (READ, WRITE and PRWRITE), the MSB 2 bits are
"don't care" (can be 0 or 1). During all other instructions (with the
exception of PRREAD), the MSB 2 bits are used to decode
instruction (along with Opcode bits, PRE and PE signals).
Protect Register Enable (PRE)
This is an active high input pin to the device and is used to
distinguish operations to memory array and operations to Protect
Register. When this pin is held low, operations to the memory
array are enabled. When this pin is held high, operations to the
Protect Register are enabled. This pin operates in conjunction
with PE pin. Refer Table1 for functional matrix of this pin for
various operations.
Data Field
This is a 16-bit field and should immediately follow the Address
bits. Only the WRITE and WRALL instructions require this field.
D15 (MSB) is clocked first and D0 (LSB) is clocked last (both
during writes as well as reads).
TABLE 1. Instruction set
Instruction
READ
Start Bit
Opcode Field
Address Field
Data Field PRE Pin
PE Pin
1
1
1
1
1
1
1
1
1
1
10
00
01
00
00
10
00
11
01
00
X
1
X
0
0
X
1
1
X
0
X
1
X
1
0
X
1
1
X
0
A3 A2 A1 A0
0
0
X
1
1
1
X
X
1
1
1
1
WEN
X
X
X
X
WRITE
WRALL
WDS
A3 A2 A1 A0
D15-D0
D15-D0
0
0
0
1
1
1
1
1
X
X
X
X
1
X
X
X
X
1
X
X
X
X
1
X
X
X
X
1
PRREAD
PREN
PRCLEAR
PRWRITE
PRDS
A3 A2 A1 A0
0
0
0
0
5
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FM93CS06 Rev. C.1
the part. Input information (Start bit, Opcode and Address) for this
WEN instruction should be issued as listed under Table1. The
device becomes write-enabled at the end of this cycle when the
CS signal is brought low. The PRE pin should be held low during
thiscycle.ExecutionofaREADinstructionisindependentofWEN
instruction. Refer Write Enable cycle diagram.
Functional Description
A typical Microwire cycle starts by first selecting the device
(bringing the CS signal high). Once the device is selected, a valid
Start bit (“1”) should be issued to properly recognize the cycle.
Following this, the 2-bit opcode of appropriate instruction should
be issued. After the opcode bits, the 6-bit address information
should be issued. For certain instructions, some (or all) of these
6 bits are don’t care values (can be “0” or “1”), but they should still
be issued. Following the address information, depending on the
instruction (WRITE and WRALL), 16-Bit data is issued. Other-
wise, depending on the instruction (READ and PRREAD), the
device starts to drive the output data on the DO line. Other
instructions perform certain control functions and do not deal with
data bits. The Microwire cycle ends when the CS signal is brought
low. However during certain instructions, falling edge of the CS
signal initiates an internal cycle (Programming), and the device
remains busy till the completion of the internal cycle. Each of the
10 instructions is explained in detail in the following sections.
3) Write (WRITE)
WRITE instruction allows write operation to a specified location in
the memory with a specified data. This instruction is valid only
when the following are true:
I Device is write-enabled (Refer WEN instruction)
I Address of the write location is not write-protected
I PE pin is held high during this cycle
I PRE pin should be held low during this cycle
Input information (Start bit, Opcode, Address and Data) for this
WRITE instruction should be issued as listed under Table1. After
inputtingthelastbitofdata(D0bit), CSsignalmustbebroughtlow
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Memory Instructions
Following five instructions, READ, WEN, WRITE, WRALL and
WDS are specific to operations intended for memory array. The
PRE pin should be held low during these instructions.
1) Read and Sequential Read (READ)
The status of the internal programming cycle can be polled at any
time by bringing the CS signal high again, after tCS interval. When
CS signal is high, the DO pin indicates the READY/BUSY status
of the chip. DO = logical 0 indicates that the programming is still
in progress. DO = logical 1 indicates that the programming is
finished and the device is ready for another instruction. It is not
required to provide the SK clock during this status polling. While
the device is busy, it is recommended that no new instruction be
issued. Refer Write cycle diagram.
READ instruction allows data to be read from a selected location
in the memory array. Input information (Start bit, Opcode and
Address) for this instruction should be issued as listed under
Table1. Upon receiving a valid input information, decoding of the
opcode and the address is made, followed by data transfer from
the selected memory location into a 16-bit serial-out shift register.
This 16-bit data is then shifted out on the DO pin. D15 bit (MSB)
is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit
(logical 0) precedes this 16-bit data output string. Output data
changes are initiated on the rising edge of the SK clock. After
reading the 16-bit data, the CS signal can be brought low to end
the Read cycle. The PRE pin should be held low during this cycle.
Refer Read cycle diagram.
It is also recommended to follow this instruction (after the device
becomes READY) with a Write Disable (WDS) instruction to
safeguarddataagainstcorruptionduetospuriousnoise,inadvert-
ent writes etc.
4) Write All (WRALL)
This device also offers “sequential memory read” operation to
allowreadingofdatafromtheadditionalmemorylocationsinstead
ofjustonelocation.Itisstartedinthesamemannerasnormalread
but the cycle is continued to read further data (instead of terminat-
ing after reading the first 16-bit data). After providing 16-bit data,
the device automatically increments the address pointer to the
next location and continues to provide the data from that location.
Any number of locations can be read out in this manner, however,
after reading out from the last location, the address pointer points
back to the first location. If the cycle is continued further, data will
be read from this first location onward. In this mode of read, the
dummy-bit is present only when the very first data is read (like
normal read cycle) and is not present on subsequent data reads.
The PRE pin should be held low during this cycle. Refer Sequen-
tial Read cycle diagram.
Write all (WRALL) instruction is similar to the Write instruction
except that WRALL instruction will simultaneously program all
memorylocationswiththedatapatternspecifiedintheinstruction.
This instruction is valid only when the following are true:
I Protect Register has been cleared (Refer PRCLEAR
instruction)
I Device is write-enabled (Refer WEN instruction)
I PE pin is held high during this cycle
I PRE pin should be held low during this cycle
Input information (Start bit, Opcode, Address and Data) for this
WRALL instruction should be issued as listed under Table1. After
inputtingthelastbitofdata(D0bit), CSsignalmustbebroughtlow
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. ReferWrite All
cycle diagram.
2) Write Enable (WEN)
When VCC is applied to the part, it “powers up” in the Write Disable
(WDS) state. Therefore, all programming operations (for both
memory array and Protect Register) must be preceded by a Write
Enable (WEN) instruction. Once a Write Enable instruction is
executed, programming remains enabled until a Write Disable
(WDS) instruction is executed or VCC is completely removed from
6
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FM93CS06 Rev. C.1
content of the Protect Register with a pattern of all 1s. However,
in this case, WRITE operation to the last memory address
(0x001111) is still enabled. PRCLEAR instruction is enabled
(valid) only when the following are true:
5) Write Disable (WDS)
Write Disable (WDS) instruction disables all programming opera-
tions and is recommended to follow all programming operations.
Executing this instruction after a valid write instruction would
protect against accidental data disturb due to spurious noise,
glitches,inadvertentwritesetc.Inputinformation(Startbit,Opcode
and Address) for this WDS instruction should be issued as listed
under Table1. The device becomes write-disabled at the end of
this cycle when the CS signal is brought low. Execution of a READ
instructionisindependentofWDSinstruction. ReferWriteDisable
cycle diagram.
I PREN instruction was executed immediately prior to
PRCLEAR instruction
I PE pin is held high during this cycle
I PRE pin is held high during this cycle
Inputinformation(Startbit,OpcodeandAddress)forthisPRCLEAR
instructionshouldbeissuedaslistedunderTable1. Afterinputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed clear cycle. It takes tWP time (Refer
appropriate DC and AC Electrical Characteristics table) for the
internal clear cycle to finish. During this time, the device remains
busyandisnotreadyforanotherinstruction. Statusoftheinternal
programmingcanbepolledasdescribedunderWRITEinstruction
description. While the device is busy, it is recommended that no
new instruction be issued. Refer Protect Register Clear cycle
diagram.
Protect Register Instructions
Following five instructions, PRREAD, PREN, PRCLEAR,
PRWRITE and PRDS are specific to operations intended for
Protect Register. The PRE pin should be held high during these
instructions.
1) Protect Register Read (PRREAD)
This instruction reads the content of the internal Protect Register.
Content of this register is 6-bit wide and is the starting address of
the “write-protected” section of the memory array. All memory
locationsgreaterthanorequaltothisaddressarewrite-protected.
Inputinformation(Startbit,OpcodeandAddress)forthisPRREAD
instruction should be issued as listed under Table1. Upon receiv-
ing a valid input information, decoding of the opcode and the
address is made, followed by data transfer (address information)
from the Protect Register. This 6-bit data is then shifted out on the
DO pin with the MSB first and the LSB last. Like the READ
instruction a dummy-bit (logical 0) precedes this 6-bit data output
string. Output data changes are initiated on the rising edge of the
SK clock. After reading the 6-bit data, the CS signal can be
brought low to end the PRREAD cycle. The PRE pin should be
held high during this cycle. Refer Protect Register Read cycle
diagram.
4) Protect Register Write (PRWRITE)
Thisinstructionisusedtowritethestartingaddressofthememory
section to be write-protected into the Protect register. After the
execution of PRWRITE instruction, all memory locations greater
than or equal to this address are write-protected. PRWRITE
instruction is enabled (valid) only the following are true:
I PRCLEAR instruction was executed first (to clear the Protect
Register)
I PREN instruction was executed immediately prior to
PRWRITE instruction
I PE pin is held high during this cycle
I PRE pin is held high during this cycle
Inputinformation(Startbit,OpcodeandAddress)forthisPRWRITE
instructionshouldbeissuedaslistedunderTable1. Afterinputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer Protect
Register Write cycle diagram.
Though the content of this register is 6-bit wide, only the last 4 bits
(LSB) are valid for FM93CS06 device.
2) Protect Register Enable (PREN)
This instruction is required to enable PRCLEAR, PRWRITE and
PRDS instructions and should be executed prior to executing
PRCLEAR, PRWRITE and PRDS instructions. However, this
PREN instruction is enabled (valid) only the following are true
I Device is write-enabled (Refer WEN instruction)
I PE pin is held high during this cycle
I PRE pin is held high during this cycle
5) Protect Register Disable (PRDS)
Input information (Start bit, Opcode and Address) for this PREN
instruction should be issued as listed under Table1. The Protect
Register becomes enabled for PRCLEAR, PRWRITE and PRDS
instructions at the end of this cycle when the CS signal is brought
low. Note that this PREN instruction must immediately precede
a PRCLEAR, PRWRITE or PRDS instruction. In other words, no
other instruction should be executed between a PREN instruction
and a PRCLEAR, PRWRITE or PRDS instruction. Refer Protect
Register Enable cycle diagram.
Unlike all other instructions, this instruction is a one-time-only
instruction which when executed permanently write-protects
the Protect Register and renders it unalterable in the future. This
instruction is useful to safeguard vital data (typically read only
data) in the memory against any possible corruption. PRDS
instruction is enabled (valid) only the following are true:
I PREN instruction was executed immediately prior to PRDS
instruction
3) Protect Register Clear (PRCLEAR)
I PE pin is held high during this cycle
I PRE pin is held high during this cycle
This instruction clears the content of the Protect register and
therefore enables write operations (WRITE or WRALL) to all
memory locations. Executing this instruction will program the
7
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FM93CS06 Rev. C.1
Input information (Start bit, Opcode and Address) for this PRDS
instructionshouldbeissuedaslistedunderTable1. Afterinputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. The Protect
Register is permanently write-protected at the end of this cycle.
Refer Protect Register Disable cycle diagram.
Clearing of Ready/Busy status
When programming is in progress, the Data-Out pin will display
the programming status as either BUSY (low) or READY (high)
when CS is brought high (DO output will be tri-stated when CS is
low). To restate, during programming, the CS pin may be brought
high and low any number of times to view the programming status
without affecting the programming operation. Once programming
is completed (Output in READY state), the output is ‘cleared’
(returned to normal tri-state condition) by clocking in a Start Bit.
After the Start Bit is clocked in, the output will return to a tri-stated
condition. When clocked in, this Start Bit can be the first bit in a
command string, or CS can be brought low again to reset all
internal circuits. Refer Clearing Ready Status diagram.
Related Document
Application Note: AN758 - Using Fairchild’s MICROWIRE™ EE-
PROM.
8
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FM93CS06 Rev. C.1
Timing Diagrams
SYNCHRONOUS DATA TIMING
CS
SK
PRE
PE
DI
t
t
t
t
CSH
CSS
SKH
SKL
t
t
PREH
PRES
t
t
PEH
PES
t
t
DIH
DIS
Valid
Input
Valid
Input
t
PD
t
t
DF
t
t
PD
DH
Valid
Output
Valid
Output
DO (Data Read)
DF
t
SV
Valid Status
DO (Status Read)
NORMAL READ CYCLE (READ)
PRE
PE
tCS
CS
SK
1
1
0
A5
A4
A1
A0
DI
Start Opcode
Bit Bits(2)
Address
Bits(6)
High - Z
0
D15
D1
D0
DO
Dummy
Bit
93CS06:
Address bits pattern -> x-x-A3-A2-A1-A0; (x -> Don't Care, can be 0 or 1); (A3-A0 -> User defined)
SEQUENTIAL READ CYCLE (PRE = 0; PE = X)
PRE
t
CS
CS
SK
1
1
0
A5
A0
DI
Start Opcode
Bit Bits(2)
Address
Bits(6)
High - Z
0
D15
D0
D15
D0
D15
D0
DO
Dummy
Bit
Data(n)
Data(n+1)
Data(n+2)
93CS06:
Address bits pattern -> x-x-A3-A2-A1-A0; (x -> Don't Care, can be 0 or 1); (A3-A0 -> User defined)
9
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FM93CS06 Rev. C.1
Timing Diagrams (Continued)
WRITE ENABLE CYCLE (WEN)
PRE
PE
tCS
CS
SK
DI
1
0
0
A5
A4
A1
A0
Start Opcode
Bit Bits(2)
Address
Bits(6)
High - Z
DO
93CS06:
Address bits pattern -> 1-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
WRITE DISABLE CYCLE (WDS)
PRE
PE
t
CS
CS
SK
DI
1
0
0
A5
A4
A1
A0
Start Opcode
Bit Bits(2)
Address
Bits(6)
High - Z
DO
93CS06:
Address bits pattern -> 0-0-x-x-x-x; (x -> Don't Care, can be 0 or 1)
WRITE CYCLE (WRITE)
PRE
PE
t
CS
CS
SK
1
0
1
A5
A4
A1
A0
D15 D14
D1
D0
DI
t
WP
Start Opcode
Bit Bits(2)
Address
Bits(6)
Data
Bits(16)
High - Z
Ready
DO
Busy
93CS06:
Address bits pattern -> x-x-A3-A2-A1-A0; (x -> Don't Care, can be 0 or 1); (A3-A0 -> User defined)
Data bits pattern -> User defined
10
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FM93CS06 Rev. C.1
Timing Diagrams (Continued)
WRITE ALL CYCLE (WRALL)
PRE
PE
tCS
CS
SK
DI
1
0
0
A5
A4
A1
A0
D15 D14
D1
D0
tWP
Start Opcode
Bit Bits(2)
Address
Bits(6)
Data
Bits(16)
High - Z
Ready
DO
Busy
93CS06:
Address bits pattern -> 0-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Data bits pattern -> User defined
PROTECT REGISTER READ CYCLE (PRREAD)
PRE
PE
tCS
CS
SK
1
1
0
A5
A4
A1
A0
DI
Start Opcode
Bit Bits(2)
Address
Bits(6)
High - Z
0
D5
D1
D0
DO
Dummy
Bit
93CS06:
Address bits pattern -> x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Of the 6-bit output data(D5-D0), only D3 to D0 are valid and they correspond to A3 to A0 respectively.
PROTECT REGISTER ENABLE CYCLE (PREN)
PRE
PE
tCS
CS
SK
1
0
0
A5
A4
A1
A0
DI
Start Opcode
Bit Bits(2)
Address
Bits(6)
High - Z
DO
93CS06:
Address bits pattern -> 1-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
11
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FM93CS06 Rev. C.1
Timing Diagrams (Continued)
PROTECT REGISTER CLEAR CYCLE (PRCLEAR)
PRE
PE
tCS
CS
SK
DI
1
1
1
A5
A4
A1
A0
tWP
Start Opcode
Bit Bits(2)
Address
Bits(6)
High - Z
Ready
DO
Busy
93CS06:
Address bits pattern -> 1-1-1-1-1-1
PROTECT REGISTER WRITE CYCLE (PRWRITE)
PRE
PE
t
CS
CS
SK
DI
1
0
1
A5
A4
A1
A0
t
WP
Start Opcode
Bit Bits(2)
Address
Bits(6)
High - Z
Ready
DO
Busy
93CS06:
Address bits pattern -> x-x-A3-A2-A1-A0; (x -> Don't Care, can be 0 or 1); (A3-A0 -> User defined)
PROTECT REGISTER DISABLE CYCLE (PRDS)
PRE
PE
tCS
CS
SK
1
0
0
A5
A4
A1
A0
DI
tWP
Start Opcode
Bit Bits(2)
Address
Bits(6)
High - Z
Ready
DO
Busy
93CS06:
Address bits pattern -> 0-0-0-0-0-0
12
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FM93CS06 Rev. C.1
Timing Diagrams (Continued)
CLEARING READY STATUS
PRE
PE
CS
SK
DI
Start
Bit
High - Z
High - Z
Ready
DO
Busy
Note: This Start bit can also be part of a next instruction. Hence the cycle
can be continued(instead of getting terminated, as shown) as if a new
instruction is being issued.
13
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FM93CS06 Rev. C.1
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8
7
6
5
0.228 - 0.244
(5.791 - 6.198)
1
2
3
4
Lead #1
IDENT
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
0.010 - 0.020
(0.254 - 0.508)
0.004 - 0.010
(0.102 - 0.254)
x 45¡
8¡ Max, Typ.
All leads
Seating
Plane
0.004
(0.102)
All lead tips
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020
Typ.
(0.356 - 0.508)
Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8)
Package Number M08A
14
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FM93CS06 Rev. C.1
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122
(2.90 - 3.10)
8
5
(7.72) Typ
(4.16) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
Land pattern recommendation
1
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0256 (0.65)
Typ.
Gage
plane
0.0075 - 0.0118
(0.19 - 0.30)
0¡-8¡
DETAIL A
Typ. Scale: 40X
0.0075 - 0.0098
(0.19 - 0.25)
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
15
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FM93CS06 Rev. C.1
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
7
0.032 0.005
(0.813 0.127)
RAD
8
7
6
5
4
0.092
(2.337)
DIA
0.250 - 0.005
(6.35 0.127)
Pin #1
IDENT
+
Pin #1 IDENT
1
Option 1
1
2
3
Option 2
0.280
MIN
0.040
(1.016)
Typ.
(7.112)
0.030
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
MAX
(0.762)
0.300 - 0.320
(7.62 - 8.128)
20° 1°
0.130 0.005
(3.302 0.127)
0.125 - 0.140
95° 5°
(3.175 - 3.556)
0.065
(1.651)
0.125
(3.175)
DIA
0.020
90° 4°
Typ
0.009 - 0.015
(0.229 - 0.381)
(0.508)
Min
0.018 0.003
(0.457 0.076)
NOM
+0.040
-0.015
0.325
0.100 0.010
+1.016
-0.381
8.255
(2.540 0.254)
0.045 0.015
(1.143 0.381)
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a)areintendedforsurgicalimplantintothebody,or(b)support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Americas
Fairchild Semiconductor
Europe
Fairchild Semiconductor
Hong Kong
Fairchild Semiconductor
Japan Ltd.
Customer Response Center
Tel. 1-888-522-5372
Fax:
Tel:
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Tel:
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+44 (0) 1793-856858
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+49 (0) 8141-6102-0
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Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
16
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FM93CS06 Rev. C.1
FM93CS06LVMT8 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
FM93CS06LVMT8X | FAIRCHILD | EEPROM, 16X16, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8 | 获取价格 | |
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FM93CS06LZEMT8 | FAIRCHILD | EEPROM, 16X16, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8 | 获取价格 | |
FM93CS06LZEN | FAIRCHILD | EEPROM, 16X16, Serial, CMOS, PDIP8, PLASTIC, DIP-8 | 获取价格 | |
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FM93CS06LZM8X | FAIRCHILD | EEPROM, 16X16, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, SO-8 | 获取价格 | |
FM93CS06LZMT8 | FAIRCHILD | EEPROM, 16X16, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8 | 获取价格 | |
FM93CS06LZN | ETC | Microwire Serial EEPROM | 获取价格 |
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