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FDS8870 [FAIRCHILD]

N-Channel PowerTrench MOSFET; N沟道PowerTrench MOSFET的
FDS8870
型号： FDS8870
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述：

N-Channel PowerTrench MOSFET
N沟道PowerTrench MOSFET的

晶体 晶体管 功率场效应晶体管 开关 光电二极管 PC
文件： 总12页 (文件大小：260K)
中文：  中文翻译
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April 2005  
FDS8870  
N-Channel PowerTrench MOSFET  
®
30V, 18A, 4.2mΩ  
Features  
General Description  
rDS(ON) = 4.2mΩ, VGS = 10V, ID = 18A  
This N-Channel MOSFET has been designed specifically to  
improve the overall efficiency of DC/DC converters using  
either synchronous or conventional switching PWM  
controllers. It has been optimized for low gate charge, low  
rDS(ON) = 4.9mΩ, VGS = 4.5V, ID = 17A  
High performance trench technology for extremely low  
rDS(ON)  
r
DS(ON) and fast switching speed.  
Low gate charge  
High power and current handling capability  
Applications  
DC/DC converters  
Branding Dash  
5
6
7
8
4
3
2
1
5
1
2
3
4
SO-8  
©2005 Fairchild Semiconductor Corporation  
FDS8870 Rev. A3  
1
www.fairchildsemi.com  
MOSFET Maximum Ratings TA = 25°C unless otherwise noted  
Symbol  
VDSS  
VGS  
Parameter  
Ratings  
30  
Units  
Drain to Source Voltage  
Gate to Source Voltage  
Drain Current  
V
V
±20  
Continuous (TA = 25oC, VGS = 10V, RθJA = 50oC/W)  
Continuous (TA = 25oC, VGS = 4.5V, RθJA = 50oC/W)  
Pulsed  
18  
17  
A
A
ID  
Figure 4  
420  
A
EAS  
Single Pulse Avalanche Energy (Note 1)  
mJ  
Power dissipation  
Derate above 25oC  
2.5  
W
PD  
20  
mW/oC  
oC  
TJ, TSTG  
Operating and Storage Temperature  
-55 to 150  
Thermal Characteristics  
RθJC  
RθJA  
RθJA  
Thermal Resistance, Junction to Case (Note 2)  
25  
50  
85  
oC/W  
oC/W  
oC/W  
Thermal Resistance, Junction to Ambient at 10 seconds (Note 3)  
Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3)  
Package Marking and Ordering Information  
Device Marking  
FDS8870  
Device  
FDS8870  
Package  
SO-8  
Reel Size  
330mm  
Tape Width  
Quantity  
12mm  
12mm  
2500 units  
2500 units  
FDS8870  
FDS8870_NL (Note 4)  
SO-8  
330mm  
Electrical Characteristics TA = 25°C unless otherwise noted  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Units  
Off Characteristics  
BVDSS  
Drain to Source Breakdown Voltage  
Zero Gate Voltage Drain Current  
Gate to Source Leakage Current  
ID = 250µA, VGS = 0V  
30  
-
-
-
-
-
-
V
V
DS = 24V  
1
IDSS  
µA  
VGS = 0V  
TA = 150oC  
-
250  
±100  
IGSS  
VGS = ±20V  
-
nA  
On Characteristics  
VGS(TH)  
Gate to Source Threshold Voltage  
VGS = VDS, ID = 250µA  
1.2  
-
2.5  
V
ID = 18A, VGS = 10V  
-
-
0.0035 0.0042  
0.0039 0.0049  
I
D = 17A, VGS = 4.5V  
rDS(ON)  
Drain to Source On Resistance  
Ω
ID = 18A, VGS = 10V,  
TA = 150oC  
-
0.0055 0.0072  
Dynamic Characteristics  
CISS  
COSS  
CRSS  
RG  
Input Capacitance  
-
4615  
900  
450  
2.0  
85  
-
-
pF  
pF  
pF  
Ω
VDS = 15V, VGS = 0V,  
f = 1MHz  
Output Capacitance  
-
Reverse Transfer Capacitance  
Gate Resistance  
-
-
VGS = 0.5V, f = 1MHz  
VGS = 0V to 10V  
0.5  
3.5  
112  
62  
6.0  
-
Qg(TOT)  
Qg(5)  
Qg(TH)  
Qgs  
Total Gate Charge at 10V  
Total Gate Charge at 5V  
Threshold Gate Charge  
Gate to Source Gate Charge  
Gate Charge Threshold to Plateau  
Gate to Drain “Miller” Charge  
-
-
-
-
-
-
nC  
nC  
nC  
nC  
nC  
nC  
VDD = 15V  
D = 18A  
Ig = 1.0mA  
VGS = 0V to 5V  
VGS = 0V to 1V  
45  
I
4.6  
11  
Qgs2  
Qgd  
6.4  
15  
-
-
2
www.fairchildsemi.com  
FDS8870 Rev. A3  
Switching Characteristics (VGS = 10V)  
tON  
td(ON)  
tr  
Turn-On Time  
Turn-On Delay Time  
Rise Time  
-
-
-
-
-
-
-
86  
ns  
ns  
ns  
ns  
ns  
ns  
9
-
48  
60  
21  
-
-
VDD = 15V, ID = 18A  
GS = 10V, RGS = 3.3Ω  
V
td(OFF)  
tf  
Turn-Off Delay Time  
Fall Time  
-
-
tOFF  
Turn-Off Time  
122  
Drain-Source Diode Characteristics  
I
SD = 18A  
-
-
-
-
-
-
-
-
1.25  
1.0  
37  
V
V
VSD  
Source to Drain Diode Voltage  
ISD = 2.1A  
trr  
Reverse Recovery Time  
ISD = 18A, dISD/dt = 100A/µs  
ISD = 18A, dISD/dt = 100A/µs  
ns  
nC  
QRR  
Reverse Recovered Charge  
22  
Notes:  
1: Starting T = 25°C, L = 1mH, I = 29A, V = 30V, V = 10V.  
J
AS  
DD  
GS  
2: R  
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the  
θJA  
drain pins. R  
is guaranteed by design while R  
is determined by the user’s board design.  
θJC  
θJA  
2
3: R  
is measured with 1.0 in copper on FR-4 board  
θJA  
4: FDS8870_NL is lead free product. FDS8870_NL marking will appear on the reel label.  
3
www.fairchildsemi.com  
FDS8870 Rev. A3  
Typical Characteristics TA = 25°C unless otherwise noted  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
20  
15  
V
= 10V  
V
= 4.5V  
GS  
GS  
10  
5
o
R
=50 C/W  
θJA  
0
0
25  
50  
75  
100  
125  
150  
25  
50  
75  
T , AMBIENT TEMPERATURE ( C)  
A
100  
125  
150  
o
o
T
, AMBIENT TEMPERATURE ( C)  
A
Figure 1. Normalized Power Dissipation vs  
Ambient Temperature  
Figure 2. Maximum Continuous Drain Current vs  
Ambient Temperature  
2
DUTY CYCLE - DESCENDING ORDER  
1
0.5  
o
R
=50 C/W  
0.2  
θJA  
0.1  
0.05  
0.02  
0.01  
0.1  
P
DM  
t
1
0.01  
t
2
SINGLE PULSE  
NOTES:  
DUTY FACTOR: D = t /t  
1
2
PEAK T = P  
x Z  
x R  
+ T  
A
J
DM  
θJA  
θJA  
0.001  
-5  
-4  
-3  
-2  
-1  
0
1
2
3
10  
10  
10  
10  
10  
10  
10  
10  
10  
t, RECTANGULAR PULSE DURATION (s)  
Figure 3. Normalized Maximum Transient Thermal Impedance  
2000  
TRANSCONDUCTANCE  
o
MAY LIMIT CURRENT  
IN THIS REGION  
T
= 25 C  
A
1000  
100  
10  
FOR TEMPERATURES  
o
ABOVE 25 C DERATE PEAK  
CURRENT AS FOLLOWS:  
V
= 10V  
GS  
150 - T  
A
I = I  
25  
125  
-5  
-4  
-3  
-2  
-1  
0
1
2
3
10  
10  
10  
10  
10  
t, PULSE WIDTH (s)  
10  
10  
10  
10  
Figure 4. Peak Current Capability  
4
www.fairchildsemi.com  
FDS8870 Rev. A3  
Typical Characteristics TA = 25°C unless otherwise noted  
100  
50  
40  
30  
20  
10  
0
If R = 0  
= (L)(I )/(1.3*RATED BV  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
t
- V  
DD  
)
AV  
If R ≠ 0  
AS  
DSS  
V
= 15V  
t
AV  
= (L/R)ln[(I *R)/(1.3*RATED BV  
AS  
- V ) +1]  
DSS DD  
DD  
o
STARTING T = 25 C  
J
o
10  
T = 150 C  
J
o
o
T
= 25 C  
J
STARTING T = 150 C  
J
o
T
= -55 C  
J
1
1.50  
1.75  
2.00  
2.25  
2.50  
2.75  
3.00  
0.1  
1
10  
100  
t
, TIME IN AVALANCHE (ms)  
AV  
V
, GATE TO SOURCE VOLTAGE (V)  
GS  
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515  
Figure 5. Unclamped Inductive Switching  
Capability  
Figure 6. Transfer Characteristics  
50  
15  
12  
9
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
V
= 10V  
GS  
V
= 4V  
I
= 18A  
GS  
D
40  
30  
20  
10  
0
V
= 5V  
GS  
V
= 3V  
GS  
V
= 2.5V  
GS  
6
o
T
= 25 C  
A
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
3
0
0.1  
0.2  
0.3  
0.4  
2
4
6
8
10  
V
, DRAIN TO SOURCE VOLTAGE (V)  
V
GS  
, GATE TO SOURCE VOLTAGE (V)  
DS  
Figure 7. Saturation Characteristics  
Figure 8. Drain to Source On Resistance vs Gate  
Voltage and Drain Current  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
1.4  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
V
= V , I = 250µA  
DS D  
GS  
1.2  
1.0  
0.8  
0.6  
0.4  
V
= 10V, I = 18A  
D
GS  
-80  
-40  
0
40  
80  
120  
160  
-80  
-40  
0
40  
80  
120  
160  
o
o
T , JUNCTION TEMPERATURE ( C)  
T , JUNCTION TEMPERATURE ( C)  
J
J
Figure 9. Normalized Drain to Source On  
Resistance vs Junction Temperature  
Figure 10. Normalized Gate Threshold Voltage vs  
Junction Temperature  
5
www.fairchildsemi.com  
FDS8870 Rev. A3  
Typical Characteristics TA = 25°C unless otherwise noted  
1.10  
1.05  
1.00  
0.95  
0.90  
10000  
I
= 250µA  
D
C
= C + C  
GS GD  
ISS  
C
C
+ C  
DS GD  
OSS  
C
= C  
GD  
RSS  
1000  
300  
V
= 0V, f = 1MHz  
GS  
-80  
-40  
0
40  
80  
120  
160  
30  
0.1  
1
10  
o
T , JUNCTION TEMPERATURE ( C)  
J
V
DS  
, DRAIN TO SOURCE VOLTAGE (V)  
Figure 11. Normalized Drain to Source  
Breakdown Voltage vs Junction Temperature  
Figure 12. Capacitance vs Drain to Source  
Voltage  
10  
V
= 15V  
DD  
8
6
4
2
0
WAVEFORMS IN  
DESCENDING ORDER:  
I
I
= 18A  
= 1A  
D
D
0
20  
40  
Q , GATE CHARGE (nC)  
60  
80  
g
Figure 13. Gate Charge Waveforms for Constant Gate Currents  
6
www.fairchildsemi.com  
FDS8870 Rev. A3  
Test Circuits and Waveforms  
V
BV  
DSS  
DS  
t
P
V
DS  
L
I
AS  
V
DD  
VARY t TO OBTAIN  
P
+
-
R
REQUIRED PEAK I  
G
AS  
V
DD  
V
GS  
DUT  
t
P
I
0V  
AS  
0
0.01Ω  
t
AV  
Figure 14. Unclamped Energy Test Circuit  
Figure 15. Unclamped Energy Waveforms  
V
DS  
V
Q
DD  
g(TOT)  
V
GS  
V
DS  
L
V
= 10V  
GS  
Q
g(5)  
V
GS  
+
-
Q
gs2  
V
= 5V  
GS  
V
DD  
DUT  
V
= 1V  
GS  
I
g(REF)  
0
Q
g(TH)  
Q
Q
gs  
gd  
I
g(REF)  
0
Figure 16. Gate Charge Test Circuit  
Figure 17. Gate Charge Waveforms  
V
DS  
t
t
ON  
OFF  
t
d(OFF)  
t
d(ON)  
R
t
t
f
L
r
V
DS  
90%  
90%  
+
V
GS  
V
DD  
10%  
10%  
0
-
DUT  
90%  
50%  
R
GS  
V
GS  
50%  
PULSE WIDTH  
10%  
V
GS  
0
Figure 18. Switching Time Test Circuit  
Figure 19. Switching Time Waveforms  
7
www.fairchildsemi.com  
FDS8870 Rev. A3  
Thermal Resistance vs. Mounting Pad Area  
The maximum rated junction temperature, TJM, and the  
thermal resistance of the heat dissipating path determines  
the maximum allowable device power dissipation, PDM, in an  
maximum transient thermal impedance curve.  
Thermal resistances corresponding to other copper areas  
can be obtained from Figure 21 or by calculation using  
Equation 2. The area, in square inches is the top copper  
area including the gate and source pads.  
application.  
Therefore the application’s ambient  
temperature, TA (oC), and thermal resistance RθJA (oC/W)  
must be reviewed to ensure that TJM is never exceeded.  
Equation 1 mathematically represents the relationship and  
serves as the basis for establishing the rating of the part.  
26  
R
= 64 + -------------------------------  
(EQ. 2)  
θ JA  
0.23 + Area  
(T  
– T )  
JM  
A
(EQ. 1)  
P
= ------------------------------  
DM  
RθJA  
The transient thermal impedance (ZθJA) is also effected by  
varied top copper board area. Figure 22 shows the effect of  
copper pad area on single pulse transient thermal  
impedance. Each trace represents a copper pad area in  
square inches corresponding to the descending list in the  
graph. Spice and SABER thermal models are provided for  
each of the listed pad areas.  
In using surface mount devices such as the SO8 package,  
the environment in which it is applied will have a significant  
influence on the part’s current and maximum power  
dissipation ratings. Precise determination of PDM is complex  
and influenced by many factors:  
Copper pad area has no perceivable effect on transient  
thermal impedance for pulse widths less than 100ms. For  
pulse widths less than 100ms the transient thermal  
impedance is determined by the die and package.  
Therefore, CTHERM1 through CTHERM5 and RTHERM1  
through RTHERM5 remain constant for each of the thermal  
models. A listing of the model component values is available  
in Table 1.  
1. Mounting pad area onto which the device is attached and  
whether there is copper on one side or both sides of the  
board.  
2. The number of copper layers and the thickness of the  
board.  
3. The use of external heat sinks.  
4. The use of thermal vias.  
200  
5. Air flow and board orientation.  
R
= 64 + 26/(0.23+Area)  
θJA  
6. For non steady state applications, the pulse width, the  
duty cycle and the transient thermal response of the part,  
the board and the environment they are in.  
150  
Fairchild provides thermal information to assist the  
designer’s preliminary application evaluation. Figure 21  
defines the RθJA for the device as a function of the top  
copper (component side) area. This is for a horizontally  
positioned FR-4 board with 1oz copper after 1000 seconds  
of steady state power with no air flow. This graph provides  
the necessary information for calculation of the steady state  
junction temperature or power dissipation. Pulse  
applications can be evaluated using the Fairchild device  
Spice thermal model or manually utilizing the normalized  
100  
50  
0.001  
0.01  
0.1  
1
2
10  
AREA, TOP COPPER AREA (in )  
Figure 21. Thermal Resistance vs Mounting  
Pad Area  
150  
COPPER BOARD AREA - DESCENDING ORDER  
2
0.04 in  
2
0.28 in  
0.52 in  
0.76 in  
1.00 in  
120  
90  
60  
30  
0
2
2
2
-1  
0
1
2
3
10  
10  
10  
t, RECTANGULAR PULSE DURATION (s)  
10  
10  
Figure 22. Thermal Impedance vs Mounting Pad Area  
8
www.fairchildsemi.com  
FDS8870 Rev. A3  
PSPICE Electrical Model  
.SUBCKT FDS8870 2 1 3 ;  
Ca 12 8 2.8e-9  
rev March 2004  
Cb 15 14 2.8e-9  
Cin 6 8 4.3e-9  
Dbody 7 5 DbodyMOD  
Dbreak 5 11 DbreakMOD  
Dplcap 10 5 DplcapMOD  
LDRAIN  
DPLCAP  
DRAIN  
2
5
10  
Ebreak 11 7 17 18 33.62  
Eds 14 8 5 8 1  
Egs 13 8 6 8 1  
Esg 6 10 6 8 1  
Evthres 6 21 19 8 1  
Evtemp 20 6 18 22 1  
RLDRAIN  
RSLC1  
51  
DBREAK  
+
RSLC2  
5
ESLC  
11  
51  
-
+
50  
-
17  
DBODY  
RDRAIN  
6
8
EBREAK 18  
-
ESG  
It 8 17 1  
EVTHRES  
+
16  
21  
+
-
19  
8
MWEAK  
Lgate 1 9 1e-9  
Ldrain 2 5 1.0e-9  
Lsource 3 7 7e-11  
LGATE  
EVTEMP  
RGATE  
GATE  
1
+
6
-
18  
22  
MMED  
9
20  
MSTRO  
8
RLGATE  
RLgate 1 9 10  
RLdrain 2 5 10  
RLsource 3 7 0.7  
LSOURCE  
CIN  
SOURCE  
3
7
RSOURCE  
RLSOURCE  
Mmed 16 6 8 8 MmedMOD  
Mstro 16 6 8 8 MstroMOD  
Mweak 16 21 8 8 MweakMOD  
S1A  
S2A  
RBREAK  
12  
15  
13  
8
14  
13  
17  
18  
RVTEMP  
19  
-
S1B  
S2B  
Rbreak 17 18 RbreakMOD 1  
Rdrain 50 16 RdrainMOD 3.05e-3  
Rgate 9 20 2  
RSLC1 5 51 RSLCMOD 1e-6  
RSLC2 5 50 1e3  
Rsource 8 7 RsourceMOD 9e-4  
Rvthres 22 8 RvthresMOD 1  
Rvtemp 18 19 RvtempMOD 1  
S1a 6 12 13 8 S1AMOD  
S1b 13 12 13 8 S1BMOD  
S2a 6 15 14 13 S2AMOD  
S2b 13 15 14 13 S2BMOD  
13  
CB  
CA  
IT  
14  
+
+
VBAT  
6
8
5
8
EGS  
EDS  
+
-
-
8
22  
RVTHRES  
Vbat 22 19 DC 1  
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))}  
.MODEL DbodyMOD D (IS=1E-11 IKF=17 N=1.01 RS=2.8e-3 TRS1=2e-3 TRS2=2e-7  
+ CJO=1.95e-9 M=0.55 TT=9e-11 XTI=2.6)  
.MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6)  
.MODEL DplcapMOD D (CJO=1.42e-9 IS=1e-30 N=10 M=0.38)  
.MODEL MmedMOD NMOS (VTO=1.85 KP=15 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2)  
.MODEL MstroMOD NMOS (VTO=2.2 KP=650 IS=1e-30 N=10 TOX=1 L=1u W=1u)  
.MODEL MweakMOD NMOS (VTO=1.48 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=20 RS=0.1)  
.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-9e-7)  
.MODEL RdrainMOD RES (TC1=1.8e-3 TC2=5e-6)  
.MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6)  
.MODEL RsourceMOD RES (TC1=8e-3 TC2=1e-6)  
.MODEL RvthresMOD RES (TC1=-1.8e-3 TC2=-9e-6)  
.MODEL RvtempMOD RES (TC1=-2.5e-3 TC2=2e-7)  
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-3)  
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-5)  
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5)  
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2)  
.ENDS  
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global  
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank  
Wheatley.  
9
www.fairchildsemi.com  
FDS8870 Rev. A3  
SABER Electrical Model  
REV March 2004  
template FDS8870 n2,n1,n3  
electrical n2,n1,n3  
{
var i iscl  
dp..model dbodymod = (isl=1e-11,ikf=17,nl=1.01,rs=2.8e-3,trs1=2e-3,trs2=2e-7,cjo=1.95e-9,m=0.55,tt=9e-11,xti=2.6)  
dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6)  
dp..model dplcapmod = (cjo=1.42e-9,isl=10e-30,nl=10,m=0.38)  
m..model mmedmod = (type=_n,vto=1.85,kp=15,is=1e-30, tox=1)  
m..model mstrongmod = (type=_n,vto=2.2,kp=650,is=1e-30, tox=1)  
m..model mweakmod = (type=_n,vto=1.48,kp=0.05,is=1e-30, tox=1,rs=0.1)  
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5,voff=-3)  
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-5)  
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-0.5)  
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2)  
c.ca n12 n8 = 2.8e-9  
LDRAIN  
DPLCAP  
DRAIN  
2
5
10  
RLDRAIN  
RSLC1  
51  
c.cb n15 n14 = 2.8e-9  
c.cin n6 n8 = 4.3e-9  
RSLC2  
ISCL  
DBREAK  
11  
dp.dbody n7 n5 = model=dbodymod  
dp.dbreak n5 n11 = model=dbreakmod  
dp.dplcap n10 n5 = model=dplcapmod  
50  
-
RDRAIN  
6
8
ESG  
DBODY  
EVTHRES  
+
16  
21  
+
-
19  
8
spe.ebreak n11 n7 n17 n18 = 33.62  
MWEAK  
LGATE  
EVTEMP  
spe.eds n14 n8 n5 n8 = 1  
spe.egs n13 n8 n6 n8 = 1  
spe.esg n6 n10 n6 n8 = 1  
spe.evthres n6 n21 n19 n8 = 1  
spe.evtemp n20 n6 n18 n22 = 1  
RGATE  
GATE  
1
6
+
-
18  
22  
EBREAK  
+
MMED  
9
20  
MSTRO  
8
17  
18  
-
RLGATE  
LSOURCE  
CIN  
SOURCE  
3
7
RSOURCE  
i.it n8 n17 = 1  
RLSOURCE  
S1A  
S2A  
RBREAK  
l.lgate n1 n9 = 1e-9  
l.ldrain n2 n5 = 1.0e-9  
l.lsource n3 n7 = 7e-11  
12  
15  
13  
8
14  
13  
17  
18  
RVTEMP  
19  
S1B  
S2B  
13  
CB  
CA  
res.rlgate n1 n9 = 10  
res.rldrain n2 n5 = 10  
res.rlsource n3 n7 = 0.7  
IT  
14  
-
+
+
VBAT  
6
8
5
8
EGS  
EDS  
+
-
-
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u  
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u  
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u  
22  
RVTHRES  
res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-9e-7  
res.rdrain n50 n16 = 3.05e-3, tc1=1.8e-3,tc2=5e-6  
res.rgate n9 n20 = 2  
res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=1e-6  
res.rslc2 n5 n50 = 1e3  
res.rsource n8 n7 = 9e-4, tc1=8e-3,tc2=1e-6  
res.rvthres n22 n8 = 1, tc1=-1.8e-3,tc2=-9e-6  
res.rvtemp n18 n19 = 1, tc1=-2.5e-3,tc2=2e-7  
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod  
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod  
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod  
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod  
v.vbat n22 n19 = dc=1  
equations {  
i (n51->n50) +=iscl  
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10))  
}
}
10  
www.fairchildsemi.com  
FDS8870 Rev. A3  
SPICE Thermal Model  
JUNCTION  
th  
REV March 2004  
FDS8870T  
Copper Area =1.0 in2  
CTHERM1 TH 8 2.0e-3  
CTHERM2 8 7 5.0e-3  
CTHERM3 7 6 1.0e-2  
CTHERM4 6 5 4.0e-2  
CTHERM5 5 4 9.0e-2  
CTHERM6 4 3 2e-1  
CTHERM7 3 2 1  
RTHERM1  
RTHERM2  
RTHERM3  
RTHERM4  
RTHERM5  
RTHERM6  
RTHERM7  
RTHERM8  
CTHERM1  
CTHERM2  
CTHERM3  
CTHERM4  
CTHERM5  
CTHERM6  
CTHERM7  
CTHERM8  
8
7
CTHERM8 2 TL 3  
RTHERM1 TH 8 1e-1  
RTHERM2 8 7 5e-1  
RTHERM3 7 6 1  
RTHERM4 6 5 5  
RTHERM5 5 4 8  
RTHERM6 4 3 12  
RTHERM7 3 2 18  
RTHERM8 2 TL 25  
6
5
SABER Thermal Model  
Copper Area = 1.0 in2  
template thermal_model th tl  
thermal_c th, tl  
{
ctherm.ctherm1 th 8 =2.0e-3  
ctherm.ctherm2 8 7 =5.0e-3  
ctherm.ctherm3 7 6 =1.0e-2  
ctherm.ctherm4 6 5 =4.0e-2  
ctherm.ctherm5 5 4 =9.0e-2  
ctherm.ctherm6 4 3 =2e-1  
ctherm.ctherm7 3 2 1  
ctherm.ctherm8 2 tl 3  
4
3
2
rtherm.rtherm1 th 8 =1e-1  
rtherm.rtherm2 8 7 =5e-1  
rtherm.rtherm3 7 6 =1  
rtherm.rtherm4 6 5 =5  
rtherm.rtherm5 5 4 =8  
rtherm.rtherm6 4 3 =12  
rtherm.rtherm7 3 2 =18  
rtherm.rtherm8 2 tl =25  
}
tl  
CASE  
TABLE 1. THERMAL MODELS  
COMPONANT  
CTHERM6  
CTHERM7  
CTHERM8  
RTHERM6  
RTHERM7  
RTHERM8  
0.04 in2  
1.2e-1  
0.5  
0.28 in2  
1.5e-1  
1.0  
0.52 in2  
2.0e-1  
1.0  
0.76 in2  
2.0e-1  
1.0  
1.0 in2  
2.0e-1  
1.0  
3.0  
12  
1.3  
2.8  
3.0  
3.0  
26  
20  
15  
13  
39  
24  
21  
19  
18  
55  
38.7  
31.3  
29.7  
25  
11  
www.fairchildsemi.com  
FDS8870 Rev. A3  
TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not  
intended to be an exhaustive list of all such trademarks.  
ACEx™  
FACT Quiet Series™ ImpliedDisconnect™ POP™  
Stealth™  
®
ActiveArray™  
Bottomless™  
CoolFET™  
CROSSVOLT™ FRFET™  
DOME™  
FAST  
FASTr™  
FPS™  
IntelliMAX™  
ISOPLANAR™  
LittleFET™  
Power247™  
PowerEdge™  
PowerSaver™  
SuperFET™  
SuperSOT™-3  
SuperSOT™-6  
SuperSOT™-8  
SyncFET™  
®
MICROCOUPLER™ PowerTrench  
®
GlobalOptoisolator™ MicroFET™  
QFET  
®
EcoSPARK™  
GTO™  
MicroPak™  
MICROWIRE™  
MSX™  
MSXPro™  
OCX™  
QS™  
TinyLogic  
2
E CMOS™  
HiSeC™  
QT Optoelectronics™ TINYOPTO™  
2
EnSigna™  
FACT™  
I C™  
Quiet Series™  
RapidConfigure™  
RapidConnect™  
µSerDes™  
SILENT SWITCHER  
SMART START™  
SPM™  
TruTranslation™  
UHC™  
i-Lo™  
®
UltraFET  
Across the board. Around the world.™ OCXPro™  
The Power Franchise  
Programmable Active Droop™  
UniFET™  
VCX™  
®
®
®
OPTOLOGIC  
OPTOPLANAR™  
PACMAN™  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY  
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY  
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;  
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR  
CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the body,  
or (b) support or sustain life, or (c) whose failure to perform  
when properly used in accordance with instructions for use  
provided in the labeling, can be reasonably expected to  
result in significant injury to the user.  
2. A critical component is any component of a life support  
device or system whose failure to perform can be  
reasonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or In  
Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  
12  
www.fairchildsemi.com  
FDS8870 Rev. A2  

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