FDMF6705B [FAIRCHILD]
Extra-Small, High-Performance, High- Frequency DrMOS Module; 超小型，高性能，高频率的DrMOS模块
| 型号： | FDMF6705B |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Extra-Small, High-Performance, High- Frequency DrMOS Module |
| 文件： | 总19页 (文件大小：1510K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2012
FDMF6705B - Extra-Small, High-Performance, High-
Frequency DrMOS Module
Benefits
Description
The XS™ DrMOS family is Fairchild’s next-generation,
fully optimized, ultra-compact, integrated MOSFET plus
driver power stage solution for high-current, high-
frequency, synchronous buck DC-DC applications. The
FDMF6705B integrates a driver IC, two power MOSFETs,
.
Ultra-Compact 6x6mm PQFN, 72% Space-Saving
Compared to Conventional Discrete Solutions
.
.
.
Fully Optimized System Efficiency
Clean Switching Waveforms with Minimal Ringing
High-Current Handling
and
a bootstrap Schottky diode into a thermally
enhanced, ultra-compact 6x6mm PQFN package.
With an integrated approach, the complete switching
power stage is optimized with regards to driver and
MOSFET dynamic performance, system inductance,
and power MOSFET RDS(ON). XS™ DrMOS uses
Fairchild's high-performance PowerTrench® MOSFET
technology, which dramatically reduces switch ringing,
eliminating the need for a snubber circuit in most buck
converter applications.
Features
.
.
.
.
.
.
.
Over 93% Peak-Efficiency
High-Current Handling of 40A at 12VIN
High-Current Handling of 38A at 19VIN
High-Performance PQFN Copper-Clip Package
3-State 3.3V PWM Input Driver
A
new driver IC with reduced dead times and
Skip-Mode SMOD# (Low-Side Gate Turn-Off) Input
propagation delays further enhances the performance of
this part. A thermal warning function warns of a potential
over-temperature situation. The FDMF6705B also
incorporates features, such as Skip Mode (SMOD), for
improved light-load efficiency, along with a three-state
3.3V PWM input for compatibility with a wide range of
PWM controllers.
Thermal Warning Flag for Over-Temperature
Condition
.
.
Driver Output Disable Function (DISB# Pin)
Internal Pull-Up and Pull-Down for SMOD# and
DISB# Inputs, Respectively
.
.
Fairchild PowerTrench® Technology MOSFETs for
Clean Voltage Waveforms and Reduced Ringing
Applications
Fairchild SyncFET™ (Integrated Schottky Diode)
Technology in the Low-Side MOSFET
.
.
.
High-Performance Gaming Motherboards
Notebook Computers, V-Core and Non-V-Core
.
.
Integrated Bootstrap Schottky Diode
Compact Blade Servers, V-Core and Non-V-Core
DC-DC Converters
Adaptive Gate Drive Timing for Shoot-Through
Protection
.
Desktop Computers, V-Core and Non-V-Core
DC-DC Converters
.
.
.
.
.
Under-Voltage Lockout (UVLO)
Optimized for Switching Frequencies up to 1MHz
Low-Profile SMD Package
.
.
Workstations
High-Current DC-DC Point-of-Load (POL)
Converters
Fairchild Green Packaging and RoHS Compliance
Based on the Intel® 4.0 DrMOS Standard
.
Small Form-Factor Voltage Regulator Modules
Ordering Information
Part Number Current Rating
Package
Top Mark
FDMF6705B
40A
40-Lead, Clipbond PQFN DrMOS, 6.0x6.0mm Package
FDMF6705B
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
Typical Application Circuit
VIN
3V ~ 24V
V5V
CVIN
CVDRV
VDRV
VCIN
VIN
RBOOT
DISB#
DISB#
BOOT
CBOOT
PWM
PWM Input
FDMF6705B
PHASE
VSWH
OFF
SMOD#
ON
VOUT
LOUT
Open-Drain
THWN#
Output
COUT
CGND
PGND
Figure 1. Typical Application Circuit
DrMOS Block Diagram
VDRV
BOOT
VIN
VCIN
UVLO
Q1
HS Power
MOSFET
DBoot
DISB#
GH
GH
Logic
Level Shift
10µA
VCIN
30kΩ
PHASE
RUP_PWM
Dead Time
Control
Input
3-State
Logic
VSWH
PWM
VDRV
RDN_PWM
GL
GL
Logic
THWN#
30kΩ
VCIN
Q2
LS Power
MOSFET
Temp.
Sense
10µA
CGND
SMOD#
PGND
Figure 2. DrMOS Block Diagram
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
2
Pin Configuration
Figure 3. Bottom View
Figure 4. Top View
Pin Definitions
Pin #
Name
Description
When SMOD#=HIGH, the low-side driver is the inverse of PWM input. When SMOD#=LOW,
1
SMOD# the low-side driver is disabled. This pin has a 10µA internal pull-up current source. Do not add a
noise filter capacitor.
2
3
VCIN IC bias supply. Minimum 1µF ceramic capacitor is recommended from this pin to CGND.
Power for gate driver. Minimum 1µF ceramic capacitor is recommended, connected as close as
VDRV
possible from this pin to CGND.
Bootstrap supply input. Provides voltage supply to high-side MOSFET driver. Connect a
bootstrap capacitor from this pin to PHASE.
4
BOOT
5, 37, 41 CGND IC ground. Ground return for driver IC.
6
7
GH
For manufacturing test only. This pin must float; must not be connected to any pin.
PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.
No connect. The pin is not electrically connected internally, but can be connected to VIN for
convenience.
8
NC
9 - 14, 42
VIN
Power input. Output stage supply voltage.
15, 29 -
35, 43
Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point
for the adaptive shoot-through protection.
VSWH
16 – 28
36
PGND Power ground. Output stage ground. Source pin of low-side MOSFET.
GL
For manufacturing test only. This pin must float; must not be connected to any pin.
Thermal warning flag, open collector output. When temperature exceeds the trip limit, the
output is pulled LOW. THWN# does not disable the module.
38
THWN#
Output disable. When LOW, this pin disables power MOSFET switching (GH and GL are held
39
40
DISB# LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter
capacitor.
PWM PWM signal input. This pin accepts a three-state logic-level PWM signal from the controller.
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VCIN
VDRV
Supply Voltage
Drive Voltage
Referenced to CGND
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-8.0
6.0
6.0
V
V
Referenced to CGND
VDISB#
VPWM
Output Disable
PWM Signal Input
Referenced to CGND
6.0
V
Referenced to CGND
6.0
V
VSMOD# Skip Mode Input
Referenced to CGND
6.0
V
VGL
Low Gate Manufacturing Test Pin
Referenced to CGND
6.0
V
VTHWN# Thermal Warning Flag
Referenced to CGND
6.0
V
VIN
Power Input
Referenced to PGND, CGND
Referenced to VSWH, PHASE
Referenced to CGND
30.0
6.0
V
V
VBOOT
Bootstrap Supply
30.0
6.0
V
Referenced to VSWH, PHASE
Referenced to CGND
V
VGH
VPHS
VSWH
High Gate Manufacturing Test Pin
PHASE
30.0
30.0
30.0
33.0
22.0
25.0
7.0
V
Referenced to CGND
V
Referenced to PGND, CGND (DC Only)
Referenced to PGND, <20ns
Referenced to VDRV
V
Switch Node Input
V
V
VBOOT
ITHWN#
IO(AV)
Bootstrap Supply
THWN# Sink Current
Output Current(1)
Referenced to VDRV, <20ns
V
-0.1
-40
mA
fSW=300kHz, VIN=19V, VO=1.0V
fSW=1MHz, VIN=19V, VO=1.0V
38
A
35
θJPCB
TA
Junction-to-PCB Thermal Resistance
Ambient Temperature Range
Maximum Junction Temperature
Storage Temperature Range
3.5
°C/W
°C
+125
+150
+150
TJ
°C
TSTG
-55
°C
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
2000
1000
ESD
Electrostatic Discharge Protection
V
Note:
1. IO(AV) is rated using Fairchild’s DrMOS evaluation board, TA = 25°C, natural convection cooling. This rating is limited
by the peak DrMOS temperature, TJ = 150°C, and varies depending on operating conditions and PCB layout. This
rating can be changed with different application settings.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
4.5
Typ.
5.0
Max.
5.5
Unit
V
VCIN
VDRV
VIN
Control Circuit Supply Voltage
Gate Drive Circuit Supply Voltage
Output Stage Supply Voltage
4.5
5.0
5.5
24.0(2)
V
3.0
12.0
V
Note:
2. Operating at high VIN can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes
during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must
remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application
Information” and “PCB Layout Guidelines” sections of this datasheet for additional information.
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
4
Electrical Characteristics
Typical values are VIN = 12V, VCIN = 5V, VDRV = 5V, and TA = +25°C unless otherwise noted.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Basic Operation
IQ
Quiescent Current
UVLO Threshold
IQ=IVCIN+IVDRV, PWM=LOW or HIGH or Float
VCIN Rising
2
mA
V
UVLO
2.9
3.1
0.4
3.3
UVLO_Hyst UVLO Hysteresis
PWM Input (VCIN = VDRV = 5V ±10%)
RUP_PWM Pull-Up Impedance
RDN_PWM Pull-Down Impedance
V
26
12
kΩ
kΩ
V
VIH_PWM
VTRI_HI
VTRI_LO
VIL_PWM
PWM High Level Voltage
3-State Upper Threshold
3-State Lower Threshold
PWM Low Level Voltage
1.88 2.25 2.61
1.84 2.20 2.56
0.70 0.95 1.19
0.62 0.85 1.13
V
V
V
tD_HOLD-OFF 3-State Shut-off Time
VHiZ_PWM 3-State Open Voltage
PWM Input (VCIN = VDRV = 5V ±5%)
RUP_PWM Pull-Up Impedance
RDN_PWM Pull-Down Impedance
160
200
ns
V
1.40 1.60 1.90
26
kΩ
kΩ
V
12
VIH_PWM
VTRI_HI
VTRI_LO
VIL_PWM
PWM High Level Voltage
3-State Upper Threshold
3-State Lower Threshold
PWM Low Level Voltage
2.00 2.25 2.50
1.94 2.20 2.46
0.75 0.95 1.15
0.66 0.85 1.09
V
V
V
tD_HOLD-OFF 3-State Shut-off Time
VHiZ_PWM 3-State Open Voltage
DISB# Input
160
200
ns
V
1.45 1.60 1.80
VIH_DISB
VIL_DISB
IPLD
High-Level Input Voltage
Low-Level Input Voltage
Pull-Down Current
2
V
V
0.8
10
µA
PWM=GND, Delay Between DISB# from
HIGH to LOW to GL from HIGH to LOW
tPD_DISBL Propagation Delay
tPD_DISBH Propagation Delay
25
25
ns
ns
PWM=GND, Delay Between DISB# from
LOW to HIGH to GL from LOW to HIGH
SMOD# Input
VIH_SMOD High-Level Input Voltage
VIL_SMOD Low-Level Input Voltage
2
V
V
0.8
10
IPLU
Pull-Up Current
µA
PWM=GND, Delay Between SMOD# from
HIGH to LOW to GL from HIGH to LOW
tPD_SLGLL Propagation Delay
tPD_SHGLH Propagation Delay
10
10
ns
ns
PWM=GND, Delay Between SMOD# from
LOW to HIGH to GL from LOW to HIGH
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
5
Electrical Characteristics
Typical values are VIN = 12V, VCIN = 5V, VDRV = 5V, and TA = +25°C unless otherwise noted.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Thermal Warning Flag
TACT
TRST
Activation Temperature
150
135
30
°C
°C
Ω
Reset Temperature
RTHWN
Pull-Down Resistance
IPLD=5mA
250ns Timeout Circuit
tD_TIMEOUT Timeout Delay
High-Side Driver
SW=0V, Delay Between GH from HIGH to
LOW and GL from LOW to HIGH
250
ns
RSOURCE_GH Output Impedance, Sourcing Source Current=100mA
RSINK_GH Output Impedance, Sinking Sink Current=100mA
1
0.8
6
Ω
Ω
tR_GH
tF_GH
Rise Time
Fall Time
GH=10% to 90%, CLOAD=1.1nF
GH=90% to 10%, CLOAD=1.1nF
ns
ns
5
GL going LOW to GH going HIGH,
1V GL to 10% GH
tD_DEADON LS to HS Deadband Time
10
16
30
30
ns
ns
ns
ns
PWM LOW Propagation
PWM going LOW to GH going LOW,
tPD_PLGHL
Delay
30
V
IL_PWM to 90% GH
PWM going HIGH to GH going HIGH,
VIH_PWM to 10% GH (SMOD=LOW)
PWM HIGH Propagation
tPD_PHGHH
Delay (SMOD Held LOW)
Exiting 3-State Propagation PWM (from 3-State) going HIGH to GH
Delay going HIGH, VIH_PWM to 10% GH
tPD_TSGHH
Low-Side Driver
RSOURCE_GL Output Impedance, Sourcing Source Current=100mA
1
0.5
10
8
Ω
Ω
RSINK_GL Output Impedance, Sinking
Sink Current=100mA
tR_GL
tF_GL
Rise Time
Fall Time
GL=10% to 90%, CLOAD=2.7nF
GL=90% to 10%, CLOAD=2.7nF
ns
ns
SW going LOW to GL going HIGH,
2.2V SW to 10% GL
tD_DEADOFF HS to LS Deadband Time
12
9
ns
ns
ns
PWM-HIGH Propagation
PWM going HIGH to GL going LOW,
tPD_PHGLL
Delay
25
VIH_PWM to 90% GL
Exiting 3-State Propagation PWM (from 3-State) going LOW to GL
tPD_TSGLH
20
Delay
going HIGH, VIL_PWM to 10% GL
Boot Diode
VF
VR
Forward-Voltage Drop
Breakdown Voltage
IF=10mA
IR=1mA
0.35
V
V
22
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
6
V IH_PWM
VIL_PWM
PWM
GL
90%
1.0V
10%
90%
GH
to
VSWH
1.2V
10%
tD_TIMEOUT
(250ns Timeout)
2.2V
VSWH
tPD PLGHL
tPD PHGLL
tD_DEADOFF
tD_DEADON
Figure 5. PWM Timing Diagram
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
7
Typical Performance Characteristics
Test Conditions: VIN=12V, VOUT=1.0V, VCIN=5V, VDRV=5V, LOUT=320nH, TA=25°C, and natural convection cooling,
unless otherwise specified.
11
10
9
45
40
35
30
25
20
15
10
5
VIN = 12V, VOUT = 1V
300kHz
500kHZ
800kHz
1MHz
fSW = 300kHz
8
7
6
fSW = 1MHz
5
4
3
2
VIN = 12V, VOUT = 1.0V
JPCB = 3.5°C/W
1
Θ
0
0
0
5
10
15
20
25
30
35
40
0
25
50
75
100
125
150
PCB Temperature (°C)
Output Current, IOUT (A)
Figure 6. Safe Operating Area
Figure 7. Module Power Loss vs. Output Current
12
11
10
9
9
VIN = 19V, VOUT = 1V
300kHz
500kHz
800kHz
1MHz
Vin = 19V, Iout = 30A
8
Vin = 12V, Iout = 30A
7
Vin = 19V, Iout = 20A
8
Vin = 12V, Iout = 20A
6
5
4
3
2
1
7
6
5
4
3
2
1
0
200
300
400
500
600
700
800
900
1000
0
5
10
15
20
25
30
35
40
Module Switching Frequency, fSW (kHz)
Output Current, IOUT (A)
Figure 8. Module Power Loss vs. Output Current
Figure 9. Module Power Loss vs. Switching
Frequency
1.20
1.15
IOUT = 30A, fSW = 300kHz
VIN = 12V, IOUT = 30A, fSW = 300kHz
1.15
1.10
1.05
1.00
0.95
1.10
1.05
1.00
0.95
0.90
4.50
4.75
5.00
5.25
5.50
4
6
8
10
12
14
16
18
20
Driver Supply Voltage, VDRV and VCIN (V)
Module Input Voltage, VIN (V)
Figure 10. Normalized Power Loss vs. Input Voltage
Figure 11. Normalized Power Loss vs. Driver
Supply Voltage
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
8
Typical Performance Characteristics (Continued)
Test Conditions: VIN=12V, VOUT=1.0V, VCIN=5V, VDRV=5V, LOUT=320nH, TA=25°C, and natural convection cooling,
unless otherwise specified.
1.9
1.7
1.5
1.3
1.1
0.9
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
VIN = 12V, IOUT = 30A, fSW = 300kHz
VIN = 12V, IOUT = 30A, fSW = 300kHz
225
275
325
375
425
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Output Inductance, LOUT (nH)
Output Voltage, VOUT (V)
Figure 12. Normalized Power Loss vs.
Output Voltage
Figure 13. Module Power Loss vs.
Output Inductance
34
30
26
22
18
14
10
6
12
11
10
9
VIN = 12V, IOUT = 0A, fSW = 300kHz
VIN = 12V, IOUT = 0A, fSW = 300kHz
4.5
4.75
5
5.25
5.5
200
400
600
800
1000
Driver Supply Voltage, VDRV & VCIN (V)
Module Switching Frequency, fSW (kHz)
Figure 14. Driver Supply Current vs. Frequency
Figure 15. Driver Supply Current vs. Driver
Supply Voltage
3.0
1.10
TA = 25°C
300kHz
1MHz
2.5
1.08
VIH_PWM
2.0
1.06
VTRI_HI
VHiZ_PWM
1.5
1.0
0.5
0.0
1.04
1.02
1.00
0.98
VTRI_LO
VIL_PWM
0
5
10
15
20
25
30
35
40
4.50
4.75
5.00
5.25
5.50
Module Output Current, IOUT (A)
Driver Supply Voltage, VCIN (V)
Figure 16. Normalized Driver Supply Current vs.
Output Current
Figure 17. PWM Thresholds vs. Driver
Supply Voltage
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
9
Typical Performance Characteristics (Continued)
Test Conditions: VIN=12V, VOUT=1.0V, VCIN=5V, VDRV=5V, LOUT=320nH, TA=25°C, and natural convection cooling,
unless otherwise specified.
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.2
2.0
1.8
1.6
1.4
1.2
VCIN = 5V
TA = 25°C
VIH_PWM
VTRI_HI
VIH_SMOD
VTRI_LO
VIL_SMOD
VIL_PWM
-50
-25
0
25
50
75
100
125
150
4.50
4.75
5.00
5.25
5.50
Driver IC Junction Temperature, TJ (oC)
Driver Supply Voltage, VCIN (V)
Figure 18. PWM Thresholds vs. Temperature
Figure 19. SMOD# Thresholds vs. Driver Supply
Voltage
2.0
-9.0
VCIN = 5V
VCIN = 5V
1.9
-9.5
-10.0
-10.5
-11.0
-11.5
-12.0
1.8
VIH_SMOD
1.7
1.6
VIL_SMOD
1.5
1.4
1.3
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Driver IC Junction Temperature (oC)
Driver IC Junction Temperature, TJ (oC)
Figure 20. SMOD# Thresholds vs. Temperature
Figure 21. SMOD# Pull-Up Current vs. Temperature
2.1
2.00
TA = 25oC
2.0
VCIN = 5V
1.90
VIH_DISB
1.9
1.80
VIH_DISB
1.8
1.7
1.70
VIL_DISB
1.6
1.60
VIL_DISB
1.5
1.4
1.3
1.50
1.40
4.50
4.75
5.00
5.25
5.50
-50
-25
0
25
50
75
100
125
150
Driver Supply Voltage, VCIN (V)
Driver IC Junction Temperature, TJ (°C)
Figure 22. DISB# Thresholds vs. Driver
Supply Voltage
Figure 23. DISB# Thresholds vs. Temperature
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
10
Typical Performance Characteristics (Continued)
Test Conditions: VIN=12V, VOUT=1.0V, VCIN=5V, VDRV=5V, LOUT=320nH, TA=25°C, and natural convection cooling,
unless otherwise specified.
11.5
VCIN = 5V
11.0
IPLD
10.5
10.0
9.5
-50
-25
0
25
50
75
100
125
150
Driver IC Junction Temperature, TJ (°C)
Figure 24. DISB# Pull-Down Current vs. Temperature
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
11
Functional Description
The FDMF6705B is a driver-plus-FET module optimized
for the synchronous buck converter topology. A single
PWM input signal is all that is required to properly drive
the high-side and the low-side MOSFETs. Each part is
capable of driving speeds up to 1MHz.
3-State PWM Input
The FDMF6705B incorporates a three-state PWM input
gate drive design. The three-state gate drive has both
logic HIGH level and LOW level, along with a three-state
shutdown window. When the PWM input signal enters
and remains within the three-state window for a defined
hold-off time (tD_HOLD-OFF), both GL and GH are pulled
LOW. This feature enables the gate drive to shut down
both high-and low-side MOSFETs to support features
such as phase shedding, which is a common feature on
multiphase voltage regulators.
VCIN and Disable
The VCIN pin is monitored by an Under-Voltage Lockout
(UVLO) circuit. When VCIN rises above ~3.1V, the driver
is enabled. When VCIN falls below ~2.7V, the driver is
disabled (GH, GL=0). The driver can also be disabled by
pulling the DISB# pin LOW (DISB# < VIL_DISB), which
holds both GL and GH LOW regardless of the PWM
input state. The driver can be enabled by raising the
DISB# pin voltage HIGH (DISB# > VIH_DISB).
Operation when Exiting Three-State
Condition
When exiting
a
valid three-state condition, the
FDMF6705B design follows the PWM input command. If
the PWM input goes from three-state to LOW, the low-
side MOSFET is turned on. If the PWM input goes from
three-state to HIGH, the high-side MOSFET is turned
on. This is illustrated in Figure 26. The FDMF6705B
design allows for short propagation delays when exiting
the three-state window (see Electrical Characteristics).
Table 1. UVLO and Disable Logic
UVLO DISB#
Driver State
0
X
0
Disabled (GH, GL=0)
Disabled (GH, GL=0)
Enabled (See Table 2)
Disabled (GH, GL=0)
1
1
1
Low-Side Driver
1
Open
The low-side driver (GL) is designed to drive a ground-
referenced low RDS(ON) N-channel MOSFET. The bias
for GL is internally connected between VDRV and
CGND. When the driver is enabled, the driver's output is
180° out of phase with the PWM input. When the driver
is disabled (DISB#=0V), GL is held LOW.
Note:
3. DISB# internal pull-down current source is 10µA.
Thermal Warning Flag
The FDMF6705B provides a thermal warning flag
(THWN) to warn of over-temperature conditions. The
thermal warning flag uses an open-drain output that
pulls to CGND when the activation temperature (150°C)
is reached. The THWN output returns to a high-
impedance state once the temperature falls to the reset
temperature (135°C). The THWN output requires a pull-
up resistor, which can be connected to VCIN. THWN
does NOT disable the DrMOS module.
High-Side Driver
The high-side driver is designed to drive a floating N-
channel MOSFET. The bias voltage for the high-side
driver is developed by a bootstrap supply circuit,
consisting of the internal Schottky diode and external
bootstrap capacitor (CBOOT). During startup, VSWH is
held at PGND, allowing CBOOT to charge to VDRV
through the internal diode. When the PWM input goes
HIGH, GH begins to charge the gate of the high-side
MOSFET (Q1). During this transition, the charge is
removed from CBOOT and delivered to the gate of Q1. As
Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to
VIN + VBOOT, which provides sufficient VGS enhancement
for Q1. To complete the switching cycle, Q1 is turned off
by pulling GH to VSWH. CBOOT is then recharged to
VDRV when VSWH falls to PGND. GH output is in-
phase with the PWM input. The high-side gate is held
LOW when the driver is disabled or the PWM signal is
held within the three-state window for longer than the
150°C
Activation
Temperature
135°C
Reset
HIGH
THWN
Logic
State
Normal
Operation
Thermal
Warning
LOW
TJ_driverIC
Figure 25. THWN Operation
three-state hold-off time, tD_HOLD-OFF
.
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
12
Adaptive Gate Drive Circuit
The driver IC advanced design ensures minimum
MOSFET dead time, while eliminating potential shoot-
through (cross-conduction) currents. It senses the state
of the MOSFETs and adjusts the gate drive adaptively
to ensure they do not conduct simultaneously. Figure 26
provides the relevant timing waveforms. To prevent
overlap during the LOW-to-HIGH switching transition
(Q2 off to Q1 on), the adaptive circuitry monitors the
voltage at the GL pin. When the PWM signal goes
HIGH, Q2 turns off after a propagation delay (tPD_PHGLL).
Once the GL pin is discharged below ~1V, Q1 turns on
To preclude overlap during the HIGH-to-LOW transition
(Q1 off to Q2 on), the adaptive circuitry monitors the
voltage at the VSWH pin. When the PWM signal goes
LOW, Q1 turns off after a propagation delay (tPD_PLGHL).
Once the VSWH pin falls below ~2.2V, Q2 turns on after
adaptive delay, tD_DEADOFF
. Additionally, VGS(Q1) is
monitored. When VGS(Q1) is discharged below ~1.2V, a
secondary adaptive delay is initiated, which results in
Q2 being driven on after tD_TIMEOUT, regardless of SW
state. This function is implemented to ensure CBOOT is
recharged each switching cycle in the event that the SW
voltage does not fall below the 2.2V adaptive threshold.
after adaptive delay, tD_DEADON
.
Secondary delay tD_TIMEOUT is longer than tD_DEADOFF
.
VIH_PWM
VIH_PWM
VIH_PWM
VIH
VTRI_HI
PWM
VTRI_HI
VTRI_LO
VIL_PWM
IL_PWM
V
tR_GH
tF_GH
PWM
less than
tD_HOLD
90%
10%
tD_HOLD -
OFF
OFF
-
GH
to
VSWH
VIN
DCM
CCM
DCM
VOUT
2.2V
VSWH
GL
90%
90%
10%
1.0V
10%
tPD_PLGHL
tPD_PHGLL
tD_DEADON
less than
tD_HOLD
tF_GL
tR_GL
tPD_TSGHH
tD_HOLD
tPD_TSGHH tD_HOLD -OFF
-OFF tPD_TSGLH
OFF
-
tD_DEADOFF
Exit
3 S t a t e
Enter
3-State
Enter
Enter
3 -State
Exit
3-State
Exit
3-State
3 -State
Notes:
PD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal.
tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH)
t
Example (tPD_PHGLL – PWM going HIGH to LS VGS (GL) going LOW)
PWM
PD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS
tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS
PD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW)
Exiting 3-state
t
tPD_TSGHH = PWM 3-state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS
tPD_TSGLH = PWM 3-state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS
t
SMOD#
Dead Times
tPD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS
tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS
tD_DEADON = LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS
tD_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS
Figure 26. PWM and 3-StateTiming Diagram
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
13
Skip Mode (SMOD)
The SMOD function allows higher converter efficiency
under light-load conditions. During SMOD, the low-side
FET gate signal is disabled (held LOW), preventing
discharging of the output capacitors as the filter inductor
current attempts reverse current flow – also known as
Diode Emulation Mode. When the SMOD# pin is pulled
HIGH, the synchronous buck converter works in
Synchronous Mode, gating on the low-side FET. When
the SMOD# pin is pulled LOW, the low-side FET is
gated off. The SMOD# pin is connected to the PWM
controller, which enables or disables SMOD
automatically when the controller detects light-load
condition from output current sensing. Normally this pin
is active LOW. See Figure 27 for timing delays.
Table 2. SMOD Logic
DISB#
PWM
SMOD#
GH
0
GL
0
0
1
1
1
1
1
X
X
X
0
0
1
1
3-State
0
0
0
1
0
1
0
0
1
0
0
1
1
0
Note:
4. The SMOD feature is intended to have low
propagation delay between the SMOD signal and
the low-side FET VGS response time to control
diode emulation on a cycle-by-cycle basis.
SMOD#
VIH_SMOD
VIL_SMOD
VIH_PWM
VIH_PWM
VIL_PWM
PWM
90%
GH
to
VSWH
10%
10%
DCM
VOUT
CCM
CCM
2.2V
VSWH
GL
90%
1.0V
10%
10%
tPD_PLGHL
tPD_PHGLL
tPD_PHGHH
tPD_SHGLH
tPD_SLGLL
tD_DEADOFF
tD_DEADON
Delay from SMOD# going
LOW to LS VGS LOW
Delay from SMOD# going
HIGH to LS V HIGH
GS
HS turn -on with SMOD# LOW
Figure 27. SMOD Timing Diagram
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
14
Application Information
Supply Capacitor Selection
For the supply inputs (VDRV and VCIN), a local ceramic
bypass capacitor is required to reduce noise and to
supply peak transient currents during gate drive
switching action. It is recommended to use a minimum
capacitor value of 1µF X7R or X5R. Keep this capacitor
close to the VCIN and VDRV pins and connect it to the
GND plane with vias.
VCIN Filter
The VDRV pin provides power to the gate drive of the
high-side and low-side power MOSFETs. In most cases,
VDRV can be connected directly to VCIN, which
supplies power to the logic circuitry of the gate driver.
For additional noise immunity, an RC filter can be
inserted between VDRV and VCIN. Recommended
values of 10Ω (RVCIN) placed between VDRV and VCIN
and 1µF (CVCIN) from VCIN to CGND, Figure 28.
Bootstrap Circuit
Power Loss and Efficiency
The bootstrap circuit uses a charge storage capacitor
(CBOOT), as shown in Figure 28. A bootstrap capacitance
of 100nF X7R or X5R capacitor is typically adequate. A
series bootstrap resistor may be needed for specific
applications to improve switching noise immunity. The
boot resistor (RBOOT) may be required when operating
near the maximum rated VIN and is effective at
controlling the high-side MOSFET turn-on slew rate and
VSHW overshoot. Typical RBOOT values from 0.5 to 3.0Ω
are effective in reducing VSWH overshoot.
Measurement and Calculation
Refer to Figure 29 for power-loss testing method. Power
loss calculations are:
(1)
PIN=(VIN x IIN) + (V5V x I5V) (W)
SW=VSW x IOUT (W)
POUT=VOUT x IOUT (W)
LOSS_MODULE=PIN - PSW (W)
P
(2)
(3)
(4)
(5)
(6)
(7)
P
PLOSS_BOARD=PIN - POUT (W)
EFFMODULE=100 x PSW/PIN (%)
EFFBOARD=100 x POUT/PIN (%)
V5V
VIN
A
A
RV
CIN
I5V
IIN
CVIN
CVDRV
CV
CIN
VDRV
VCIN
VIN
DISB#
DISB#
RBOOT
PWM
Input
OFF
BOOT
PWM
FDMF6705B
CBOOT
VSWH
OUT
I
SMOD#
ON
A
LOUT
Open-
Drain
PHASE
THWN
VOUT
Output
V VSW
CGND
PGND
COUT
Figure 28. Block Diagram with VCIN Filter
V5V
A
A
V
IN
I5V
IIN
CVDRV
CVIN
VDRV
VCIN
VIN
DISB#
DISB#
RBOOT
BOOT
VSWH
PWM
Input
OFF
PWM
FDMF6705B
CBOOT
IOUT
SMOD
ON
A
LOUT
Open-
Drain
PHASE
THWN#
Output
V VSW
CGND
PGND
COUT
Figure 29. Power Loss Measurement
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
15
PCB Layout Guidelines
Figure 30 provides an example of a proper layout for
critical components. All of the high-current paths, such
as VIN, VSWH, VOUT, and GND copper, should be short
and wide for low inductance and resistance. This
technique achieves a more stable and evenly distributed
current flow, along with enhanced heat radiation and
system performance.
BOOT-to-VSWH loop size, including RBOOT and
BOOT, should be as small as possible. The boot
C
resistor may be required when operating near the
maximum rated VIN. The boot resistor is effective at
controlling the high-side MOSFET turn-on slew rate
and VSHW overshoot. RBOOT can improve noise
operating margin in synchronous buck designs that
have noise issues due to ground bounce or high
positive and negative VSWH ringing. However,
inserting a boot resistance lowers the DrMOS
efficiency. Efficiency versus noise trade-offs must be
considered. RBOOT values from 0.5 to 3.0Ω are
typically effective in reducing VSWH overshoot.
The following guidelines are recommendations for the
PCB designer:
1. Input ceramic bypass capacitors must be placed
close to the VIN and PGND pins. This helps reduce
the high-current power loop inductance and the input
current ripple induced by the power MOSFET
switching operation.
The VIN and PGND pins handle large current
transients with frequency components greater than
100MHz. If possible, these pins should be connected
directly to the VIN and board GND planes. The use
of thermal relief traces in series with these pins is
discouraged since this adds inductance to the
power path. This added inductance in series with
either the VIN or PGND pin degrades system noise
immunity by increasing positive and negative VSWH
ringing.
2. The VSWH copper trace serves two purposes. In
addition to being the high-frequency current path
from the DrMOS package to the output inductor, it
also serves as a heat sink for the low-side MOSFET
in the DrMOS package. The trace should be short
and wide enough to present a low-impedance path
for the high-frequency, high-current flow between the
DrMOS and inductor to minimize losses and
temperature rise. Note that the VSWH node is a
high-voltage and high-frequency switching node with
high noise potential. Care should be taken to
minimize coupling to adjacent traces. Since this
copper trace also acts as a heat sink for the lower
FET, balance using the largest area possible to
8. CGND pad and PGND pins should be connected to
the GND plane copper with multiple vias for stable
grounding. Poor grounding can create a noise
transient offset voltage level between CGND and
PGND. This could lead to faulty operation of the
gate driver and MOSFETs.
improve
DrMOS
cooling
while
maintaining
acceptable noise emission.
9. Ringing at the BOOT pin is most effectively
controlled by close placement of the boot capacitor.
Do not add an additional BOOT to the PGND
capacitor. This may lead to excess current flow
through the BOOT diode.
3. An output inductor should be located close to the
FDMF6705B to minimize the power loss due to the
VSWH copper trace. Care should also be taken so
the inductor dissipation does not heat the DrMOS.
10. The SMOD# and DISB# pins have weak internal
pull-up and pull-down current sources, respectively.
These pins should not have any noise filter
capacitors. Do not to float these pins unless
absolutely necessary.
4. PowerTrench® MOSFETs are used in the output
stage. The power MOSFETs are effective at
minimizing ringing due to fast switching. In most
cases, no VSWH snubber is required. If a snubber is
used, it should be placed close to the VSWH and
PGND pins. The resistor and capacitor need to be of
proper size for the power dissipation.
11. Use multiple vias on each copper area to
interconnect top, inner, and bottom layers to help
distribute current flow and heat conduction. Vias
should be relatively large and of reasonably low
inductance. Critical high-frequency components,
such as RBOOT, CBOOT, the RC snubber, and bypass
capacitors should be located as close to the
respective DrMOS module pins as possible on the
top layer of the PCB. If this is not feasible, they
should be connected from the backside through a
network of low-inductance vias.
5. VCIN, VDRV, and BOOT capacitors should be
placed as close as possible to the VCIN to CGND,
VDRV to CGND, and BOOT to PHASE pins to
ensure clean and stable power. Routing width and
length should be considered.
6. Include a trace from PHASE to VSWH to improve
noise margin. Keep the trace as short as possible.
7. The layout should include a place holder to insert a
small-value series boot resistor (RBOOT) between the
boot capacitor (CBOOT) and DrMOS BOOT pin. The
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
16
Top View
Bottom View
Figure 30. PCB Layout Example
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
17
Physical Dimensions
B
PIN#1
0.10 C
2X
INDICATOR
6.00
5.80
4.50
A
30
21
31
20
11
6.00
2.50
1.60
0.40
0.65
0.25
0.10 C
40
2X
1
0.50 TYP
10
TOP VIEW
0.60
0.35
SEE
DETAIL 'A'
0.15
2.10
2.10
LAND PATTERN
RECOMMENDATION
FRONT VIEW
4.40±0.10
(2.20)
0.10
0.05
C A B
C
0.30
0.40
(40X)
0.20
31
21
30
20
(0.70)
0.50
2.40±0.10
0.20
PIN #1 INDICATOR
0.50
1.50±0.10
40
(40X)
0.30
11
10
1
0.40
2.00±0.10
0.50
(0.20)
2.00±0.10
(0.20)
NOTES: UNLESS OTHERWISE SPECIFIED
BOTTOM VIEW
A) DOES NOT FULLY CONFORM TO JEDEC
REGISTRATION MO-220, DATED
MAY/2005.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
1.10
0.90
0.10 C
0.08 C
0.30
0.20
0.05
0.00
E) DRAWING FILE NAME: PQFN40AREV2
C
SEATING
PLANE
DETAIL 'A'
SCALE: 2:1
Figure 31. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0mm Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
18
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
www.fairchildsemi.com
19
相关型号：
©2020 ICPDF网 联系我们和版权申明