FAN7529_07 [FAIRCHILD]
Critical Conduction Mode PFC Controller; 临界导通模式PFC控制器
| 型号： | FAN7529_07 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Critical Conduction Mode PFC Controller |
| 文件： | 总20页 (文件大小：1733K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2007
FAN7529
Critical Conduction Mode PFC Controller
Features
Description
Low Total Harmonic Distortion (THD)
Precise Adjustable Output Over-Voltage Protection
Open-Feedback Protection and Disable Function
Zero Current Detector
The FAN7529 is an active power factor correction (PFC)
controller for boost PFC applications that operates in crit-
ical conduction mode (CRM). It uses the voltage mode
PWM that compares an internal ramp signal with the
error amplifier output to generate MOSFET turn-off sig-
nal. Because the voltage-mode CRM PFC controller does
not need rectified AC line voltage information, it saves the
power loss of the input voltage sensing network neces-
sary for the current-mode CRM PFC controller.
150µs Internal Start-up Timer
MOSFET Over-Current Protection
Under-Voltage Lockout with 3.5V Hysteresis
Low Start-up (40µA) and Operating Current (1.5mA)
Totem Pole Output with High State Clamp
+500/-800mA Peak Gate Drive Current
8-Pin DIP or 8-Pin SOP
FAN7529 provides many protection functions, such as
over-voltage protection, open-feedback protection, over-
current protection, and under-voltage lockout protection.
The FAN7529 can be disabled if the INV pin voltage is
lower than 0.45V and the operating current decreases to
65µA. Using a new variable on-time control method,
THD is lower than the conventional CRM boost PFC ICs.
Applications
Adapter
Ballast
LCD TV, CRT TV
SMPS
Related Application Notes
AN-6026 - Design of Power Factor Correction Circuit
Using FAN7529
Ordering Information
OperatingTemp.
Marking
Part Number
FAN7529N
Range
Pb-Free
Yes
Package
8-DIP
Packing Method
Code
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
Rail
Rail
FAN7529
FAN7529
FAN7529
FAN7529M
Yes
8-SOP
8-SOP
FAN7529MX
Yes
Tape & Reel
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
Typical Application Diagrams
L
D
VO
AC
IN
NAUX
VAUX
RZCD
ZCD
R2
CO
VCC
FAN7529
INV
MOT
CS
COMP
R1
GND
FAN7529 Rev. 00
Figure 1. Typical Boost PFC Application
Internal Block Diagram
2.5V
Ref
VCC
8
Vref1
VCC
UVLO
Internal
Bias
Drive
Output
7
OUT
8.5V
12V
Disable
Timer
5
ZCD
S
R
Q
6.7V
1.4V 1.5V
Zero Current
Detector
OVP
2.5V
2.675V
4
CS
Disable
40k
0.45V 0.35V
8pF
0.8V
Current Protection
Comparator
Ramp
Signal
Vref1
1V Offset
Error
Amplifier
Saw Tooth
Generator
MOT
3
Gm
2.9V
1
INV
1V~5V
Range
6
2
FAN7529 Rev. 00
GND
COMP
Figure 2. Functional Block Diagram of FAN7529
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
2
Pin Assignments
VCC
8
OUT
7
GND
6
ZCD
5
Y W W
F A N 7 5 2 9
1
2
3
4
INV
COMP
MOT
CS
FAN7529 Rev. 00
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
This pin is the inverting input of the error amplifier. The output voltage of the boost PFC
converter should be resistively divided to 2.5V.
1
INV
This pin is the output of the transconductance error amplifier. Components for output
voltage compensation should be connected between this pin and GND.
2
3
COMP
This pin is used to set the slope of the internal ramp. The voltage of this pin is main-
tained at 2.9V. If a resistor is connected between this pin and GND, current flows out of
the pin and the slope of the internal ramp is proportional to this current.
MOT
CS
This pin is the input of the over-current protection comparator. The MOSFET current is
sensed using a sensing resistor and the resulting voltage is applied to this pin. An
internal RC filter is included to filter switching noise.
4
This pin is the input of the zero current detection block. If the voltage of this pin goes
higher than 1.5V, then goes lower than 1.4V, the MOSFET is turned on.
5
6
ZCD
GND
This pin is used for the ground potential of all the pins. For proper operation, the signal
ground and the power ground should be separated.
This pin is the gate drive output. The peak sourcing and sinking current levels are
+500mA and -800mA respectively. For proper operation, the stray inductance in the
gate driving path must be minimized.
7
8
OUT
VCC
This pin is the IC supply pin. IC current and MOSFET drive current are supplied using
this pin.
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA = 25°C unless otherwise specified.
Symbol
VCC
Parameter
Value
VZ
Unit
V
Supply Voltage
IOH, IOL
Iclamp
Peak Drive Output Current
+500/-800
±10
mA
mA
mA
V
Driver Output Clamping Diodes VO>VCC or VO<-0.3V
Detector Clamping Diodes
Idet
±10
VIN
Error Amplifier, MOT, CS Input Voltages
Operating Junction Temperature
Operating Temperature Range
-0.3 to 6
150
TJ
°C
°C
°C
kV
V
TA
-40 to 125
-65 to 150
2.0
TSTG
Storage Temperature Range
VESD_HBM
VESD_MM
VESD_CDM
ESD Capability, Human Body Model
ESD Capability, Machine Model
ESD Capability, Charged Device Model
300
500
V
(1)
Thermal Impedance
Symbol
Parameter
Value
110
Unit
°C/W
°C/W
8-DIP
θJΑ
Thermal Resistance, Junction-to-Ambient
8-SOP
150
Note:
1. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10.
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7529 Rev. 1.0.2
4
Electrical Characteristics
VCC = 14V and TA = -40°C~125°C unless otherwise specified.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
UNDER-VOLTAGE LOCKOUT SECTION
Vth(start) Start Threshold Voltage
Vth(stop) Stop Threshold Voltage
HY(uvlo) UVLO Hysteresis
VCC increasing
11
7.5
3.0
20
12
8.5
3.5
22
13
9.5
4.0
24
V
V
V
V
VCC decreasing
VZ
Zener Voltage
ICC = 20mA
SUPPLY CURRENT SECTION
Ist
ICC
Start-up Supply Current
VCC = Vth(start) - 0.2V
Output no switching
50kHz, Cl=1nF
Vinv = 0V
40
1.5
2.5
65
70
3.0
4.0
95
µA
mA
mA
µA
Operating Supply Current
Idcc
Dynamic Operating Supply Current
Operating Current at Disable
ICC(dis)
20
ERROR AMPLIFIER SECTION
Vref1
ΔVref1
ΔVref2
Ib(ea)
Isource
Isink
Voltage Feedback Input Threshold1
TA = 25°C
2.465 2.500 2.535
V
mV
mV
µA
µA
µA
V
Line Regulation
VCC = 14V ~ 20V
0.1
20
10.0
(2)
Temperature Stability of Vref1
Input Bias Current
Vinv = 1V ~ 4V
-0.5
0.5
Output Source Current
Output Sink Current
Vinv = Vref1 - 0.1V
Vinv = Vref1 + 0.1V
Vinv = Vref1 - 0.1V
-12
12
Veao(H) Output Upper Clamp Voltage
5.4
0.9
90
6.0
1.0
115
6.6
1.1
Veao(Z)
gm
Zero Duty Cycle Output Voltage
Transconductance(2)
V
140
µmho
MAXIMUM ON-TIME SECTION
Vmot
Maximum On-Time Voltage
Rmot = 40.5kΩ
2.784 2.900 3.016
V
Ton(max) Maximum On-Time Programming
CURRENT SENSE SECTION
Rmot = 40.5kΩ, TA = 25°C
19
24
29
µs
Current Sense Input Threshold
Voltage Limit
VCS(limit)
0.7
0.8
-0.1
350
0.9
1.0
V
Ib(cs)
td(cs)
Note:
Input Bias Current
VCS = 0V ~ 1V
-1.0
µA
ns
dV/dt = 1V/100ns,
from 0V to 5V
Current Sense Delay to Output(2)
500
2. These parameters, although guaranteed by design, are not tested in production.
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7529 Rev. 1.0.2
5
Electrical Characteristics (Continued)
VCC = 14V and TA = -40°C~125°C unless otherwise specified.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
ZERO CURRENT DETECT SECTION
Vth(ZCD)
HY(ZCD)
Input Voltage Threshold(3)
Detect Hysteresis(3)
1.35
0.05
6.0
0
1.50
0.10
6.7
1.65
0.15
7.4
V
V
Vclamp(H) Input High Clamp Voltage
Vclamp(L) Input Low Clamp Voltage
Idet = 3mA
V
Idet = -3mA
VZCD = 1V ~ 5V
TA = 25°C
0.65
-0.1
1.00
1.0
V
Ib(ZCD)
Isource(zcd) Source Current Capability(3)
Isink(zcd)
Sink Current Capability(3)
Input Bias Current
-1.0
µA
mA
mA
-10
TA = 25°C
10
Maximum Delay from ZCD to Output dV/dt = -1V/100ns,
tdead
100
9.2
200
ns
Turn-on(3)
from 5V to 0V
OUTPUT SECTION
VOH
VOL
tr
Output Voltage High
IO = -100mA, TA = 25°C
IO = 200mA, TA = 25°C
Cl = 1nF
11.0
1.0
50
12.8
2.5
V
V
Output Voltage Low
Rising Time(3)
100
100
14.5
1
ns
ns
V
tf
Falling Time(3)
Cl = 1nF
50
VO(max)
Maximum Output Voltage
VCC = 20V, IO = 100μA
11.5
50
13.0
VO(UVLO) Output Voltage with UVLO Activated VCC = 5V, IO = 100μA
V
RESTART TIMER SECTION
td(rst)
Restart Timer Delay
150
300
µs
OVER-VOLTAGE PROTECTION SECTION
Vovp
OVP Threshold Voltage
OVP Hysteresis
TA = 25°C
TA = 25°C
2.620 2.675 2.730
0.120 0.175 0.230
V
V
HY(ovp)
ENABLE SECTION
Vth(en)
HY(en)
Enable Threshold Voltage
Enable Hysteresis
0.40
0.05
0.45
0.10
0.50
0.15
V
V
Note:
3. These parameters, although guaranteed by design, are not tested in production.
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7529 Rev. 1.0.2
6
Typical Characteristics
9.5
9.0
8.5
8.0
7.5
13.0
12.5
12.0
11.5
11.0
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
Figure 4. Start Threshold Voltage vs. Temp.
Figure 5. Stop Threshold Voltage vs. Temp.
23.0
4.00
3.75
3.50
3.25
3.00
22.5
22.0
21.5
21.0
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
Figure 6. UVLO Hysteresis vs. Temp.
Figure 7. Zener Voltage vs. Temp.
60
45
30
15
2.4
1.6
0.8
0.0
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
Figure 8. Start-up Supply Current vs. Temp.
Figure 9. Operating Supply Current vs. Temp.
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
7
Typical Characteristics (Continued)
4
3
2
1
0
90
72
54
36
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
Figure 10. Dynamic Operating Supply Current vs.
Temp.
Figure 11. Operating Current at Disable vs. Temp.
10.0
7.5
5.0
2.5
0.0
2.52
2.50
2.48
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
Figure 12. Vref1 vs. Temp.
Figure 13. ΔVref1 vs. Temp.
0.50
0.25
-9
-12
-15
-18
0.00
-0.25
-0.50
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
Figure 14. Input Bias Current vs. Temp.
Figure 15. Output Source Current vs. Temp.
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
8
Typical Characteristics (Continued)
18
15
12
9
6.6
6.3
6.0
5.7
5.4
6
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
Figure 16. Output Sink Current vs. Temp.
Figure 17. Output Upper Clamp Voltage vs. Temp.
1.10
1.05
1.00
0.95
0.90
3.00
2.95
2.90
2.85
2.80
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
Figure 18. Zero Duty Cycle Output Voltage vs. Temp.
Figure 19. Maximum On-Time Voltage vs. Temp.
0.90
0.85
0.80
0.75
0.70
27
24
21
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
Figure 20. Maximum On-Time vs. Temp.
Figure 21. Current Sense Input Threshold Voltage vs.
Temp.
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
9
Typical Characteristics (Continued)
1.0
0.5
7.2
6.8
6.4
6.0
0.0
-0.5
-1.0
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
Figure 22. Input Bias Current vs. Temp.
Figure 23. Input High Clamp Voltage vs. Temp.
1.00
1.0
0.5
0.75
0.50
0.25
0.00
0.0
-0.5
-1.0
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
Figure 24. Input Low Clamp Voltage vs. Temp.
Figure 25. Input Bias Current vs. Temp.
0.9
0.6
0.3
0.0
-0.3
14
13
12
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
Figure 26. Maximum Output Voltage vs. Temp.
Figure 27. Output Voltage with UVLO Activated vs.
Temp.
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
10
Typical Characteristics (Continued)
2.73
2.70
2.67
2.64
300
250
200
150
100
50
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
Figure 28. Restart Delay Time vs. Temp.
Figure 29. OVP Threshold Voltage vs. Temp.
0.500
0.21
0.475
0.450
0.425
0.400
0.18
0.15
0.12
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
Figure 30. OVP Hysteresis vs. Temp.
Figure 31. Enable Threshold Voltage vs. Temp.
0.150
0.125
0.100
0.075
0.050
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature [°C]
Figure 32. Enable Hysteresis vs. Temp.
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
11
Applications Information
below 1.4V. If the voltage goes below 1.4V, the zero cur-
rent detector turns on the MOSFET. The ZCD pin is pro-
tected internally by two clamps, 6.7V-high clamp and
0.65V-low clamp. The 150µs timer generates a MOSFET
turn-on signal if the drive output has been low for more
than 150µs from the falling edge of the drive output.
1. Error Amplifier Block
The error amplifier block consists of a transconductance
amplifier, output OVP comparator, and disable compara-
tor. For the output voltage control, a transconductance
amplifier is used instead of the conventional voltage
amplifier. The transconductance amplifier (voltage con-
trolled current source) aids the implementation of OVP
and disable function. The output current of the amplifier
changes according to the voltage difference of the invert-
ing and non-inverting input of the amplifier. The output
voltage of the amplifier is compared with the internal
ramp signal to generate the switch turn-off signal. The
OVP comparator shuts down the output drive block when
the voltage of the INV pin is higher than 2.675V and
there is 0.175V hysteresis. The disable comparator dis-
ables the operation of the FAN7529 when the voltage of
the inverting input is lower than 0.45V and there is
100mV hysteresis. An external small signal MOSFET
can be used to disable the IC, as shown in Figure 33.
The IC operating current decreases below 65µA to
reduce power consumption if the IC is disabled.
Turn-on
Signal
150μs
V
in
Timer
ZCD
RZCD
5
S
Q
6.7V
1.4V
1.5V
Zero Current
Detector
R
FAN7529 Rev. 00
Figure 34. Zero Current Detector Block
3. Sawtooth Generator Block
The output of the error amplifier and the output of the
sawtooth generator are compared to determine the
MOSFET turn-off instance. The slope of the sawtooth is
determined by an external resistor connected to the
MOT pin. The voltage of the MOT pin is 2.9V and the
slope is proportional to the current flowing out of the
MOT pin. The internal ramp signal has a 1V offset; there-
fore, the drive output is shut down if the voltage of the
COMP pin is lower than 1V. The MOSFET on-time is
maximum when the COMP pin voltage is 5V. According
to the slope of the internal ramp, the maximum on-time
can be programmed. The necessary maximum on-time
depends on the boost inductor, lowest AC line voltage,
and maximum output power. The resistor value should
be designed properly.
2.675V
2.5V
OVP
Disable
0.45V 0.35V
Vref1 (2.5V)
Vout
Error Amp
INV
Gm
1
Disable
Signal
2
COMP
Off Signal
FAN7529 Rev. 00
1V Offset
MOT
Saw Tooth
Generator
Figure 33. Error Amplifier Block
3
2.9V
2. Zero Current Detection Block
Error Amp
Output
The zero current detector (ZCD) generates the turn-on
signal of the MOSFET when the boost inductor current
reaches zero using an auxiliary winding coupled with the
inductor. If the voltage of the ZCD pin goes higher than
1.5V, the ZCD comparator waits until the voltage goes
FAN7529 Rev. 00
Figure 35. Sawtooth Generator Block
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
12
4. Over-Current Protection Block
5. Switch Drive Block
The MOSFET current is sensed using an external sens-
ing resistor for the over-current protection. If the CS pin
voltage is higher than 0.8V, the over-current protection
comparator generates a protection signal. An internal RC
filter is included to filter switching noise.
The FAN7529 contains a single totem-pole output stage
designed for direct drive of the power MOSFET. The
drive output is capable of up to +500/-800mA peak cur-
rent with a typical rise and fall time of 50ns with 1nF load.
The output voltage is clamped to 13V to protect the
MOSFET gate if the VCC voltage is higher than 13V.
OCP
Signal
40k
8pF
6. Under-Voltage Lockout Block
4
CS
If the VCC voltage reaches 12V, the IC’s internal blocks
are enabled and start operation. If the VCC voltage drops
below 8.5V, most of the internal blocks are disabled to
reduce the operating current. VCC voltage should be
higher than 8.5V under normal conditions.
Over Current Protection
Comparator
0.8V
FAN7529 Rev. 00
Figure 36. Over-Current Protection Block
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
13
Typical Application Circuit
Application
Output Power
100W
Input Voltage
Output Voltage
Universal input
Ballast
400V
(85~265VAC
)
Features
High efficiency (>90% at 85VAC input)
Low Total Harmonic Distortion (THD) (<10% at 265VAC input, 25W load)
Key Design Notes
R1, R2, R5, C11 should be optimized for best THD characteristic.
1. Schematic
T1
PFC OUTPUT
VAUX
D2
BD
C5
R4
R3
R5
D3
R6
R10
C10
ZD1
Q1
NTC
C11
D1
C9
C3
C4
8
7
6
5
VCC
ZCD
GND
OUT
C2
R9
LF1
FAN7529
R2
C1
V1
R11
INV
1
COMP
2
MOT
3
CS
4
R8
C8
R7
F1
C7 R1
C6
FAN7529 Rev. 00
AC INPUT
Figure 37. Schematic
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
14
2. Inductor Schematic Diagram
4
NVcc
2
3
Np
5
FAN7529 Rev. 00
Figure 38. Inductor Schematic Diagram
3. Winding Specification
No
Pin (s→f)
5 → 3
Wire
0.1φ × 30
Turns
Winding Method
Np
58
Solenoid Winding
Insulation: Polyester Tape t = 0.050mm, 4 Layers
NVcc 2 → 4
0.2φ × 1
8
Solenoid Winding
Outer Insulation: Polyester Tape t = 0.050mm, 4 Layers
Air Gap: 0.6mm for each leg
4. Electrical Characteristics
Pin
Specification
Remarks
Inductance
3 - 5
600µH ± 10%
100kHz, 1V
5. Core & Bobbin
Core: EI 3026
Bobbin: EI3026
Ae(mm2): 111
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
15
6. Demo Circuit Part List
Part
F1
Value
3A/250V
10D-9
Note
Part
Value
Note
Fuse
NTC
Inductor
T1
600µH
EI3026
NTC
MOSFET
Resistor
Q1
FQPF13N50C
Fairchild
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
56kΩ
1/4W
1/4W
1/2W
1/2W
1/4W
1/4W
1/2W
1/4W
1/4W
1/4W
1/4W
820kΩ
330kΩ
150Ω
20kΩ
10Ω
Diode
D1
D2
1N4148
BYV26C
SB140
Fairchild
600V, 1A
Fairchild
18V
D3
ZD1
1N4746
0.2Ω
10kΩ
10kΩ
2MΩ
Bridge Diode
KBL06
BD
LF1
IC1
V1
600V/4A
Wire 0.4mm
Fairchild
470V
12.6kΩ
Line Filter
Capacitor
40mH
FAN7529
471
C1
C2
C3
C4
C5
C6
C7
150nF/275VAC
470nF/275VAC
2.2nF/3kV
Box Capacitor
Box Capacitor
IC
Ceramic Capacitor
Ceramic Capacitor
2.2nF/3kV
TNR
47µF/25V
47nF/50V
Electrolytic Capacitor
Ceramic Capacitor
Multilayer Ceramic
Capacitor
C8
220nF/50V
C9
100µF/450V
12nF/100V
56pF/50V
Electrolytic Capacitor
Film Capacitor
C10
C11
Ceramic Capacitor
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
16
7. Layout
Separate the power ground
and the signal ground
Power Ground
Signal Ground
Place the output voltage
sensing resistors close to IC
Figure 39. PCB Layout Considerations for FAN7529
8. Performance Data
P
85V
115V
230V
265V
AC
OUT
AC
AC
AC
PF
THD
0.998
5.1%
0.998
3.6%
0.991
5.2%
0.984
6.2%
96%
100W
75W
50W
25W
Efficiency
PF
90.9%
0.999
4.1%
93.7%
0.998
3.6%
95.6%
0.986
5.0%
0.975
5.7%
95.3%
0.956
6.2%
93.4%
0.876
8.7%
88.1%
THD
Efficiency
PF
91.6%
0.998
4.4%
93.3%
0.997
5.0%
94.6%
0.974
5.7%
THD
Efficiency
PF
91.3%
0.995
7.9%
91.9%
0.991
8.6%
92.7%
0.923
8.3%
THD
Efficiency
86.4%
87.1%
87.3%
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
17
Mechanical Dimensions
8-DIP
Dimensions are in millimeters (inches) unless otherwise noted.
6.40 0.20
0.252 0.008
#1
#4
#8
#5
3.30 0.30
0.130 0.012
5.08
0.200
MAX
7.62
3.40 0.20
0.134 0.008
0.300
0.33
0.013
MIN
September 1999, Rev B
8dip_dim.pdf
Figure 40. 8-Lead Dual In-Line Package (DIP)
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
18
Mechanical Dimensions (Continued)
8-SOP
Dimensions are in millimeters (inches) unless otherwise noted.
0.1~0.25
0.004~0.001
MIN
1.55 0.20
0.061 0.008
#8
#5
#1
#4
6.00 0.30
0.236 0.012
1.80
0.071
MAX
3.95 0.20
0.156 0.008
5.72
0.225
0.50 0.20
0.020 0.008
September 2001, Rev B1
sop8_dim.pdf
Figure 41. 8-Lead Small Outline Package (SOP)
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
19
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
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As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Obsolete
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
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This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I26
© 2006 Fairchild Semiconductor Corporation
FAN7529 Rev. 1.0.2
www.fairchildsemi.com
20
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