FAN7085_12 [FAIRCHILD]
High Side Gate Driver with Recharge FET; 高边栅极驱动器与充电FET型号: | FAN7085_12 |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | High Side Gate Driver with Recharge FET |
文件: | 总14页 (文件大小:407K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
September 2012
FAN7085_GF085
High Side Gate Driver with Recharge FET
Features
Description
•
Qualified to AEC Q100
The FAN7085_GF085 is a high-side gate drive IC with reset
input and built-in recharge FET. It is designed for high voltage
and high speed driving of MOSFET or IGBT, which operates up
to 300V. Fairchild's high-voltage process and common-mode
noise cancellation technique provide stable operation in the
high side driver under high-dV/dt noise circumstances. Logic
input is compatible with standard CMOS outputs. The UVLO cir-
cuits prevent from malfunction when VCC and VBS are lower
than the specified threshold voltage. It is available with space
saving SOIC-8 Package. Minimum source and sink current
capability of output driver is 250mA and 250mA. Built-in
recharge FET to refresh bootstrap circuit is very useful for circuit
topology requiring switches on low and high side of load.
•
Floating channel designed for bootstrap operation fully oper-
ational up to 300V.
•
•
•
•
•
•
•
•
Tolerance to negative transient voltage on VS pin
dv/dt immune.
Gate drive supply range from 4.5V to 20V
Under-voltage lockout
CMOS Schmitt-triggered inputs with pull-down and pull-up
High side output out of phase with input (Inverted input)
Reset input
Internal recharge FET for bootstrap refresh
SOIC-8
Typical Applications
•
Diesel and gasoline injectors/valves
•
MOSFET-and IGBT high side driver applications
For Fairchild’s definition of “green” Eco Status, please visit:
http://www.fairchildsemi.com/company/green/rohs_green.html
Ordering Information
Operating
Temp.
Device
Package
FAN7085M_GF085 SOIC-8
FAN7085MX_GF085 SOIC-8
X : Tape & Reel type
-40 C ~ 125 C
-40 C ~ 125 C
©2012 Fairchild Semiconductor Corporation
FAN7085_GF085 Rev. 1.0.1
1
www.fairchildsemi.com
Block Diagrams
VB
HO
VS
Pulse Filter
Flip Flop
Brake before
make
Under
Voltage Reset
VB to VS
Under Voltage
Reset VCC to GND
VCC
Level Shifter
RESET-
Logic
Pulse
Filter
ON
Delay
Level Shifter
OFF
IN-
GND
Pin Assignments
1
2
8
7
VB
VCC
IN-
HO
3
4
6
5
NC
VS
GND
RESET-
Pin Definitions
Pin Number
Pin Name
I/O
Pin Function Description
1
2
3
4
5
6
7
8
VCC
IN-
P
I
Driver supply voltage, typically 5V
Driver control signal input (Negative Logic)
Ground
GND
RESET-
VS
P
I
Driver enable input signal (Negative Logic)
High side floating offset for MOSFET Source connection
No connection (No Bond wire)
P
-
NC
HO
A
P
High side drive output for MOSFET Gate connection
Driver output stage supply
VB
©2012 Fairchild Semiconductor Corporation
FAN7085_GF085 Rev. 1.0.1
2
www.fairchildsemi.com
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are abso-
lute voltages referenced to GND.
Parameter
Symbol
VBS
Min.
-0.3
-5
Max.
25
Unit
High side floating supply voltage
V
V
High side driver output stage voltage
VB
325
Neg. transient: 0.5 ms, external MOSFET off
High side floating supply offset voltage
Neg. transient 0.2 us
Vs
-25
300
V
High side floating output voltage
Supply voltage
VHO
VCC
VIN
VS-0.3
-0.3
VB+0.3
25
V
V
Input voltage for IN-
-0.3
Vcc+0.3
Vcc+0.3
0.625
200
V
Input voltage for RESET-
Power Dissipation 1)
Thermal resistance, junction to ambient 1)
VRES
Pd
-0.3
V
W
Rthja
VESD
C/W
V
Electrostatic discharge voltage
(Human Body Model)
1.5K
500
Charge device model
Junction Temperature
Storage Temperature
VCDM
Tj
V
150
150
C
C
TS
-55
Note: 1) The thermal resistance and power dissipation rating are measured bellow conditions;
JESD51-2: Integrated Circuit Thermal Test Method Environmental Conditions - Natural condition(StillAir)
JESD51-3: Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Package
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.-40°C <= Ta <= 125°C
Parameter
Symbol
Min.
Max.
Unit
High side floating supply voltage(DC)
Transient:-10V@ 0.2 us
VB
VS+4.5
VS+20
V
V
V
High side floating supply offset voltage(DC)
@VBS=7V
VS
VS
-3
300
300
High side floating supply offset voltage(Transient)
0.2us @VBS<25V
-25
High side floating output voltage
Allowable offset voltage Slew Rate 1)
Supply voltage for logic part
Input voltage for IN-
VHO
dv/dt
Vs
-
VB
50
V
V/ns
V
VCC
4.5
0
20
VIN
Vcc
Vcc
200K
-
V
Input voltage for RESET-
Switching frequency 2)
Minimum low input width 3)
Minimum high input width 3)
Minimum operating voltage of VB related to GND
Ambient temperature
VRESET
Fs
0
V
Hz
ns
ns
V
tIN(low,min)
tIN(high,min)
1000
60
-
4)
VB(MIN)
4
-
Ta
-40
125
C
Note: 1) Guaranteed by design.
2) Duty = 0.5, VBS >=7V
3) Guaranteed by design. Pulse widths below the specified values, may be ignored. Output will either follow the input signal or will ignore it.
No false output state is guaranteed when minimum input width is smaller than tin
4) Guaranteed by design
©2012 Fairchild Semiconductor Corporation
FAN7085_GF085 Rev. 1.0.1
3
www.fairchildsemi.com
Statics Electrical Characteristics
Unless otherwise specified, -40°C <= Ta <= 125°C, VCC = 5V, VBS = 7V, VS = 0V, VRESET = 5V, RL = 50, CL = 2.5nF.
Parameter
Symbol
Conditions
Min.
Typ. Max. Unit
VCC and VBS Supply Characteristics
VCC and VBS supply under voltage
positive going threshold
VCCUV+
VBSUV+
Vcc and VBS rising from 0V
-
3.7
3.4
0.3
4.3
V
V
V
VCC and VBS supply under voltage
negative going threshold
VCCUV-
VBSUV-
Vcc and VBS dropping from 5V
-
2.8
0.02
-
-
VCC and VBS under voltage hysteresis
VCCUVH
VBSUVH
Under voltage lockout response time
tduvcc
tduvbs
VCC: 6.5V->2.4V or 2.4V->6.5V
VBS: 6.5V->2.4V or 2.4V->6.5V
0.5
0.5
20
20
us
us
Offset supply leakage current
Quiescent Vcc supply current
Quiescent VBS supply current
ILK
VB=VS=300V
Vcc=20V
-
-
-
-
200
500
100
uA
uA
uA
IQCC
IQBS1
Static mode,
VBS=7V, VIN=0 or 5V
Quiescent VBS supply current
IQBS2
Static mode,
VBS=16V, VIN=0 or 5V
200
210
uA
VBS drop due to output turn-on
(Design guaranty)
VBS
VBS=7V, Cbs=1uF, tdIG-IN =3uS,
tTEST=100uS
mV
Input Characteristics
High logic level input voltage for IN-
Low logic level input voltage for IN-
Low logic level input bias current for IN-
High logic level input bias current for IN-
Full up resistance at IN
VIH
VIL
0.6VCC
-
-
-
V
V
-
0.28VCC
IIN-
VIN=0
5
-
25
-
60
uA
uA
V
IIN+
VIN=5V
5
1000
-
RIN
83
200
-
High logic level input voltage for RESET-
Low logic level input voltage for RESET-
High logic level input current for RESET-
Low logic level input bias current for RESET-
Full down resistance at RESET-
Output characteristics
VRH
VRL
IRES+
IRES-
RRES
0.6Vcc
0.28Vcc
60
V
VRESET=5V
VRESET=0
5
25
uA
uA
5
83
200
1000
High level output voltage, VB - VHO
Low level output voltage, VHO-GND
Peak output source current
VOH
VOL
IO+
IO=0
IO=0
-
-
0.1
0.1
-
V
V
-
-
VIN=5V
VIN=0
250
250
450
450
15.5
15.5
mA
mA
Peak output sink current
IO-
-
Equivalent output resistance
ROP
RON
28
28
Recharge Characteristics
Recharge TR turn-on propagation delay
Recharge TR turn-off propagation delay
Recharge TR on-state voltage drop
Dead Time Characteristics
Ton_rech
Toff_rech
VRECH
4
7.9
0.2
9.8
0.4
1.2
us
us
V
Is=1mA, VIN=5V @125C
High side turn-off to recharge gate turn-on
Recharge gate turn-off to high side turn-on
DTHOFF
DTHON
Vcc=5V, VS=7V
Vcc=5V, VS=7V
4
7.8
0.4
9.8
0.7
us
us
0.1
Note: The input parameter are referenced to GND. The VO and IO parameters are referenced to GND.
©2012 Fairchild Semiconductor Corporation
FAN7085_GF085 Rev. 1.0.1
4
www.fairchildsemi.com
Dynamic Electrical Characteristics
Unless otherwise specified, -40°C <= Ta <= 125°C, VCC = 5V, VBS = 7V, VS = 0V, VRESET = 5V, RL = 50, CL = 2.5nF.
Parameter
Symbol
Conditions
Min. Typ. Max. Unit
Input-to-output turn-on propagation delay
tplh
50% input level to 10% output level,
VS = 0V
0.56
1
us
Input-to-output turn-off propagation delay
tphl
50% input level to 90% output level
VS = 0V
-
0.15
0.5
us
RESET-to-output turn-off propagation delay
RESET-to-output turn-on propagation delay
Output rising time
tphl_res
tplh_res
tr1
50% input level to 90% output level
50% input level to 10% output level
Tj=25C
-
-
-
0.17
0.56
65
-
0.5
1
us
us
ns
ns
ns
ns
ns
ns
ns
ns
200
400
200
400
200
300
200
300
tr2
tr3
Tj=25C,VBS=16V
VBS=16V
65
-
tr4
Output falling time
tf1
Tj=25C
-
25
-
tf2
tf3
Tj=25C,VBS=16V
25
-
tf4
VBS=16V
©2012 Fairchild Semiconductor Corporation
FAN7085_GF085 Rev. 1.0.1
5
www.fairchildsemi.com
Application Information
1. Logic Tables
VCC
< VCCUVLO-
X
VBS
RESET-
X
IN-
X
Ho
OFF
OFF
OFF
ON
RechFET
ON
X
X
LOW
X
X
ON
X
X
HIGH
LOW
LOW
ON
> VCCUVLO+
> VCCUVLO+
> VBSUVLO+
< VBSUVLO-
HIGH
HIGH
OFF
OFF
OFF
Notes:
X means independent from signal
IN-=LOW indicates that the high side NMOS is ON
IN-=HIGH indicates that the high side NMOS is OFF
RechFET =ON indicates that the recharge MOSFET is ON
RechFET =OFF indicates that the recharge MOSFET is OFF
©2012 Fairchild Semiconductor Corporation
FAN7085_GF085 Rev. 1.0.1
6
www.fairchildsemi.com
Typical Application Circuit
1. Typical Application Circuit
Up to 300V
D1
VCC
VCC
VB
HO
NC
R1
R2
Load
IN-
GND
C3
C2
RESET- VS
C1
2. Application Example
Voltage Source
R1
From Charge Pump
5V
D5
VCC
VB
HO
NC
S1
IN-
R2
GND
C3
RESET- VS
C2
C1
Load
D3
R3
R4
S2
D4
From LS Driver
C4
GND
©2012 Fairchild Semiconductor Corporation
FAN7085_GF085 Rev. 1.0.1
7
www.fairchildsemi.com
Input-Output Waveforms
1. Input/Output Timing Diagrams
IN-
RESET-
90%
90%
VS
10%
10%
tr
tf
VHO
tphl
Recharge
tplh
Toff_rech
Ton_rech
Figure.1 Input and Output Timing Diagram and Switching Time Waveform Definition
2. Reset Timing Diagrams
IN-
RESET-
VHO
tplh_res
tphl_res
Figure.2 Reset and Output Timing Diagram
©2012 Fairchild Semiconductor Corporation
FAN7085_GF085 Rev. 1.0.1
8
www.fairchildsemi.com
3.VB Drop Voltage Diagram
Ig
IN-
Ig
VCC
IN-
VB
HO
NC
50R
RESET-
1u
GND
RESET- VS
2n5
7V
VBdrop
VB-VS
Figure3.b VB Drop Voltage Test Circuit
Brake before make
Figure3.a VB Drop Voltage Diagram
©2012 Fairchild Semiconductor Corporation
FAN7085_GF085 Rev. 1.0.1
9
www.fairchildsemi.com
Performance Graphs
This performance graphs based on ambient temperature -40C ~125C
2.6
2.4
2.2
2.0
1.8
3.2
VBS=7V, RL=50, CL=2.5nF
3.0
VBS=7V, RL=50, CL=2.5nF
2.8
2.6
2.4
Typ.
Typ.
2.2
4.4
4.7
5.0
5.3
5.6
5.9
6.2
6.5
4.4
4.7
5.0
5.3
5.6
5.9
6.2
6.5
Vsupply (V)
Vsupply (V)
Figure 4a. Positive IN and RESET Threshold vs VCC Supply
Figure 4b. Negative IN and RESET Threshold vs VCC Supply
500
2000
VCC=5V
VCC=5V, VBS=7V
Typ.
-40oC
125oC
1600
1200
800
400
0
450
400
350
300
-50
0
50
100
150
5
10
15
20
VBS(V)
Temperature (oC)
Figure5a. Output Sink Current vs VBS Supply
Figure5b. Output Source Current vs Temperature
650
250
VCC=5V,VBS=7V, RL=50, CL=2.5nF
VCC=5V,VBS=7V, RL=50, CL=2.5nF
620
590
560
530
500
200
150
Typ.
Typ.
100
-50
-50
0
50
100
150
0
50
100
150
Temperature(oC)
Temperature (oC)
Figure 6b. Turn-Off Propagation Delay Time vs Temperature
Figure 6a. Turn-On Propagation Delay Time vs Temperature
©2012 Fairchild Semiconductor Corporation
FAN7085_GF085 Rev. 1.0.1
10
www.fairchildsemi.com
700
650
600
550
500
250
200
150
100
VCC=5V, VBS=7V, RL=50, CL=2.5nF
VCC=5V, VBS=7V, RL=50, CL=2.5nF
Typ.
Typ.
-50
0
50
100
150
-50
0
50
100
150
Temperature (oC)
Temperature (oC)
Figure 7a. RES to Output Turn-On Propagation Delay vs Temperature Figure 7b. RES to Output Turn-Off Propagation Delay vs Temperatur
50
40
30
20
10
0
50
40
30
20
10
0
VCC=5V, RL=50, CL=2.5nF
VCC=5V, RL=50, CL=2.5nF
Typ.
Typ.
-50
0
50
100
150
-50
0
50
100
150
Temperature (oC)
Temperature (oC)
Figure 8. Logic “0” IN Input Current vs Temperature
Figure 9. Logic “1” RESET Input Current vs Temperature
5.0
4.5
5.0
4.5
Max.
4.0
4.0
Max.
Typ.
3.5
3.5
Typ.
3.0
Min.
2.5
Min.
3.0
2.5
2.0
2.0
-50
0
50
100
150
-50
0
50
100
150
Temperature(oC)
Temperature(oC)
Figure 10a. VBS Under Voltage Threshold(+) vs Temperature
Figure 10b. VBS Under Voltage Threshold(-) vs Temperature
©2012 Fairchild Semiconductor Corporation
FAN7085_GF085 Rev. 1.0.1
11
www.fairchildsemi.com
5.0
4.5
4.0
3.5
3.0
2.5
2.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
Max.
Typ.
Max.
Typ.
Min.
Min.
-50
0
50
100
150
-50
0
50
100
150
Temperature(oC)
Temperature(oC)
Figure 11a. VCC Under Voltage Threshold(+) vs Temperature
Figure 11b. VCC Under Voltage Threshold(-) vs Temperature
10
300
VCC=5v, VBS=7, VRL=50, CL=2.5nF
VCC=5v, VBS=7V, RL=50, CL=2.5nF
260
220
180
8
Typ.
6
Typ.
4
-50
140
-50
0
50
100
150
0
50
100
150
Temperature(oC)
Temperature (oC)
Figure 12. Recharge FET Turn-on Delay time
Figure 12. Recharge FET Turn-off Delay time
10
1.8
1.4
1.0
0.6
0.2
VCC=5v, VBS=7V, RL=50, CL=2.5nF
VCC=5v, VBS=7V, RL=50, CL=2.5nF
8
Typ.
6
Typ.
4
-50
0
50
100
150
0.4
0.6
0.8
1.0
1.2
Temperature (oC)
V (V)
Figure 14. Recharge FET I-V curve
Figure 15. High Side Turn-off to Recharge FET turn-on VS Temperature
©2012 Fairchild Semiconductor Corporation
FAN7085_GF085 Rev. 1.0.1
12
www.fairchildsemi.com
Package Dimensions
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
x 45°
GAGE PLANE
0.25
R0.10
R0.10
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SEATING PLANE
0.90
(1.04)
0.406
DETAIL A
SCALE: 2:1
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
©2012 Fairchild Semiconductor Corporation
FAN7085_GF085 Rev. 1.0.1
13
www.fairchildsemi.com
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®
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FRFET®
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RapidConfigure
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™
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Saving our world, 1mW/W/kW at a time™
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Definition of Terms
Datasheet
Product Status
Definition
Identification
Datasheet contains the design specifications for product development. Specifications may change
in any manner without notice.
Advance Information
Preliminary
Formative / In Design
First Production
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve the design.
No Identification Needed
Obsolete
Full Production
Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.
The datasheet is for reference information only.
Not In Production
Rev. I43
©2012 Fairchild Semiconductor Corporation
FAN7085_GF085 Rev. 1.0.1
14
www.fairchildsemi.com
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