FAN6206MY
更新时间：2024-09-18 12:52:35
品牌：FAIRCHILD
描述：Highly Integrated Dual-Channel Synchronous Rectification Controller
概述
规格参数
数据手册FAN6206MY 概述
Highly Integrated Dual-Channel Synchronous Rectification Controller 高度集成的双通道同步整流控制器 开关式稳压器或控制器
FAN6206MY 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Obsolete | 零件包装代码： | SOIC |
| 包装说明： | SOP, | 针数： | 8 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.31.00.01 | 风险等级： | 5.66 |
| 模拟集成电路 - 其他类型： | DUAL SWITCHING CONTROLLER | 控制技术： | PULSE WIDTH MODULATION |
| 最大输入电压： | 25 V | 最小输入电压： | 8 V |
| 标称输入电压： | 20 V | JESD-30 代码： | R-PDSO-G8 |
| JESD-609代码： | e3 | 长度： | 4.9 mm |
| 湿度敏感等级： | 3 | 功能数量： | 1 |
| 端子数量： | 8 | 最高工作温度： | 105 °C |
| 最低工作温度： | -40 °C | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SOP | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 峰值回流温度（摄氏度）： | 260 |
| 认证状态： | Not Qualified | 座面最大高度： | 1.75 mm |
| 表面贴装： | YES | 切换器配置： | PHASE-SHIFT |
| 温度等级： | INDUSTRIAL | 端子面层： | Matte Tin (Sn) |
| 端子形式： | GULL WING | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | 30 |
| 宽度： | 3.9 mm | Base Number Matches： | 1 |
FAN6206MY 数据手册
通过下载FAN6206MY数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载April 2010
FAN6206
Highly Integrated Dual-Channel Synchronous
Rectification Controller for Dual-Forward Converter
Features
Description
The highly integrated FAN6206 is a dual-channel
synchronous rectification (SR) controller. FAN6206
allows design of a cost-effective power supply with
fewer external components, especially suited for dual-
forward topology used to obtain higher efficiency for
ATX power supplies.
Highly Integrated Dual-Channel SR Controller
Receives Synchronized Driving Signal from the
Primary Side
Internal Linear-Predict Timing Control for DCM
Operation
The primary-side control method provides synchronous
rectification control for dual-forward converters that
operate in continuous conduction mode (CCM).
FAN6206 includes a proprietary linear-predict timing
control mechanism for dual-forward converters that
operate in discontinuous conduction mode (DCM) at
fixed or variable frequency. PWM frequency tracking
with secondary-side winding detection is provided by
adding dividing resistors. The primary-side signals are
generated from Fairchild’s FAN6210 (Primary-Side
Synchronous Rectifier Signal Trigger for Dual-Forward
Converter). The primary-side signals are transferred
through a pulse transformer to the secondary-side. The
benefits of this technique include simple control method
and improved power system reliability.
Ultra-Low VDD Operating Voltage for Different
Output Voltage of PC Power
VDD Over-Voltage Protection
14V Gate Driver Clamp
Applications
PC Power
Server Power
Open-Frame SMPS
FAN6206 is available in 8-pin SOP package.
Ordering Information
Operating
Temperature Range
Packing
Part Number
Package
Method
-40°C to +105°C
FAN6206MY
8-Pin Small Outline Package (SOP)
Tape & Reel
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
Application Diagram
Figure 1. Typical Application
Internal Block Diagram
Figure 2. Functional Block Diagram
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
2
Marking Information
F: Fairchild Logo
Z: Plant Code
X: Year Code
Y: Week Code
TT: Package Type
T: M=SOP
P: Y: Green Package
M: Manufacture Flow Code
Figure 3. Top Mark
Pin Configuration
Figure 4. Pin Configuration
Description
Pin Definitions
Pin #
Name
Winding detection. This pin is used to detect the voltage on the winding during the on-time
period of the primary GATE. An internal current source, ICHG, is determined according to the
voltage on the DET pin.
LPC1,
LPC2
1,2
Synchronized signal to turn on SR. This pin is used to receive the “XN” signal from the primary
side to turn off the SR gate.
3
4
5
SN
SP
Synchronized signal to turn on SR. This pin is used to receive the “XP” signal from the primary-
side to turn-on the SR gate.
Power supply pin. The threshold voltages for startup and turn-off are 8.5V and 7.5V,
respectively.
VDD
6
7
8
GATE2 Driver output for freewheeling synchronous rectifier MOSFET.
GND Ground
GATE1 Driver output for rectifying synchronous rectifier MOSFET.
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VDD
VHV
VL
DC Supply Voltage
SP, SN
30
30
V
V
LPC
-0.3
7.0
V
PD
Power Dissipation at TA < 50°C
400
130
46
mW
°C/W
°C/W
°C
ΘJA
Ψjt
Junction to Ambient Thermal Resistance
Junction to Top Thermal Characteristics
Operating Junction Temperature
TJ
-40
-55
+125
+150
+260
4.00
1.25
TSTG
TL
Storage Temperature Range
°C
Lead Temperature, (Soldering 10 Seconds)
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
°C
ESD
kV
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
TA
Operating Ambient Temperature
-40
+105
°C
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
4
Electrical Characteristics
VDD=20V, TA=25Ԩ, unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ. Max. Units
VDD Section
VOP
Continuously Operating Voltage
Turn-On Threshold Voltage
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
Turn-Off Threshold Voltage
Operating Current
25
9.0
9.0
8.0
8.0
5
V
V
VTH-ON1
VTH-ON2
VTH-OFF1
VTH-OFF2
IDD-OP
8.0
8.0
7.0
7.0
8.5
8.5
7.5
7.5
3
V
V
V
VDD=15V, DET=50KHz
VDD = 7.5V
mA
μA
V
IDD-ST
Startup Current
340
21
500
22
VDD-OVP1
VDD-OVP2
VDD-OVP-HYS1
VDD-OVP-HYS2
tOVP1
VDD Over-Voltage Protection 1
VDD Over-Voltage Protection 2
Hysteresis Voltage for VDD OVP 1
Hysteresis Voltage for VDD OVP 2
VDD OVP Debounce Time 1
VDD OVP Debounce Time 2
20
20
21
22
V
1.2
1.2
40
1.7
1.7
60
2.2
2.2
100
100
V
V
μs
μs
tOVP2
40
60
Output Drive for SR MOSFET Section
VZ1
VZ2
Output Voltage Maximum (Clamp) 1 VDD = 20V
Output Voltage Maximum (Clamp) 2 VDD = 20V
12
12
14
14
V
V
V
V
V
V
VOL1
VOL2
VOH1
VOH2
Output Voltage LOW 1
Output Voltage LOW 2
Output Voltage HIGH 1
Output Voltage HIGH 2
VDD=12V, IO=50mA
VDD=12V, IO=50mA
VDD=12V, IO=50mA
VDD=12V, IO=50mA
0.5
0.5
9
9
VDD=12V, CL=7nF,
OUT=2V~9V
tR1
tR2
tF1
tF2
Rising Time 1
Rising Time 2
Falling Time1
30
30
20
20
70
70
50
50
120
120
100
100
ns
ns
ns
VDD=12V, CL=7nF,
OUT=2V~9V
VDD=12V, CL=7nF,
OUT=9V~2V
VDD=12V, CL=7nF,
OUT=9V~2V
Falling Time 2
ns
V
VZ1
Output Voltage Maximum (Clamp)
VDD = 20V
12
14
tPD-HIGH-SP1
tR+tPD
(Trigger by SP),
|SP-SN|=5V
,
280
280
180
180
350
450
Propagation Delay to OUT HIGH
Propagation Delay to OUT LOW
ns
tPD-HIGH-SP2
tPD-LOW-SN1
tPD-LOW-SN2
350
250
250
450
350
350
tR+tPD
,
(Trigger by SN),
|SP-SN|=5V
ns
ns
tPD-LOW-LPC1
tPD-LOW-LPC2
tON-MAX1
100
100
12
150
150
13
200
200
14
tR+tPD
(Trigger by LPC)
,
Propagation Delay to OUT LOW
Maximum On Time
μs
μs
tON-MAX2
12
13
14
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
5
Electrical Characteristics
VDD=20V, TA=25°C, unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
SP/SN Section
Threshold Voltage of
VN-VP to Turn-Off SR MOS 1
Sweep VN-P- from LOW
to HIGH
VN-P(turn off) 1
VN-P(turn off) 2
VP-N(turn on) 1
VP-N(turn on) 2
3
3
3
3
4
4
4
4
5
5
5
5
5
V
V
Threshold Voltage of
VN-VP to Turn-Off SR MOS 2
Threshold Voltage of
VP-VN to Turn-On SR MOS 1
Sweep VP-N- from LOW
to HIGH
V
Threshold Voltage of
VP-VN to Turn-On SR MOS 2
Sweep VP-N- from LOW
to HIGH
V
Voltage Difference between
SP and SN
| VSP-VSN | /
Ratio_SP-SN
%
MIN(VSP,VSN
)
LPC Section
Connect a Diode
Charge Divide Discharge Current 1N4148 and Divider
Ratio_LPC-RES
2.79
3.00
3.21
Transfer Ratio vs. Input Voltage
(Ratio 12) to LPC,
DET = 3V, VLPC = 3V
V
VLPC-EN1
VLPC-EN2
LPC Enable Threshold Voltage 1
LPC Enable Threshold Voltage 2
1.8
1.8
2.0
2.0
2.2
2.2
V
V
VLPC-CLAMP1 Lower Clamp Voltage 1
VLPC-CLAMP2 Lower Clamp Voltage 2
ILPC-SOURCE1 Maximum Source Current 1
ILPC-SOURCE2 Maximum Source Current 2
ILPC = -5μA
ILPC = -5μA
VLPC = -0.3V
VLPC = -0.3V
0.10
0.10
0.25
0.25
250
250
0.40
0.40
300
300
V
V
μA
μA
Threshold Voltage for Disable
LPC Function
VLPC-LOW1
1.3
1.3
70
1.5
1.5
1.7
1.7
V
V
Threshold Voltage for Disable
LPC Function
VLPC-LOW2
Debounce Time for Disable LPC
μs
μs
tLPC-LOW1
Function
VLPC < VLPC-LOW
100
100
130
130
Debounce Time for Disable LPC
tLPC-LOW2
Function
VLPC < VLPC-LOW
70
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
6
Typical Performance Characteristics
These characteristic graphs are normalized at TA = 25°C.
8.5
8.4
8.3
8.2
8.1
8.0
8.5
8.4
8.3
8.2
8.1
8.0
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature℃
Temperature℃
Figure 5. Turn-On Threshold Voltage 1
Figure 6. Turn-On Threshold Voltage 2
7.7
7.6
7.5
7.4
7.3
7.7
7.6
7.5
7.4
7.3
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature℃
Temperature℃
Figure 7. Turn-Off Threshold Voltage 1
Figure 8. Turn-Off Threshold Voltage 2
2.9
2.8
2.7
2.6
2.5
500
400
300
200
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature℃
Temperature℃
Figure 9. Operating Current
Figure 10.Startup Current
420
400
380
360
340
320
300
280
420
400
380
360
340
320
300
280
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature℃
Temperature℃
Figure 11.Propagation Delay to OUT HIGH 1
(Trigger by SP)
Figure 12.Propagation Delay to OUT HIGH 2
(Trigger by SP)
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
7
Typical Performance Characteristics
These characteristic graphs are normalized at TA = 25°C.
350
300
250
200
150
350
300
250
200
150
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature℃
Temperature℃
Figure 13.Propagation Delay to OUT LOW 1
(Trigger by SN)
Figure 14.Propagation Delay to OUT LOW 2
(Trigger by SN)
180
160
140
120
180
160
140
120
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature℃
Temperature℃
Figure 15.Propagation Delay to OUT LOW 1
(Trigger by LPC)
Figure 16.Propagation Delay to OUT LOW 2
(Trigger by LPC)
14.0
13.5
13.0
12.5
12.0
14.0
13.5
13.0
12.5
12.0
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature℃
Temperature℃
Figure 17.Maximum On Time 1
Figure 18.Maximum On Time 2
5.0
4.5
4.0
3.5
3.0
5.0
4.5
4.0
3.5
3.0
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature℃
Temperature℃
Figure 19.Threshold Voltage of VN-VP
to Turn Off SR MOS 1
Figure 20.Threshold Voltage of VN-VP
to Turn Off SR MOS 2
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
8
Typical Performance Characteristics
These characteristic graphs are normalized at TA = 25°C.
5.0
4.5
4.0
3.5
3.0
5.0
4.5
4.0
3.5
3.0
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature℃
Temperature℃
Figure 21.Threshold Voltage of VP-VN
to Turn On SR MOS 1
Figure 22.Threshold Voltage of VP-VN
to Turn On SR MOS 2
2.2
2.1
2.0
1.9
1.8
2.2
2.1
2.0
1.9
1.8
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature℃
Temperature℃
Figure 23.LPC Enable Threshold Voltage 1
Figure 24.LPC Enable Threshold Voltage 2
0.4
0.3
0.2
0.1
0.4
0.3
0.2
0.1
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature℃
Temperature℃
Figure 25.Lower Clamp Voltage 1
Figure 26.Lower Clamp Voltage 2
300
275
250
225
200
300
275
250
225
200
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature℃
Temperature℃
Figure 27.Maximum Source Current 1
Figure 28.Maximum Source Current 2
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
9
Function Description
Figure 29 and Figure 30 show the simplified circuit
diagram of a dual-forward converter and its key
waveforms. Switches Q1 and Q2 are turned on and off
together. Once Q1 and Q2 are turned on, input voltage is
applied across the transformer primary side and power
is delivered to the secondary side through the
transformer, powering D1. During this time, the
magnetizing current linearly increases. When Q1 and Q2
are turned off, the magnetizing current of the
transformer forces the reset diodes (DR1 and DR2) and
negative input voltage is applied across the transformer
primary side. During this time, magnetizing current
linearly decreases to zero and the secondary-side
inductor current freewheels through diode D2. When
synchronous rectifier SR1 and SR2 are used instead of
diodes D1 and D2, it is important to have proper timing
between drive signals for SR1 and SR2.
Figure 31 shows a typical application circuit. When a
dual-forward converter operates in continuous
conduction mode, the SR gate signals (GATE1 and
GATE2) are mainly controlled by SP and SN signals. SP
and SN signals are transferred through
a pulse
transformer from XP and XN signals, which are
generated by FAN6210 (Primary-Side Synchronous
Rectifier Signal Trigger for Dual Forward Converter).
Figure 31.Typical Application Circuit
Figure 32 shows the timing diagram for continuous
conduction mode (CCM). Figure 33 shows the timing
diagram for discontinuous conduction mode (DCM).
The switching operation of SR MOSFETs Q3 and Q4 is
determined by the SN and SP signals. FAN6206 turns
on SR MOSFETs at the rising edge of the SP signal,
while it turns off the SR MOSFETs at the rising edge of
the SN signal. Within one switching cycle, SP and SN
are obtained two times.
Figure 29.Simplified Circuit Diagram of
Dual-Forward Converter
With a voltage divider R1 and R2 connected from LPC1
to secondary winding, R3 and R4 connected from LPC2
to secondary winding, the PWM timing sequences and
frequency can be tracked precisely. The SR MOSFET is
turned on by SP signal only when the voltage level on
LPC1 or LPC2 pin is pulled LOW to GND.
During PWM-on period, the rectifying SR Q3 is turned on
by the rising edge of the SP signal after a propagation
delay (tPD-HIGH-SP1) and Q3 is turned off by the rising edge
of the SN signal after a propagation delay (tPD-LOW-SN1).
During PWM-off period, the freewheeling SR Q4 is
turned on by the rising edge of the SP signal after a
propagation delay (tPD-HIGH-SP2) and Q4 is turned off by
the rising edge of the SN signal after a propagation
delay (tPD-LOW-SN2) in CCM operation.
In DCM operation, the proprietary Linear-Predict Timing
Control (LPC) technique can provide synchronous
rectification control mechanism for freewheeling SR
MOSFET. Since SN signal is sent following with PWM
signal, the freewheeling SR MOSFET cannot be turned
off in time by SN signal before ILo linearly decreases to
zero. Therefore, the LPC mechanism is applied to turn
off Q3 in DCM mode.
Figure 30.Key Waveforms of Dual-Forward
Converter
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
10
Figure 32. SR Gate is Driven by SP & SN Signal in CCM Mode
Figure 33.Freewheeling SR Turned Off by LPC Mechanism in DCM Mode
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
11
Linear-Predict Timing Control
Under-Voltage Lockout (UVLO)
When a dual-forward converter operates in CCM or
DCM; in PWM tON period, the VIN voltage is applied to
the primary winding and the secondary inductor starts to
rise linearly and store energy. The across voltage on
secondary winding is coupled from primary winding and
proportional to VIN. The SR controller can detect this
winding voltage through a voltage divider and acquire
the VIN level. According to this detected VIN level during
PWM turn-on period, SR controller produces a charge
current ICHG to charge internal capacitor, CT, of the SR
controller. On the other hand, at PWM turn-off period,
the energy stored in the secondary inductor is
discharged. The SR controller also detects the output
voltage level to modulate discharge current IDISCHG of
internal capacitor, CT. Once the internal capacitor
voltage reaches zero, SR controller turns off SR MOS
immediately.
The power-on and off thresholds are fixed at 8.5V and
7.5V. The VDD pin is connected to a 12V output voltage
terminal.
VDD Pin Over-Voltage Protection
The over-voltage conditions are usually caused by open
feedback loops. VDD over-voltage protection is built in to
prevent damage if over voltage occurs. When the
voltage on the VDD pin exceeds 21V, the SR controller
turns off all of SR MOS operations.
R4 is connected between the LPC2 pin and the drain
terminal of Q4. During PWM turn-on period, voltage on
the LPC2 pin is pulled HIGH due to the secondary
winding coupled from primary winding. At this moment,
SR MOS is turned off and the internal body diode of SR
MOS is reverse-biased. During PWM turn-off period, the
potential on the primary winding reverses and the
internal body diode starts to conduct output current. The
voltage on the LPC2 pin is also pulled LOW to GND. R2
is recommended as 10kΩ and the divided voltage level
on the LPC1 pin is suggested between 3V~5V. If the
voltage level of VO is 12V, the resistor values are
recommended as 105kΩ for R3 and 10kΩ for R4. The
R4
turn-off timing of Q4 is determined by the ratio
R3 + R4
R4
as Figure 34 shows. If
off earlier.
decreases, Q4 is turned
R3 + R4
Figure 34.Turn-Off Timing of Freewheeling SR
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
12
Typical Application Circuit (Dual-Forward Converter with SR)
Application
Fairchild Devices
Input Voltage Range
Output
FAN4801
FAN6210
FAN6206
PC Power
90~264VAC
12V/25A
Figure 35. Application Circuit
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
13
Physical Dimensions
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
0.406
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
DETAIL A
SCALE: 2:1
Figure 36. 8-Pin Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
14
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
15
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