FAN5056MV90 [FAIRCHILD]
Switching Controller, Current/voltage-mode, 345kHz Switching Freq-Max, PDSO24, SOIC-24;
| 型号： | FAN5056MV90 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Switching Controller, Current/voltage-mode, 345kHz Switching Freq-Max, PDSO24, SOIC-24 开关 光电二极管 |
| 文件： | 总18页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FAN5056V85/FAN5056V90
High Performance Programmable Synchronous
DC-DC Controller for Multi-Voltage Platforms
Features
Description
• Output programmable in 25mV steps from 1.1V to 1.85V
(90 version) or 1.05V to 1.825V (85 version) using a
dynamically programmable integrated 5-bit DAC
• Controls adjustable linears for Vclock (2.5V),
Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V), and
Vadj (1.2V nominal)
• Remote sense
• Programmable Active Droop™ up to 200mV
• Drives N-Channel MOSFETs
• Overcurrent protection using MOSFET sensing
• Overvoltage protection including startup
• 85% efficiency typical at full load
• Integrated Power Good and Enable/Soft Start functions
• Meets Intel VRM8.5 and VRM9.0 specifications using
minimum number of external components
• 24 pin SOIC package
The FAN5056 is a synchronous mode DC-DC controller IC
which provides a highly accurate, programmable set of output
voltages for multi-voltage platforms such as the Intel Pentium IV,
and provides a complete solution for all Intel VRM8.5 and
VRM9.0 CPU applications, and for other high-performance
processors. The FAN5056 features remote voltage sensing,
independently adjustable current limit, and a proprietary wide-
range Programmable Active Droop™ for optimal converter
transient response and VRM8.5 compliance. The FAN5056
uses a 5-bit D/A converter to dynamically program the output
voltage during operation from 1.1V to 1.85V (FAN5056V90)
or 1.05V to 1.825V (FAN5056V85) in 25mV steps. The
FAN5056 uses a high level of integration to deliver load cur-
rents in excess of 45A from a 5V source with minimal exter-
nal circuitry. Synchronous-mode operation offers optimum
efficiency over the entire specified output voltage range. An
on-board precision low TC reference achieves 0.8% voltage
regulation without expensive external components. The
FAN5056 includes linear regulator controllers for Vclock
(2.5V),Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V),
and Vadjustable (1.2V nominal) each adjustable with an
Applications
• Power supply for Pentium® III Platforms
• VRM for Pentium IV processor
• Programmable multi-output power supply
Block Diagram
+3.3V
+5V
VCCA 21
+1.2V/Adj
19
-
+
9
+
-
REF
RD
PWRGD,
OCL
10
VCCP
OCL
11
12
+
-
REF
+12V
+5V
PWRGD,
OCL
18
20
-
+
+2.5V
RS
OSC
-
+
VCCP
HIDRV
24
1
15
14
13
Digital
2
VCC
Control
-
+
V
-
+
23 LODRV
PWRGD, OCL
22
3.3/1.5V
GNDP
1.24V
Reference
5-Bit
DAC
17
Power
Good
PWRGD
8 7 6 5 4
3
16
ENABLE/SS
VID4/VID25mV
VID0VID2
GNDA
VID1 VID3
Pentium is a registered trademark of Intel Corporation. Programmable Active Droop is a trademark of Fairchild Semiconductor.
REV. 1.0.2 3/28/01
FAN5056V85/FAN5056V90
PRODUCT SPECIFICATION
external divider. The FAN5056 also offers integrated functions
including open-collector Power Good, Output Enable/Soft
Start and current limiting, and is available in a 24 pin SOIC
package.
Pin Assignments
24
23
22
21
20
19
18
17
16
15
14
13
VCCP
LODRV
GNDP
VCCA
VFB
HIDRV
SW
GNDA
1
2
3
VID4/VID25mV
VID3
4
5
6
7
DROOP
ILIM
VID2
VID1
VID0
FAN5056
PWRGD
SS/ENABLE
TYPEDET
VAGPGATE
VAGPFB
8
VADJGATE
VADJFB
VCKGATE
VCKFB
9
10
11
12
Pin Definitions
Pin Number Pin Name
Pin Function Description
1
2
3
4
HIDRV
High Side FET Driver. Connect this pin to the gate of an N-channel MOSFET. The
trace from this pin to the MOSFET gate should be <0.5".
SW
High Side Driver Source and Low Side Driver Drain Switching Node. Together
with DROOP and ILIM pins allows FET sensing for VCC current.
GNDA
Analog Ground. Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
VID4/
VID25mV
Multi-Value Voltage Identification Code Input. This open collector/TTL
compatible input will program the output voltage over the ranges specified in Table
1 (for the FAN5056V90) or Table 2 (for the FAN5056V85). A pull-up resistor is
internal to the controller.
5-8
VID3-0
Voltage Identification Code Inputs. These open collector/TTL compatible inputs
will program the output voltage over the ranges specified in Table 1 (for the
FAN5056V90) or Table 2 (for the FAN5056V85). Pull-up resistors are internal to the
controller.
9
VADJGATE Gate Driver for VADJ Transistor. For Adjustable output.
VADJFB Voltage Feedback for VADJ.
VCKGATE Gate Driver for VCK Transistor. For 2.5V output.
10
11
12
13
14
15
16
VCKFB
Voltage Feedback for VCK.
Voltage Feedback for VAGP.
VAGPFB
VAGPGATE Gate Driver for VAGP Transistor. For 3.3/1.5V output.
TYPEDET Type Detect. Sets 3.3V or 1.5V for AGP.
ENABLE/SS Output Enable. A logic LOW on this pin will disable all outputs. An internal current
source allows for open collector control. This pin also doubles as soft start for all
outputs.
17
18
PWRGD
Power Good Flag. An open collector output that will be logic LOW if any output
voltage is not within 14ꢀ of the nominal output voltage setpoint.
ILIM
VCC Current Feedback. Pin 18 is used in conjunction with pin 2 as the input for the
VCC current feedback control loop. Layout of these traces is critical to system
performance. See Application Information for details.
19
20
DROOP
VFB
Droop Set. Use this pin to set magnitude of active droop.
Vcc Voltage Feedback. Pin 20 is used as the input for the VCC voltage feedback
control loop. See Application Information for details regarding correct layout.
21
VCCA
Analog VCC. Connect to system 5V supply and decouple with a 0.1µF ceramic
capacitor.
2
REV. 1.0.2 3/28/01
PRODUCT SPECIFICATION
FAN5056V85/FAN5056V90
Pin Definitions (Continued)
Pin Number Pin Name
Pin Function Description
22
23
GNDP
Power Ground. Return pin for high currents flowing in pin 24 (VCCP).
LODRV
VCC Low Side FET Driver. Connect this pin to the gate of an N-channel MOSFET
for synchronous operation. The trace from this pin to the MOSFET gate should be
<0.5".
24
VCCP
Power VCC. For all FET drivers. Connect to system 12V supply through a 33Ω, and
decouple with a 1µF ceramic capacitor.
Absolute Maximum Ratings
Supply Voltage VCCP to GND
Supply Voltage VCCA to GND
Voltage Identification Code Inputs, VID0-VID4
All Other Pins
15V
13.5V
VCCA
13.5V
Junction Temperature, TJ
150°C
Storage Temperature
-65 to 150°C
300°C
Lead Soldering Temperature, 10 seconds
Thermal Resistance Junction-to-case, Θ 1
75°C/W
JA
Note 1: Component mounted on demo board in free air.
Recommended Operating Conditions
Parameter
Conditions
Min.
4.50
2.0
Typ.
Max.
Units
V
Supply Voltage VCCA
Input Logic HIGH
5
5.25
V
Input Logic LOW
0.8
70
V
Ambient Operating Temperature
Output Driver Supply, VCCP
0
°C
V
10.8
12
13.2
Electrical Specifications
(VCCA = 5V, VCCP = 12V, VOUT = 1.425V, and TA = +25°C using circuits in Figures 1-2, unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter
Conditions
Min. Typ. Max. Units
VCC Regulator
Output Voltage
See Tables I and II FAN5056V90
FAN5056V85
•
•
1.1
1.05
1.85
1.825
V
A
Output Current
45
Initial Voltage Setpoint
ILOAD = 0.8A, VVID = 1.425V (V85)
VVID = 1.650V (V90)
1.453 1.465 1.477
1.677 1.690 1.703
V
V
Output Temperature Drift
Line Regulation
Internal Droop Impedance3
Maximum Programmable Droop
Output Ripple
TA = 0 to 70°C, VVID = 1.425V
VIN = 4.75V to 5.25V
•
•
-6
mV
mV/V
KΩ
+10
ILOAD = 0.8A to 30A
13.0
200
14.4
15.8
•
mV
20MHz BW, ILOAD = 28A
20
mVpk
REV. 1.0.2 3/28/01
3
FAN5056V85/FAN5056V90
PRODUCT SPECIFICATION
Electrical Specifications (Continued)
(VCCA = 5V, VCCP = 12V, VOUT = 1.425V, and TA = +25°C using circuits in Figures 1-2, unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter
Conditions
Min. Typ. Max. Units
Total Output Variation, Steady State1 VVID = 1.425V3 (V85)
1.650V3 (V90)
•
•
1.360
1.630
1.490
1.700
V
V
Total Output Variation, Transient2
ILOAD = 0.8A to Imax, VVID = 1.425V (V85)
VVID = 1.650V (V90)
•
•
1.335
1.630
1.515
1.700
V
V
Short Circuit Detect Current
Efficiency
•
45
50
83
50
50
60
µA
ꢀ
I
LOAD = 18A, VVID = 1.425V
Output Driver Rise & Fall Time
Output Driver Deadtime
Duty Cycle
See Figure 3
See Figure 3
nsec
nsec
ꢀ
0
100
4.24
9.35
5V UVLO
•
•
3.76
7.65
4
V
12V UVLO
8.5
V
Adjustable Linear Regulator
Output Voltage
ILOAD ≤ 2A
•
•
1.152
2.375
1.2
80
1.248
2.625
V
Over Current Trip Level
VCLK Linear Regulator
Output Voltage
ꢀVO
ILOAD ≤ 2A
2.5
80
V
Over Current Trip Level
VAGP Linear Regulator
Output Voltage
ꢀVO
ILOAD ≤ 2A, TYPEDET = 0V
•
•
1.425
3.135
1.5
3.3
80
1.575
3.465
V
V
Output Voltage
ILOAD ≤ 2A, TYPEDET = OPEN
Over Current Trip Level
Common Functions
Oscillator Frequency
PWRGD Threshold4 Switcher
ꢀVO
•
255
300
345
kHz
ꢀ
Logic HIGH [VVID + 85mV]
Logic LOW [VVID–155mV]
•
•
88
80
112
120
PWRGD Delay Switcher
HIGH → LOW
6
µsec
mV
PWRGD Hysteresis Switcher
PWRGD Threshold4 Linear
Regulators
25
80
All Outputs
•
ꢀVout
Notes:
1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Droop, Output Ripple and Output Temperature Drift and is
measured at the converter’s VFB sense point.
2. As measured at the converter’s VFB sense point. For motherboard applications, the PCB layout should exhibit no more than
0.5mΩ trace resistance between the converter’s output capacitors and the CPU. Remote sensing should be used for optimal
performance.
3. Using the VFB pin for remote sensing of the converter’s output at the load, and the appropriate droop, the converter will be in
compliance with Intel’s VRM 8.5 (FAN5056V85) or VRM9.0 (FAN5056V90) specification. If Intel specifications on maximum
plane resistance from the converter’s output capacitors to the CPU are met, the specifications at the capacitors will also be
met.
4. PWRGD will be high only if BOTH the linears and the switcher conditions are met. PWRGD will be low if EITHER condition is met.
4
REV. 1.0.2 3/28/01
PRODUCT SPECIFICATION
FAN5056V85/FAN5056V90
Table 1. Output Voltage Programming Codes for FAN5056V90
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Nominal VOUT
Output Off
1.100V
1.125V
1.150V
1.175V
1.200V
1.225V
1.250V
1.275V
1.300V
1.325V
1.350V
1.375V
1.400V
1.425V
1.450V
1.475V
1.500V
1.525V
1.550V
1.575V
1.600V
1.625V
1.650V
1.675V
1.700V
1.725V
1.750V
1.775V
1.800V
1.825V
1.850V
Note:
1. 0 = processor pin is tied to GND.
1 = processor pin is open.
REV. 1.0.2 3/28/01
5
FAN5056V85/FAN5056V90
PRODUCT SPECIFICATION
Table 2. Output Voltage Programming Codes for FAN5056V85
VID25mV
VID3
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
VID2
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
VID1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Nominal VOUT
1.050V
1.075V
1.100V
1.125V
1.150V
1.175V
1.200V
1.225V
1.250V
1.275V
1.300V
1.325V
1.350V
1.375V
1.400V
1.425V
1.450V
1.475V
1.500V
1.525V
1.550V
1.575V
1.600V
1.625V
1.650V
1.675V
1.700V
1.725V
1.750V
1.775V
1.800V
1.825V
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Note:
1. 0 = processor pin is tied to GND.
1 = processor pin is open
6
REV. 1.0.2 3/28/01
PRODUCT SPECIFICATION
FAN5056V85/FAN5056V90
Typical Operating Characteristics
(VCCA = 5V, VCCP = 12V, and TA = +25°C using circuits in Figure 1–2, unless otherwise noted.)
Vcpu Efficiency vs.Output Current
Droop,Circuit of Fig.1
90
1.48
1.46
85
1.44
80
1.42
1.4
75
70
65
1.38
1.36
1.34
2
4
6
8
10
12
14
16
18
20
22
24
26
28
0
3
6
9
12
15
18
21
24
28
Output Current (A)
Output Current (A)
Output Ripple, 1.425 @ 28A
Transient Response, 28A to 0.1A
1.515V
1.425V
1.335V
Time (2 s/division)
Time (20 s/division)
Transient Response, 0.1A to 28A
Switching Waveforms, 28A Load
1.515V
HIDRV
pin
1.425V
1.335V
LODRV
pin
Time (20 s/division)
Time (20 s/division)
REV. 1.0.2 3/28/01
7
FAN5056V85/FAN5056V90
PRODUCT SPECIFICATION
Typical Operating Characteristics (continued)
Output Startup from Enable
Time (20ms/div)
Application Circuit
L1
(Optional)
+5V
CIN
C1
R6
R7
R5
C2
R2
R1
C5
1
Q1
Q2
24
23
22
+12V
L2
2
3
VO
4
21
20
19
18
17
COUT
VID25mV
U1
R3
5
6
7
8
9
FAN5056V85
D1
VID3
VID2
VID1
C3
Q5
VCC
R4
3.3V IN
Q3
VID0
PWRGD
C6
16
15
14
ENABLE/SS
10
11
TYPEDET
C4
3.3/1.5V
(AGP)†
12
13
Q4
1.2V†
C8
C7
2.5V†
C9
† Adjustable with an external divider.
Figure 1. Application Circuit for VRM8.5 Motherboards
(Worst Case Analyzed! See Appendix for Details)
8
REV. 1.0.2 3/28/01
FAN5056V85/FAN5056V90
PRODUCT SPECIFICATION
Table 3. FAN5056 Application Bill of Materials for Intel VRM8.5 Motherboards
(Components based on Worst Case Analysis—See Appendix for Details)
Reference Manufacturer Part #
Quantity Description
Requirements/Comments
C1
C2, C5
C3-4,C6
C7-9
CIN
AVX
TAJB475M010R5
1
2
3
3
4
8
1
4.7µF, 10V Capacitor
Panasonic
ECU-V1C105ZFX
1µF, 16V Capacitor
Panasonic
ECU-V1H104ZFX
100nF, 50V Capacitor
Sanyo
6MV1000FA
1000µF, 6.3V
Electrolytic
Rubycon
16ZL1000M
1000µF, 16V
Electrolytic
IRMS = 2.3A
COUT
D1
Rubycon
6.3ZL1500M
1500µF, 6.3V
Electrolytic
ESR ≤ 23mΩ
Motorola
8A Schottky Diode
MBRD835L
L1
Any
Optional 1.3µH, 10A Inductor
DCR ~ 6mΩ
See Note 1.
L2
Coiltronics
HC2-1R0
1
2
2
3
1.0µH, 34A Inductor
N-Channel MOSFET
N-Channel MOSFET
N-Channel MOSFET
DCR ~ 1mΩ
Q1
Fairchild
FDD6690A
RDS(ON) = 17mΩ @ VGS = 4.5V
See Note 2.
Q2
Fairchild
FDD6672A
RDS(ON) = 9.5mΩ @ VGS =
4.5V See Note 2.
Q3-5
Fairchild
NDB4032L
R1, R6
R2-3
R4
Any
Any
Any
Any
Any
2
2
1
1
1
1
10Ω
4.7Ω
10KΩ
R5
20KΩ
R7
6.19KΩ
DC/DC Controller
U1
Fairchild
FAN5056V85M
Notes:
1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with
Intel dI/dt requirements. L1 may be omitted if desired.
2. For 30A designs using the TO-220 MOSFETs, heatsinks with thermal resistance ΘSA < 20°C/W should be used. For designs
using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections,
refer to Applications Bulletins AB-8 and AB-15.
9
REV. 1.0.2 3/28/01
PRODUCT SPECIFICATION
FAN5056V85/FAN5056V90
L1
(Optional)
+5V
CIN
C1
R6
R7
R5
C2
R2
R1
1
Q1
L2
24
23
22
+12V
C5
2
3
VO
4
21
20
19
18
17
COUT
Q2
U1
FAN5056V90
VID4
VID3
VID2
VID1
R3
5
6
7
8
9
D1
C3
Q5
VCC
R4
3.3V IN
Q3
VID0
PWRGD
16
15
14
ENABLE/SS
C6
10
11
TYPEDET
C4
3.3/1.5V
(AGP)†
12
13
Q4
1.2V†
C8
C7
2.5V†
C9
† Adjustable with an external divider.
Figure 2. Application Circuit for VRM9.0 Motherboards
(Worst Case Analyzed! See Appendix for Details)
REV. 1.0.2 3/28/01
10
PRODUCT SPECIFICATION
FAN5056V85/FAN5056V90
Table 4. FAN5056 Application Bill of Materials for Intel VRM9.0 Motherboards
(Components based on Worst Case Analysis—See Appendix for Details)
Reference Manufacturer Part #
Quantity Description
Requirements/Comments
C1
C2, C5
C3-4,C6
C7-9
CIN
AVX
TAJB475M010R5
1
4.7µF, 10V Capacitor
Panasonic
ECU-V1C105ZFX
2
1µF, 16V Capacitor
Panasonic
ECU-V1H104ZFX
3
100nF, 50V Capacitor
Sanyo
6MV1000FA
3
1000µF, 6.3V
Electrolytic
Rubycon
16ZL1000M
3
1000µF, 16V
Electrolytic
IRMS = 2.3A
COUT
D1
Rubycon
6.3ZL1500M
12
1
1500µF, 6.3V
Electrolytic
ESR ≤ 23mΩ
Fairchild
8A Schottky Diode
MBRD835L
L1
L2
Any
Optional 1.3µH, 10A Inductor
DCR ~ 6mΩ, See Note 1.
DCR ~ 1mΩ
Coiltronics
HC2-1R0
1
2
2
3
1.0µH, 34A Inductor
N-Channel MOSFET
N-Channel MOSFET
N-Channel MOSFET
Q1
Q2
Fairchild
FDD6690A
RDS(ON) = 17mΩ @ VGS = 4.5V
See Note 2.
Fairchild
FDD6672A
RDS(ON) = 9.5mΩ @ VGS = 4.5V
See Note 2.
Q3-5
Fairchild
NDB4032L
R1, R6
R2-3
R4
Any
Any
Any
Any
Any
2
2
1
1
1
1
10Ω
4.7Ω
10KΩ
R5
20KΩ
R7
6.19KΩ
DC/DC Controller
U1
Fairchild
FAN5056V90M
Notes:
1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply
with Intel dI/dt requirements. L1 may be omitted if desired.
2. For 35A designs using the TO-220 MOSFETs, heatsinks with thermal resistanceΘSA < 20°C/W should be used. For designs
using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections,
refer to Applications Bulletins AB-8 and AB-15.
Test Parameters
tR
tF
90%
90%
HIDRV
10%
tDT
10%
tDT
2V
2V
LODRV
2V
Figure 3. Output Drive Timing Diagram
2V
REV. 1.0.2 3/28/01
11
FAN5056V85/FAN5056V90
PRODUCT SPECIFICATION
Internal Voltage Reference
Application Information
The reference included in the FAN5056 is a precision band-
gap voltage reference. Its internal resistors are precisely
trimmed to provide a near zero temperature coefficient (TC).
Based on the reference is the output from an integrated 5-bit
DAC.
The FAN5056 Controller
The FAN5056 is a programmable synchronous DC-DC con-
troller IC. When designed around the appropriate external
components, the FAN5056 can be configured to deliver more
than 45A of output current, as appropriate for Intel’s
In the FAN5056V90, the DAC monitors the 5 voltage identi-
fication pins, VID0-4, and scales the voltage linearly from
1.100V to 1.850V in 25mV steps. The code 11111 turns the
FAN5056A off.
VRM8.5 nd VRM9.0, and other processors. The FAN5056
functions as a fixed frequency PWM step down regulator.
Main Control Loop
Refer to the FAN5056 Block Diagram on page 1. The
FAN5056 implements “summing mode control,” which is
different from both classical voltage-mode and current-mode
control. It provides superior performance to either by allowing
a large converter bandwidth over a wide range of output loads.
In the FAN5056V85, the DAC monitors the 5 voltage identi-
fication pins, VID0-3 and VID25mV, and scales the voltage
from 1.050V to 1.825V in 25mV steps according to Table II.
Power Good (PWRGD)
The FAN5056 Power Good function is designed in accor-
dance with VRM8.5 and VRM9.0 DC-DC converter specifi-
cations and provides a continuous voltage monitor on the
VFB pin. The circuit compares the VFB signal to the VREF
voltage and outputs an active-low interrupt signal to the CPU
should either of two conditions obtain: 1) any of the linear
power supply voltages deviate more than -20% from their
nominal setpoint; 2) The switching power supply output is
more than +14% from (VVID + 80mV), or less than –14%
from (VVID – 120mV). The Power Good flag provides no
other control function to the FAN5056.
The control loop of the regulator contains two main sections:
the analog control block and the digital control block. The
analog section consists of signal conditioning amplifiers
feeding into a comparator which provides the input to the
digital control block. The signal conditioning section accepts
input from the DROOP (current feedback) and VFB (voltage
feedback) pins and sets up two controlling signal paths. The
first, the voltage control path, amplifies the difference
between the VFB signal and the reference voltage from the
DAC and presents the output to one of the summing amplifier
inputs. The second, current control path, takes the difference
between the DROOP and SW pins when the high-side
MOSFET is on, reproducing the voltage across the MOSFET
and thus the input current; it presents the resulting signal to
another input of the summing amplifier. These two signals are
then summed together. This output is then presented to a com-
parator looking at the oscillator ramp, which provides the
main PWM control signal to the digital control block.
Output Enable/Soft Start (ENABLE/SS)
The FAN5056 will accept an open collector/TTL signal for
controlling the output voltage. The low state disables the out-
put voltage. When disabled, the PWRGD output is in the low
state.
Even if an enable is not required in the circuit, this pin
should have attached a capacitor (typically 100nF) to soft-
start the switching.
The digital control block takes the analog comparator input
and the main clock signal from the oscillator to provide the
appropriate pulses to the HIDRV and LODRV output pins.
These two outputs control the external power MOSFETs.
Over-Voltage Protection
The FAN5056 continuously monitors the output voltage for
protection against over-voltage conditions. If the voltage at
the VFB pin exceeds approximately 2.5V, an OVP circuit
forces the low-side MOSFET on, over-riding all other
conditions. The OVP circuit remains active, and the low-side
MOSFET remains on, until the VFB voltage drops below
approximately 2.1V. The OVP circuit is functional even
during startup; thus, protection is provided even during
startup with a shorted high-side MOSFET.
There is an additional comparator in the analog control sec-
tion whose function is to set the point at which the FAN5056
current limit comparator disables the output drive signals to
the external power MOSFETs.
High Current Output Drivers
The FAN5056 contains two identical high current output
drivers that utilize high speed bipolar transistors in a push-
pull configuration. The drivers’ power and ground are sepa-
rated from the chip’s power and ground for switching noise
immunity. The power supply pin, VCCP, is supplied from an
external 12V source through a series resistor. The resulting
voltage is sufficient to provide the gate to source drive to the
external MOSFETs required in order to achieve a low
Oscillator
The FAN5056 oscillator section uses a fixed frequency of
operation of 300KHz.
RDS,ON
.
12
REV. 1.0.2 3/28/01
PRODUCT SPECIFICATION
FAN5056V85/FAN5056V90
Some margin should be maintained away from both Lmin and
Lmax. Adding margin by increasing L almost always adds
expense since all the variables are predetermined by system
performance except for Co, which must be increased to
increase L. Adding margin by decreasing L can be done by
purchasing capacitors with lower ESR. The FAN5056 pro-
vides significant cost savings for the newer CPU systems
that typically run at high supply current.
Design Considerations and Component
Selection
Additional information on design and component selection
may be found in Fairchild’s Application Note 57.
MOSFET Selection
This application requires N-channel Logic Level Enhance-
ment Mode Field Effect Transistors. Desired characteristics
are as follows:
FAN5056 Short Circuit Current Characteristics
The FAN5056 protects against output short circuit on the
core supply by latching off both the high-side and low-side
MOSFETs. The FAN5056 short circuit current characteristic
includes a hysteresis function that prevents the DC-DC con-
verter from oscillating in the event of a short circuit. The
short circuit limit is set with the RS resistor, as given by the
formula
• Low Static Drain-Source On-Resistance, RDS,ON < 20mΩ
(lower is better)
• Low gate drive voltage, VGS = 4.5V rated
• Power package with low Thermal Resistance
• Drain-Source voltage rating > 15V.
The on-resistance (RDS,ON) is the primary parameter for
MOSFET selection. The on-resistance determines the power
dissipation within the MOSFET and therefore significantly
affects the efficiency of the DC-DC Converter. For details
and a spreadsheet on MOSFET selection, refer to Applica-
tions Bulletin AB-8.
ISC *RDS, on
RS
=
IDetect
with IDetect ≈ 50µA, ISC the desired current limit, and RDS,on
the high-side MOSFET’s on resistance. Remember to make
the RS large enough to include the effects of initial tolerance
and temperature variation on the MOSFET’s RDS,on. Alter-
nately, use of a sense resistor in series with the source of the
MOSFET, as shown in Figure 6, eliminates this source of
inaccuracy in the current limit.
Inductor Selection
Choosing the value of the inductor is a trade-off between
allowable ripple voltage and required transient response. The
system designer can choose any value within the allowed
minimum to maximum range in order to either minimize rip-
ple or maximize transient performance. The first order equa-
tion (close approximation) for minimum inductance is:
As an example, Figure 4 shows the typical characteristic of
the DC-DC converter circuit with two FDD6690A high-side
MOSFETs (RDS = 17mΩ maximum at 25°C * 1.25 at 75°C
= 21.25mΩ each for a total of 10.6mΩ) and a 6.19KΩ RS.
(V – Vout
)
Vout
Vin
ESR
in
Lmin
=
x
x
Vripple
f
where:
Vin = Input Power Supply
Vout = Output Voltage
f = DC/DC converter switching frequency
ESR = Equivalent series resistance of all output capacitors in
parallel
Vripple = Maximum peak to peak output ripple voltage budget.
The first order equation for maximum allowed inductance is:
0
10
20
30
40
50
Output Current (A)
(V – Vout) Dm Vtb
in
2CO
=
Lmax
2
Ipp
Figure 4. FAN5056 Short Circuit Characteristic
where:
The converter exhibits a normal load regulation characteris-
tic until the voltage across the MOSFET exceeds the internal
short circuit threshold of 50µA * 6.2KΩ = 310mV, which
occurs at 310mV/10.6mΩ = 29A. [Note that this current
limit level can be as high as 310mV/6.5mΩ = 48A, if the
MOSFET has typical RDS,on rather than maximum, and is at
25°C. This is the reason for using the external sense resistor.]
At this point, the internal comparator trips and signals the
Co = The total output capacitance
Ipp = Maximum to minimum load transient current
Vtb = The output voltage tolerance budget allocated to load
transient
Dm = Maximum duty cycle for the DC/DC converter (usu-
ally 95%).
REV. 1.0.2 3/28/01
13
FAN5056V85/FAN5056V90
PRODUCT SPECIFICATION
controller to reduce the converter’s duty cycle to approxi-
mately 20%. This causes a drastic reduction in the output
voltage as the load regulation collapses into the short circuit
control mode. With a 4mΩ output short, the voltage is
reduced to 29A * 4mΩ = 116mV. The output voltage does
not return to its nominal value until the output current is
reduced to a value within the safe operating range for the
DC-DC converter.
deliver current when the high side MOSFET switches on.
Figure 5 shows 3 x 1000µF, but the exact number required
will vary with the speed and type of the processor. For the
top speed Katmai and Coppermine, the capacitors should be
rated to take 9A and 6A of ripple current respectively.
Capacitor ripple current rating is a function of temperature,
and so the manufacturer should be contacted to find out the
ripple current rating at the expected operational temperature.
For details on the design of an input filter, refer to Applica-
tions Bulletin AB-15.
Schottky Diode Selection
The application circuits of Figure 1-5 shows a Schottky
diode, D2, which is used as a free-wheeling diode to assure
that the body-diode in Q2 does not conduct when the upper
MOSFET is turning off and the lower MOSFET is turning
on. It is undesirable for this diode to conduct because its high
forward voltage drop and long reverse recovery time
degrades efficiency, and so the Schottky provides a shunt
path for the current. Since this time duration is very short,
the selection criterion for the diode is that the forward volt-
age of the Schottky at the output current should be less than
the forward voltage of the MOSFET’s body diode.
2.5µH
Vin
5V
0.1µF
1000µF, 10V
Electrolytic
Figure 5. Input Filter
Programmable Active Droop™
The FAN5056 includes Programmable Active Droop™: as
the output current increases, the output voltage drops, and
the amount of this drop is user adjustable. This is done in
order to allow maximum headroom for transient response of
the converter. The current is typically sensed by measuring
the voltage across the RDS,on of the high-side MOSFET
during its on time, as shown in Figures 1 and 2.
Output Filter Capacitors
The output bulk capacitors of a converter help determine its
output ripple voltage and its transient response. It has
already been seen in the section on selecting an inductor that
the ESR helps set the minimum inductance, and the capaci-
tance value helps set the maximum inductance. For most
converters, however, the number of capacitors required is
determined by the transient response and the output ripple
voltage, and these are determined by the ESR and not the
capacitance value. That is, in order to achieve the necessary
ESR to meet the transient and ripple requirements, the
capacitance value required is already very large.
To program the amount of droop, use the formula
14.4KΩ *Imax *Rsense
RD
VDroop *9
where Imax is the current at which the droop occurs, and
Rsense is the resistance of the current sensor, either the source
resistor or the high-side MOSFET’s on-resistance. For exam-
ple, to get 120mV of droop with a maximum output current
of 30A and a 10mΩ sense resistor, use RD = 14.4KΩ * 30A *
10mΩ/(120mV * 9) = 4KΩ. The value of the product
Imax*Rsense must be < 600mV for proper functioning of
the droop circuit. If this product is exceeded, a lower resis-
tance MOSFET must be used. Further details on use of the
Programmable Active Droop™ may be found in Applications
Bulletin AB-24.
The most commonly used choice for output bulk capacitors
is aluminum electrolytics, because of their low cost and low
ESR. The only type of aluminum capacitor used should be
those that have an ESR rated at 100kHz. Consult Application
Bulletin AB-14 for detailed information on output capacitor
selection.
The output capacitance should also include a number of
small value ceramic capacitors placed as close as possible to
the processor; 0.1µF and 0.01µF are recommended values.
Input Filter
Remote Sense
The DC-DC converter design may include an input inductor
between the system +5V supply and the converter input as
shown in Figure 5. This inductor serves to isolate the +5V
supply from the noise in the switching portion of the DC-DC
converter, and to limit the inrush current into the input capac-
itors during power up. A value of 2.5µH is recommended.
The FAN5056 offers remote sense of the output voltage to
minimize the output capacitor requirements of the converter.
It is highly recommended that the remote sense pin, Pin 8, be
tied directly to the processor power pins, so that the effects
of power plane impedance are eliminated. Further details on
use of the remote sense feature of the FAN5056 may be
found in Applications Bulletin AB-24.
It is necessary to have some low ESR aluminum electrolytic
capacitors at the input to the converter. These capacitors
14
REV. 1.0.2 3/28/01
PRODUCT SPECIFICATION
FAN5056V85/FAN5056V90
Adjusting the Linear Regulators’ Output
Voltages
PCB Layout Guidelines
• Placement of the MOSFETs relative to the FAN5056 is
critical. Place the MOSFETs such that the trace length of
the HIDRV and LODRV pins of the FAN5056 to the FET
gates is minimized. A long lead length on these pins will
cause high amounts of ringing due to the inductance of the
trace and the gate capacitance of the FET. This noise
radiates throughout the board, and, because it is switching
at such a high voltage and frequency, it is very difficult to
suppress.
Any or all of the linear regulators’ outputs may be adjusted
high to compensate for voltage drop along traces, as shown
in Figure 6.
VGATE
VOUT
R
• In general, all of the noisy switching lines should be kept
away from the quiet analog section of the FAN5056. That
is, traces that connect to pins 1, 2, 23, and 24 (HIDRV,
SW, LODRV and VCCP) should be kept far away from the
traces that connect to pins 3, 20 and 21.
VFB
10KΩ
• Place the 0.1µF decoupling capacitors as close to the
FAN5056 pins as possible. Extra lead length on these
reduces their ability to suppress noise.
• Each VCC and GND pin should have its own via to the
appropriate plane. This helps provide isolation between
pins.
Figure 6. Adjusting the Output Voltage of the
Linear Regulator
The resistor value should be chosen as
• Place the MOSFETs, inductor, and Schottky as close
together as possible for the same reasons as in the first
bullet above. Place the input bulk capacitors as close to
the drains of the high side MOSFETs as possible. In
addition, placement of a 0.1µF decoupling cap right on the
drain of each high side MOSFET helps to suppress some
of the high frequency switching noise on the input of the
DC-DC converter.
Vout
R = 2KΩ*
Vnom
For example, to get the VADJ voltage to be 1.50V instead of
1.20V, use R = 2KΩ * [(1.50/1.20) – 1] = 500Ω.
Using the FAN5056 for Vnorthbridge = 1.8V
• Place the output bulk capacitors as close to the CPU as
possible to optimize their ability to supply instantaneous
current to the load in the event of a current transient.
Additional space between the output capacitors and the
CPU will allow the parasitic resistance of the board traces
to degrade the DC-DC converter’s performance under
severe load transient conditions, causing higher voltage
deviation. For more detailed information regarding
capacitor placement, refer to Application Bulletin AB-5.
• A PC Board Layout Checklist is available from Fairchild
Applications. Ask for Application Bulletin AB-11.
Similarly, the FAN5056 can also be used to generate Vnorth-
bridge = 1.8V by utilizing the AGP regulator as shown in
Figure 6: tie the TYPEDET pin to ground, and use R = 399Ω.
Additional Information
For additional information contact your local Fairchild
Semiconductor representative, or visit us at our web site
www.fairchildsemi.com.
REV. 1.0.2 3/28/01
15
FAN5056V85/FAN5056V90
PRODUCT SPECIFICATION
Number of capacitors needed for COUT = the greater of:
Appendix
Worst-Case Formulae for the Calculation of
Cin, Cout, R5, R7 and Roffset (Circuits similar
ESR * IO
X =
VT-
+ VS+ – .024 * Vnom
to Figure 1 only)
The following formulae design the FAN5056 for worst-case
operation, including initial tolerance and temperature depen-
dence of all of the IC parameters (initial setpoint, reference
tolerance and tempco, internal droop impedance, current
sensor gain), the initial tolerance and temperature depen-
dence of the MOSFET, and the ESR of the capacitors. The
following information must be provided:
or
ESR * IO
Y =
14400 * IO * RD
18 * R5 * 1.1
VT+ – VS+
+
VS+, the value of the positive static voltage limit;
|VS-|, the absolute value of the negative static voltage limit;
VT+, the value of the positive transient voltage limit;
Example: Suppose that the static limits are +89mV/-79mV,
transient limits are 134mV, current I is 14.2A, and the nom-
inal voltage is 2.000V, using MOSFET current sensing. We
have VS+ = 0.089, |VS-| = 0.079, VT+ = |VT-| = 0.134, IO =
14.2, Vnom = 2.000, and ∆RD = 1.67. We calculate:
|VT-|, the absolute value of the negative transient voltage
limit;
2
2.000
5
2.000
5
–
14.2 *
IO, the maximum output current;
Vnom, the nominal output voltage;
Vin, the input voltage (typically 5V);
=
3.47 ⇒ 4 caps
*1000 = 15.8Ω
Cin
=
2
0.089 – .014 * 2.000 – .029
Roffset
=
0.29 + 2.000
Irms, the ripple current rating of the input capacitors, per cap
(2A for the Sanyo parts shown in this data sheet);
14.2 * 0.020 * (1 + 0.67)
=
10.5KΩ
R7 =
45 * 10-6
RD, the resistance of the current sensor (usually the MOSFET);
14400 * 14.2 * 0.020 * (1 + 0.67) * 1.1
3.48KΩ
=
R5 =
∆
RD, the tolerance of the current sensor (usually about 67%
for MOSFET sensing, including temperature); and
18 * (0.089 + 0.079 – .024 * 2.000)
0.044 * 14.2
= 3.57
X =
ESR, the ESR of the output capacitors, per cap (44mΩ for
the Sanyo parts shown in this data sheet).
0.134 + 0.089 – .024 * 2.00
0.044 * 14.2
2
= 6.14
Y
=
Vnom
Vin
Vnom
Vin
14400 * 14.2 * 0.020
IO*
–
0.134 – 0.089 +
18 * 3640 * 1.1
Cin
=
Irms
Since Y > X, we choose Y, and round up to find we need 7
capacitors for COUT
.
VS+ – .014 * Vnom – .029
* 1KΩ
Roffset
=
.029 * Vnom
A detailed explanation of this calculation may be found in
Applications Bulletin AB-24.
IO* RD * (1 + ∆RD)
R7 =
45 * 10-6
14400 * IO* RD * (1 + ∆RD) *1.1
R5 =
18 * (VS+ + VS- – .024 * Vnom
)
16
REV. 1.0.2 3/28/01
PRODUCT SPECIFICATION
FAN5056V85/FAN5056V90
Mechanical Dimensions
24 Lead SOIC
Notes:
Inches
Millimeters
Symbol
Notes
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Min.
Max.
Min.
Max.
2. "D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).
A
.093
.004
.013
.009
.599
.290
.104
.012
.020
.013
.614
.299
2.35
0.10
0.33
0.23
15.20
7.36
2.65
0.30
0.51
0.32
15.60
7.60
A1
B
3. "L" is the length of terminal for soldering to a substrate.
4. Terminal numbers are shown for reference only.
5. "C" dimension does not include solder finish thickness.
6. Symbol "N" is the maximum number of terminals.
C
D
E
5
2
2
e
.050 BSC
1.27 BSC
.394
.010
.016
.419
.020
.050
10.00
0.25
0.40
10.65
0.51
1.27
H
h
L
3
6
N
α
24
24
0°
8°
0°
8°
ccc
—
.004
—
0.10
24
13
E
H
1
12
h x 45°
D
C
A1
A
α
SEATING
PLANE
– C –
L
B
e
LEAD COPLANARITY
ccc C
REV. 1.0.2 3/28/01
17
FAN5056V85/FAN5056V90
PRODUCT SPECIFICATION
Ordering Information
Product Number
FAN5056MV85
FAN5056MV90*
Description
Package
VRM8.5
VRM9.0
24 pin SOIC
24 pin SOIC
* Contact factory for availability
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
3/28/01 0.0m 004
Stock#DS30005056V85/V90
2001 Fairchild Semiconductor Corporation
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