FAN2564UMP13X [FAIRCHILD]
300mA Low VIN LDO for Digital Applications; 300mA低压VIN LDO数字应用
| 型号： | FAN2564UMP13X |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 300mA Low VIN LDO for Digital Applications |
| 文件： | 总13页 (文件大小：577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2009
FAN2564
300mA Low VIN LDO for Digital Applications
Features
Description
The FAN2564 operates from a minimum input of 1.65V
and provides outputs as low as 1.2V. Output current is
guaranteed to 300mA, making this regulator ideal for
digital loads.
Input Voltage 1.65V to 3.6V
Guaranteed 300mA Output
High Initial Output Voltage Accuracy: ±1%
Fixed Output Voltage options from 1.2V to 2.8V
Very Low Dropout: 100mV at 300mA
45µA Quiescent Current at No Load
Low Output Noise of 100µVRMS
Inrush Current Controlled to Less Than 500mA
PSRR of 60dB at 1kHz
The unique low input voltage capability and very low
dropout make this device an ideal post regulator to a
synchronous buck regulator. In this configuration, accu-
rate low voltage regulation is provided without the ineffi-
ciencies typically related to linear regulators.
The enable pin can be used to initiate shutdown mode,
where the operating current falls to an extremely low
10nA, typically.
The FAN2564 is designed to be stable with space-
saving ceramic capacitors as small as 0402 case size.
100µs Startup Time
Stable with Ceramic Capacitors
Thermal and Short-Circuit Protection
4-bump WLCSP, 0.5mm Pitch
6-pin 2 x 2mm UMLP
The FAN2564 is available in 4-bump 0.5mm pitch wa-
fer-level chip-scale package (WLCSP) and a 6-lead 2 x
2mm ultra-thin molded leadless package (UMLP).
Applications
Post Regulator
Cell Phones and Smart Phones
WLAN, 3G, and 4G Data Cards
PMP and MP3 Players
Typical Application Circuit
Figure 1.
Typical Application Circuit
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.1
www.fairchildsemi.com
Ordering Information
Output
Temperature
Range
Packing
Method
Part Number
Package
Voltage(1)
1.2
Eco Status
FAN2564UC12X
FAN2564UC13X
FAN2564UC15X
FAN2564UC18X
FAN2564UMP12X
FAN2564UMP13X
FAN2564UMP15X
FAN2564UMP18X
Notes:
1.3
–40 to 85°C
–40 to 85°C
WLCSP-4 0.5mm Pitch
Green
Tape and Reel
Tape and Reel
1.5
1.8
1.2
1.3
6 Lead UMLP 2 x 2mm
RoHS
1.5
1.8
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
1. Other voltage options available upon request. Contact a Fairchild representative.
Block Diagram
Figure 2.
Block Diagram
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.1
www.fairchildsemi.com
2
Pin Configuration
A1
B1
A2
B2
A2
B2
A1
B1
GND
EN
EN
GND
VOUT
VIN
VIN
VOUT
Figure 3.
WLCSP Bumps Facing Down
Figure 4.
WLCSP, Bumps Facing Up
Figure 5.
UMLP, Leads Facing Down
Pin Definitions
Pin #
Name
Description
WLCSP UMLP
A1
B1
B2
6
4
3
GND
VOUT
VIN
Ground. Power and IC ground. All signals are referenced to this pin.
OUT. Connect to output voltage.
V
Input Voltage. Connect to input power source.
Enable. The device is in shutdown mode when voltage to this pin is <0.4V
and enabled when >0.95V.
A2
1
EN
5
2
NC
NC
No connect.
No connect.
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.1
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be oper-
able above the recommended operating conditions and stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Input Voltage with Respect to GND
Min.
-0.3
-0.3
-40
Max.
4.5
Units
V
VIN
Voltage on Any Other Pin with Respect to GND
Junction Temperature
VIN
V
TJ
TSTG
TL
+150
+150
+260
°C
Storage Temperature
-65
°C
Lead Temperature (Soldering 10 Seconds)
°C
Human Body Model per JESD22-A114
4
2
kV
V
Electrostatic Discharge
Protection Level
ESD
Charged Device Model per JESD22-C101
Machine Model per JESD22-A115
200
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
Parameter
Min.
1.8
0
Typ.
Max.
3.6
Units
V
Supply Voltage Range
Output Current
IOUT
CIN
300
mA
µF
Input Capacitor
1.0
4.7
COUT
TA
Output Capacitor
1.0
-40
-40
10.0
+85
µF
Operating Ambient Temperature
Operating Junction Temperature
°C
TJ
+125
°C
Thermal Properties
Symbol Parameter
Min.
Typ.
Max.
Units
WLSCP
UMLP
200
49
°C/W
°C/W
ΘJA
Junction-to-Ambient Thermal Resistance(2)
Note:
2. Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured
with four-layer 2s2p boards in accordance to JESD51- JEDEC standard. Special attention must be paid not to
exceed junction temperature TJ(max) at a given ambient temperate TA.
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.1
www.fairchildsemi.com
4
Electrical Characteristics
VIN(3)=VOUT + 0.5V or 1.8V (whichever is higher). TA=-40°C to +85°C, test circuit is Figure 1, typical values are at
TA=25°C, ILOAD=1 mA, VEN=VIN, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ. Max. Units
Power Supplies
VIN
Input Voltage Range
1.65
3.60
75
V
ILOAD=0mA
45
μA
IGND
Ground Current
ILOAD=300mA
140
200
μA
μA
ISD
Shutdown Supply Current
VIN=3.6V, EN=GND
0.01
1.00
Enable High-level Input Voltage
Enable Low-level Input Voltage
0.95
V(EN)
V
0.4
4.0
EN=GND
0
I(EN)
Enable Input Leakage Current
EN=VIN=3.6V
2.5
μA
Regulation
IOUT
Minimum Output Current
Maximum Output Current
Dropout Voltage(4)
0
mA
mA
mV
IOUT
300
VDO
ILOAD=300mA
100
160
1.0
1.8V
Over Full VIN,
OUT, at Room
Temperature
-1.0
-1.5
I
1.2V, 1.3V, 1.5V
1.5
∆VOUT
Output Voltage Accuracy
%
Over Full VIN,
1.2V, 1.3V,
1.5V, 1.8V
I
OUT, Tempera-
-2.5
2.5
ture Range
VIN=VOUT(NOM) + 0.5V to 3.6V,
OUT=1mA
∆VOUTline Line Regulation
∆VOUTload Load Regulation
0.03
0.50
%/V
I
IOUT=1mA to 300mA
10
60
µV/mA
mA
ISCP
ISU
Short-circuit Current Limit
500
500
900
900
Start-up Peak Current
Turn-on Time(5)
EN Transition, LOW to HIGH
EN Transition, LOW to HIGH
mA
tON
100
µs
Startup Overshoot(5)
IOUT=1mA
0
%
°C
Rising Temperature
Hysteresis
+160
+30
60
TSD
Thermal Shutdown
°C
PSRR
en
Power Supply Rejection Ratio(5) f=1kHz
Output Noise Voltage(5)
10Hz to 100kHz
dB
100
µVRMS
Timing Characteristics
Peak
∆VOUTline
Line Transient Response(5)
Load Transient Response(5)
600mV, tRISE=tFALL=30µs
±6
mV
mV
Peak
∆VOUTload
1mA-300mA-1mA, tRISE=tFALL=1µs
±50
Note:
3. VIN voltage tolerance +/- 5%.
4. Dropout voltage is the minimum input to output differential voltage needed to maintain VOUT to within 5% of
nominal value. This parameter is only specified for output voltages greater than or equal to 1.8V.
5. This electrical specification is guaranteed by design.
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.1
www.fairchildsemi.com
5
Typical Performance Characteristics
Unless otherwise noted, VIN=VOUT(Nominal)+0.5V or 1.8V (whichever is greater), VOUT=1.2V,CIN=1µF, COUT=4.7µF,
and TA=25°C.
Figure 6.
Output Voltage Change
vs. Temperature
Figure 7.
Output Voltage vs. Minimum Input
Voltage
Figure 8.
Dropout Voltage
Figure 9.
Ground Current vs. Load Current
Figure 10. Ground Current vs. VIN, ILOAD=1mA
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.1
www.fairchildsemi.com
6
Typical Performance Characteristics
Unless otherwise noted, VIN=VOUT(Nominal)+0.5V or 1.8V (whichever is greater), VOUT=1.2V,CIN=1µF, COUT=4.7µF,
and TA=25°C.
Figure 11. Load Transient, VOUT 1.2V
Figure 12. Load Transient, VOUT 2.8V
=
=
Figure 13. Line Transient, ILOAD 1mA
=
Figure 14. Line Transient, ILOAD 300mA
=
Figure 15. Enable Characteristics
Figure 16. Short Circuit Current
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.1
www.fairchildsemi.com
7
Typical Performance Characteristics
Unless otherwise noted, VIN=VOUT(Nominal)+0.5V or 1.8V (whichever is greater), VOUT=1.2V,CIN=1µF, COUT=4.7µF,
and TA=25°C.
Figure 17. Inrush Current
Figure 19. Power Supply Rejection Ratio
Figure 21. Noise Density
Figure 18. Inrush Current
Figure 20. Power Supply Rejection Ratio
Figure 22. Noise Density
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.1
www.fairchildsemi.com
8
Application Information
Enable and Soft Start
Thermal Considerations
For best performance, the die temperature and the
power dissipated should be kept at moderate values.
The maximum power dissipated can be evaluated based
on the following relationship:
A 1.4 MΩ pull-down resistor ensures the EN pin to be in
LOW state when it is floating. The chip is in shut-down
mode when EN pin is LOW.
To enable the chip, the EN pin needs to be raised higher
than 0.95V. The output pin starts to charge up to the
final voltage. On-chip soft-start circuitry limits the peak
inrush current through VIN pin to less than the specified
typical value of 500mA, regardless of COUT value and
load conditions.
T
− TA
⎧
⎨
⎩
⎫
⎬
⎭
J(max)
PD(max)
=
(1)
ΘJA
where TJ(max) is the maximum allowable junction tem-
perature of the die and TA is the ambient operating tem-
perature. θJA is dependent on the surrounding PCB lay-
out and can be improved by providing a heat sink of sur-
rounding copper ground.
The startup time increases as VOUT, COUT, and load in-
creases, but meets the specified 100µs under the worst
load and VOUT conditions.
The addition of backside copper with through-holes, stiff-
eners, and other enhancements can also aid in reducing
θJA. The heat contributed by the dissipation of other de-
vices located nearby must be included in design consid-
erations.
Short-Circuit and Thermal Protection
The output current is short-circuit protected. When a
short-circuit fault occurs, the output current is automati-
cally limited and VOUT drops, depending on the actual
short-circuit resistance.
Capacitors Selection
Short-circuit fault or output overload may cause the die
temperature to increase and exceed maximum ratings
due to power dissipation. In such cases, depending
upon the ambient temperature; VIN, load current, and the
junction-to-air thermal resistance (θJA) of the die; the
device may enter thermal shutdown.
The FAN2564 is stable with a wide range of capacitor
values and sizes.
For loop stability, a 1µF input capacitor or bigger is rec-
ommended. Tolerance, temperature, and voltage coeffi-
cients of the capacitor must be considered to ensure
effective capacitance stays around 1µF or above. There
is no special requirement on its ESR value.
When the die temperature exceeds the shutdown limit
temperature, the onboard thermal protection disables
the output until the temperature drops below its hyteresis
value, at which point the output is re-enabled and a new
soft-start sequence occurs as described above.
An output capacitor with an effective capacitance be-
tween 1µF and 10µF is required for loop stability. The
ESR value should be within 5 to 100mΩ. 2.2µF or 4.7µF
ceramic capacitors are recommended to ensure stability
over the full temperature, input, and output voltage
range of operation, such as those listed in Table 1.
Table 1. Recommended Capacitors
Capacitance
Size
Vendor
Part Number
0603
0603
0402
0603
0402
MURATA
MURATA
MURATA
MURATA
MURATA
GRM188R71C105KA120
GRM188R61A225KF340
GRM155R60J225ME15
GRM188C80G475KE19
GRM155R60G475M
1μF
2.2μF
2.2μF
4.7μF
4.7μF
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.1
www.fairchildsemi.com
9
Layout Considerations
CIN and COUT should be placed close to the device for
optimal transient response and device behavior. A dedi-
cated ground plane is recommended for proper GND
connection.
Figure 25. Bottom Layer
Figure 23. Assembly Diagram
Figure 24. Top Layer
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.1
www.fairchildsemi.com
10
Physical Dimensions
E
BALL A1
INDEX AREA
E
A
0.50
0.50
B
A1
0.03 C
2X
(Ø0.25)
Cu PAD
(Ø0.35)
SOLDER MASK
OPENING
D
0.03 C
2X
TOP VIEW
RECOMMENDED LAND PATTERN (NSMD)
0.06 C
0.330±0.013
0.250±0.025
0.618
0.542
0.05 C
D
C
SEATING PLANE
SIDE VIEWS
NOTES:
(X)+/-.018
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASMEY14.5M, 1994.
D. DATUM C, THE SEATING PLANE IS DEFINED
BY THE SPHERICAL CROWNS OF THE BALLS.
E. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
0.005
12 X Ø0.315 +/- .025
C A B
0.50
E
B
0.50
A
1
2
(Y)+/-.018
F. DRAWING FILENAME: UC004ABrev1
BOTTOM VIEW
Figure 26. 4-Bump, Wafer-Level Chip-Scale Package (WLCSP), 0.5mm Pitch
Product Specific Dimensions
Product
D
E
X
Y
FAN2564UCX
1.41 +/-0.030
0.93 +/-0.030
0.215
0.455
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.1
www.fairchildsemi.com
11
Physical Dimensions
0.10 C
2.0
A
2X
B
1.60
1.50
2.0
6
4
0.50
0.10 C
2X
1.10
1.40 2.40
PIN1
IDENT
TOP VIEW
1
3
0.30
0.55 MAX
0.65
0.10
C
(0.15)
C
RECOMMENDED LAND PATTERN
0.08 C
0.05
0.00
SEATING
PLANE
SIDE VIEW
NOTES:
1.50
MAX
A. OUTLINE BASED ON JEDEC REGISTRATION
MO-229, VARIATION VCCC.
PIN1
IDENT
1
3
B. DIMENSIONS ARE IN MILLIMETERS.
1.10
MAX
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
0.35
0.25
6x
D. DRAWING FILENAME: MKT-UMLP06Crev1
6
4
0.35
0.25
6x
0.65
1.30
0.10
0.05
C
C
A B
BOTTOM VIEW
Figure 27. 6-Pin, Ultrathin Molded Leadless Package (UMLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.1
www.fairchildsemi.com
12
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.1
www.fairchildsemi.com
13
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