F74ALVC16245 [FAIRCHILD]
Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs; 低电压16位双向收发器，具有3.6V容限输入和输出
| 型号： | F74ALVC16245 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs |
| 文件： | 总7页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2001
Revised May 2005
74ALVC16245
Low Voltage 16-Bit Bidirectional Transceiver
with 3.6V Tolerant Inputs and Outputs
General Description
Features
■ 1.65V–3.6V VCC supply operation
The ALVC16245 contains sixteen non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for bus
oriented applications. The device is byte controlled. Each
byte has separate 3-STATE control inputs which can be
shorted together for full 16-bit operation. The T/R inputs
determine the direction of data flow through the device.
The OE inputs disable both the A and B ports by placing
them in a high impedance state.
■ 3.6V tolerant inputs and outputs
■ tPD
3.0 ns max for 3.0V to 3.6V VCC
3.5 ns max for 2.3V to 2.7V VCC
6.0 ns max for 1.65V to 1.95V VCC
■ Power-down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ Uses patented noise/EMI reduction circuitry
■ Latchup conforms to JEDEC JED78
■ ESD performance:
The 74ALVC16245 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74ALVC16245 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Human body model 2000V
Machine model 200V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
through a pull-up resistor; the minimum
CC
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
Package Number
Package Description
74ALVC16245G
(Note 2)(Note 3)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74ALVC16245MTD
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
DS500678
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Connection Diagrams
Pin Descriptions
Pin Assignment of TSSOP
Pin Names
Description
OEn
Output Enable Input (Active LOW)
Transmit/Receive Input
T/Rn
A0–A15
B0–B15
NC
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
B0
B2
NC
B1
T/R1
NC
OE1
NC
NC
A1
A0
A2
B4
B3
VCC
VCC
A3
A4
B6
B5
GND GND
GND GND
GND GND
A5
A6
B8
B7
A7
A8
B10
B12
B14
B9
A9
A10
A12
A14
G
H
B11
B13
VCC
NC
VCC
NC
A11
A13
J
B15
NC
T/R2
OE2
NC
A15
Truth Tables
Pin Assignment for FBGA
Inputs
Outputs
OE1
T/R1
L
L
L
H
X
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
HIGH Z State on A0–A7, B0–B7
H
Inputs
Outputs
OE2
T/R2
L
L
L
H
X
Bus B8–B15 Data to Bus A8–A15
Bus A8–A15 Data to Bus B8–B15
HIGH Z State on A8–A15, B8–B15
H
H
L
HIGH Voltage Level
LOW Voltage Level
(Top Thru View)
X
Z
Immaterial (HIGH or LOW, inputs and I/O’s may not float)
High Impedance
Logic Diagram
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2
Absolute Maximum Ratings(Note 4)
Recommended Operating
Conditions (Note 6)
Supply Voltage (VCC
)
0.5V to 4.6V
0.5V to 4.6V
DC Input Voltage (VI)
Power Supply
Output Voltage (VO) (Note 5)
0.5V to VCC 0.5V
Operating
1.65V to 3.6V
0V to VCC
DC Input Diode Current (IIK
VI 0V
)
Input Voltage
50 mA
50 mA
50 mA
Output Voltage (VO)
0V to VCC
DC Output Diode Current (IOK
VO 0V
)
Free Air Operating Temperature (TA)
Minimum Input Edge Rate ( t/ V)
VIN 0.8V to 2.0V, VCC 3.0V
40 C to 85 C
DC Output Source/Sink Current
(IOH/IOL
10 ns/V
Note 4: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
)
DC VCC or GND Current per
Supply Pin (ICC or GND)
100 mA
Storage Temperature Range (TSTG
)
65 C to 150 C
Note 5: I Absolute Maximum Rating must be observed.
O
Note 6: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
V
CC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
V
V
V
HIGH Level Input Voltage
1.65 - 1.95 0.65 x V
IH
CC
2.3 - 2.7
2.7 - 3.6
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
1.65 - 3.6
1.65
1.7
2.0
V
LOW Level Input Voltage
HIGH Level Output Voltage
0.35 x V
0.7
IL
CC
V
V
0.8
I
I
I
I
100
A
V
- 0.2
OH
OH
OH
OH
OH
CC
4 mA
6 mA
1.2
2.0
1.7
2.2
2.4
2
2.3
12 mA
2.3
2.7
3.0
I
I
I
I
I
24 mA
3.0
OH
OL
OL
OL
OL
V
LOW Level Output Voltage
100
A
1.65 - 3.6
1.65
0.2
0.45
0.4
0.7
0.4
0.55
5.0
10
OL
4 mA
6 mA
2.3
V
12 mA
2.3
2.7
I
24 mA
3.0
OL
I
I
I
Input Leakage Current
3-STATE Output Leakage
Quiescent Supply Current
0
0
V
V
3.6V
3.6V
3.6
A
A
A
A
I
I
3.6
OZ
CC
O
V
V
or GND, I
O
0
3.6
40
I
CC
I
Increase in I per Input
V
V
CC
0.6V
3 - 3.6
750
CC
CC
IH
3
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AC Electrical Characteristics
T
40 C to 85 C, R
500
A
L
C
50 pF
C
30 pF
L
L
Symbol
Parameter
Units
V
3.3V 0.3V
V
2.7V
Max
V
2.5V 0.2V
V
1.8V 0.15V
CC
CC
CC
CC
Min
1.3
1.3
1.3
Max
3
Min
1.5
1.5
1.5
Min
1.0
1.0
1.0
Max
3.0
Min
1.5
1.5
1.5
Max
6.0
t
, t
Propagation Delay
Output Enable Time
Output Disable Time
3.5
5.4
4.7
ns
ns
ns
PHL PLH
t
, t
4.3
4.2
4.9
4.2
9.3
7.6
PZL PZH
t
, t
PLZ PHZ
Capacitance
T
25 C
A
Symbol
Parameter
Conditions
Units
V
Typical
CC
3.3
3.3
3.3
2.5
C
Input Capacitance
Input, Output Capacitance
Power Dissipation Capacitance
V
V
f
0V or V
CC
6
7
pF
pF
IN
I
C
C
0V or V
CC
IO
PD
O
Outputs Enabled
10 MHz, C
50 pF
20
20
L
pF
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4
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
SWITCH
Open
VL
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f 1MHz; tr tf 2ns; ZO 50
)
VCC
Symbol
3.3V 0.3V
1.5V
2.7V
1.5V
2.5 0.2V
VCC/2
1.8V 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
1.5V
VCC/2
VCC/2
VOL 0.3V
VOH 0.3V
6V
VOL 0.3V
VOH 0.3V
6V
VOL 0.15V
VOH 0.15V
VCC*2
VOL 0.15V
VOH 0.15V
VCC*2
VY
VL
FIGURE 2. Waveform for Inverting and Non-inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
5
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Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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