DM74AS74SJ [FAIRCHILD]
D Flip-Flop, AS Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, TTL, PDSO14, 5.30 MM, EIAJ TYPE2, SOP-14;
| 型号： | DM74AS74SJ |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | D Flip-Flop, AS Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, TTL, PDSO14, 5.30 MM, EIAJ TYPE2, SOP-14 触发器 |
| 文件： | 总7页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1984
Revised March 2000
DM74AS74
Dual D-Type Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Description
The AS74 is a dual edge-triggered flip-flops. Each flip-flop
has individual D, clock, clear and preset inputs, and also
complementary Q and Q outputs.
Features
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full tempera-
ture and VCC range
Information at input D is transferred to the Q output on the
positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. When the clock input is at either the HIGH or LOW
level, the D input signal has no effect.
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
■ Functionally and pin-for-pin compatible with Schottky
and LS TTL counterpart
■ Improved AC performance over S74 at approximately
half the power
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of LOW level sig-
nal.
Ordering Code:
Order Number Package Number
Package Description
DM74AS74M
DM74AS74SJX
DM74AS74N
M14A
M14D
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
PR CLR CLK
D
X
X
X
H
L
Q
H
L
Q
L
L
H
L
H
L
X
X
X
↑
H
L
H (Note 1) H (Note 1)
H
H
H
H
H
L
L
H
↑
H
H
L
X
Q0
Q0
L = LOW State
H = HIGH State
X = Don't Care
↑ = Positive Edge Transition
= Previous Condition of Q
Q
0
Note 1: This condition is nonstable; it will not persist when preset and clear
inputs return to their inactive (HIGH) level. The output levels in this condi-
tion are not guaranteed to meet the V
specification.
OH
© 2000 Fairchild Semiconductor Corporation
DS006282
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Logic Diagram
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2
Absolute Maximum Ratings(Note 2)
Supply Voltage
Input Voltage
7V
7V
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Operating Free Air Temperature Range
Storage Temperature Range
Typical θJA
0°C to +70°C
−65°C to +150°C
N Package
76.0°C/W
M Package
107.0°C/W
Recommended Operating Conditions
Symbol
Parameter
Min
4.5
2
Nom
Max
Units
V
VCC
VIH
VIL
Supply Voltage
5
5.5
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency
V
0.8
−2
V
IOH
IOL
mA
mA
MHz
ns
20
fCLK
0
4
105
tW(CLK)
Width of Clock Pulse
HIGH
LOW
5.5
4
ns
tW
Pulse Width Preset & Clear LOW
Data Setup Time (Note 3)
ns
tSU
tSU
tH
4.5↑
2↑
0↑
0
ns
PRE or CLR Setup-Time (Note 3)
Data Hold Time (Note 3)
ns
ns
TA
Free Air Operating Temperature
70
°C
Note 3: The (↑) arrow indicates the positive edge of the Clock is used for reference.
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, T = 25°C.
A
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
V
Input Clamp Voltage
HIGH Level
V
V
= 4.5V, I = −18 mA
−1.2
V
V
IK
CC
I
= 4.5V to 5.5V,
OH
CC
V
− 2
CC
Output Voltage
I
= −2 mA
OH
V
LOW Level
V
= 4.5V, V = Max,
OL
CC IH
0.35
0.5
V
Output Voltage
I
= 20 mA
OL
I
I
Input Current @ Max Input Voltage
HIGH Level Input Current
V
V
V
V
V
V
V
= 5.5V, V = 7V
0.1
20
mA
µA
I
CC
CC
IH
= 5.5V,
Clock, D
IH
= 2.7V
Preset, Clear
Clock, D
40
µA
IH
I
LOW Level Input Current
= 5.5V,
−0.5
−1.8
−112
16
mA
mA
mA
mA
IL
CC
= 0.4V
Preset, Clear
IL
I
I
Output Drive Current
Supply Current
= 5.5V, V = 2.25V
−30
O
CC
CC
O
= 5.5V
10.5
CC
3
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Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
= 4.5V to 5.5V
CC
From
To
Min
Max
Units
f
t
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
V
105
MHz
MAX
R
= 500Ω
= 50 pF
Preset
Q or
PLH
PHL
PLH
PHL
L
L
3
7.5
10.5
8
ns
ns
ns
ns
or Clear
C
Q
t
t
t
Propagation Delay Time
Preset
Q or
3.5
3.5
4.5
HIGH-to-LOW Level Output
or Clear
Q
Propagation Delay Time
Clock
Q or
LOW-to-HIGH Level Output
Q
Propagation Delay Time
Clock
Q or
9
HIGH-to-LOW Level Output
Q
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4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M14A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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