CD4514BCWMX [FAIRCHILD]
4-To-16-Line Demultiplexer ; 4-至16行解复用器\n
| 型号： | CD4514BCWMX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 4-To-16-Line Demultiplexer
|
| 文件： | 总8页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised August 2000
CD4514BC• CD4515BC
4-Bit Latched/4-to-16 Line Decoders
General Description
Features
The CD4514BC and CD4515BC are 4-to-16 line decoders
with latched inputs implemented with complementary MOS
(CMOS) circuits constructed with N- and P-channel
enhancement mode transistors. These circuits are prima-
rily used in decoding applications where low power dissipa-
tion and/or high noise immunity is required.
■ Wide supply voltage range: 3.0V to 15V
■ High noise immunity: 0.45 VDD (typ.)
■ Low power TTL: fan out of 2
compatibility: driving 74L
■ Low quiescent power dissipation:
0.025 µW/package @ 5.0 VDC
The CD4514BC (output active high option) presents a logi-
cal “1” at the selected output, whereas the CD4515BC pre-
sents a logical “0” at the selected output. The input latches
are R–S type flip-flops, which hold the last input data pre-
sented prior to the strobe transition from “1” to “0”. This
input data is decoded and the corresponding output is acti-
vated. An output inhibit line is also available.
■ Single supply operation
■ Input impedance = 1012Ω typically
■ Plug-in replacement for MC14514, MC14515
Ordering Code:
Order Number Package Number
Package Diagram
CD4514BCWM
CD4514BCN
CD4515BCWM
CD4515BCN
M24B
N24A
M24B
N24A
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Top View
© 2000 Fairchild Semiconductor Corporation
DS005994
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Truth Table
Decode Truth Table (Strobe = 1)
Data Inputs
Selected Output
Inhibit
D
C
B
A
CD4514 = Logic “1”
CD4515 = Logic “0”
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
All Outputs = 0, CD4514
All Outputs = 1, CD4515
X = Don’t Care
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions (Note 2)
DC Supply Voltage (VDD
Input Voltage (VIN
)
−0.5V to +18V
−0.5V to VDD + 0.5V
−65°C to +150°C
DC Supply Voltage (VDD
Input Voltage (VIN
)
3V to 15V
0V to VDD
)
)
Storage Temperature Range (TS)
Power Dissipation (PD)
Dual-In-Line
Operating Temperature Range (TA)
CD4514BC, CD4515BC
−40°C to +85°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The tables of “Recommended Operating Conditions”
and “Electrical Characteristics” provide conditions for actual device opera-
tion.
700 mW
500 mW
Small Outline
Lead Temperature (TL)
(Soldering, 10 seconds)
260°C
Note 2: VSS = 0V unless otherwise specified.
DC Electrical Characteristics (Note 2)
CD4514BC, CD4515BC
−40°C
+25°C
Typ
+85°C
Symbol
Parameter
Conditions
Units
Min
Max
Min
Max
20
Min
Max
IDD
Quiescent Device
V
V
V
V
DD = 5V, VIN = VDD or V SS
DD = 10V, VIN = VDD or V SS
DD = 15V, VIN = VDD or V SS
20
40
80
0.005
0.010
0.015
150
300
600
µA
µA
µA
Current
40
80
VOL
LOW Level
IL = 0V, VIH = VDD,
Output Voltage
|IO| < 1 µA
V
V
V
V
DD = 5V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
DD = 10V
DD = 15V
VOH
HIGH Level
IL = 0V, VIH = VDD,
Output Voltage
|IO| < 1 µA
V
V
V
DD = 5V
4.95
9.95
4.95
9.95
5.0
4.95
9.95
V
V
V
DD = 10V
DD = 15V
10.0
14.95
14.95 15.0
14.95
VIL
LOW Level
|IO| < 1 µA
Input Voltage
VDD = 5V, VO = 0.5V or 4.5V
VDD = 10V, VO = 1.0V or 9.0V
VDD = 15V, VO = 1.5V or 13.5V
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
VIH
HIGH Level
|IO| < 1 µA
Input Voltage
V
V
V
V
V
V
V
V
V
V
V
DD = 5V, VO = 0.5V or 4.5V
DD = 10V, VO = 1.0V or 9.0V
DD = 15V, VO = 1.5V or 13.5V
DD = 5V, VO = 0.4V
3.5
7.0
3.5
7.0
2.75
5.50
8.25
0.88
2.25
8.8
3.5
7.0
V
V
11.0
0.52
1.3
11.0
0.44
1.1
11.0
0.36
0.90
2.4
V
IOL
IOH
IIN
LOW Level Output
Current (Note 3)
mA
mA
mA
mA
mA
mA
µA
µA
DD = 10V, VO = 0.5V
DD = 15V, VO = 1.5V
DD = 5V, VO = 4.6V
3.6
3.0
HIGH Level Output
Current (Note 3)
−0.52
−1.3
−3.6
−0.44 −0.88
−1.1 −2.25
−0.36
−0.90
−2.4
DD = 10V, VO = 9.5V
DD = 15V, VO = 13.5V
DD = 15V, VIN = 0V
−3.0
−8.8
−5
Input Current
−0.3
−10
−0.3
−1.0
−5
DD = 15V, VIN = 15V
0.3
10
0.3
1.0
Note 3: IOH and IOL are tested one output at a time.
3
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AC Electrical Characteristics (Note 4)
All types CL = 50 pF, TA = 25°C, tr = tf = 20 ns unless otherwise specified
Symbol
tTHL, tTLH
Parameter
Transition Times
Conditions
Min
Typ
100
50
Max
200
100
80
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
40
tPLH, tPHL
tPLH, tPHL
tSU
Propagation Delay Times
550
225
150
400
150
100
125
50
1100
450
300
800
300
200
250
100
75
Inhibit Propagation
Delay Times
Setup Time
38
tWH
Strobe Pulse Width
175
50
350
100
75
38
CPD
CIN
Power Dissipation Capacitance
Input Capacitance
Per Package (Note 5)
Any Input (Note 6)
150
5
7.5
Note 4: AC Parameters are guaranteed by DC correlated testing.
Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note,
AN-90.
Note 6: Capacitance is guaranteed by periodic testing.
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4
AC Test Circuit and Switching Time Waveforms
FIGURE 1.
5
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Applications
Two CD4512 8-channel data selectors are used here with
the CD4514B 4-bit latch/decoder to effect a complex data
routing system. A total of 16 inputs from data registers are
selected and transferred via a 3-STATE data bus to a data
distributor for rearrangement and entry into 16 output regis-
ters. In this way sequential data can be re-routed or inter-
mixed according to patterns determined by data select and
distribution inputs.
times faster than the shift frequency of the input registers,
the most significant bit (MSB) from each register could be
selected for transfer to the data bus. Therefore, all of the
most significant bits from all of the registers can be trans-
ferred to the data bus before the next most significant bit is
presented for transfer by the input registers.
Information from the 3-STATE bus is redistributed by the
CD4514B 4-bit latch/decoder. Using the 4-bit address,
INA–IND, the information on the inhibit line can be trans-
ferred to the addressed output line to the desired output
registers, A–P. This distribution of data bits to the output
registers can be made in many complex patterns. For
example, all of the most significant bits from the input regis-
ters can be routed into output register A, all of the next
most significant bits into register B, etc. In this way horizon-
tal, vertical, or other methods of data slicing can be imple-
mented.
Data is placed into the routing scheme via the 8 inputs on
both CD4512 data selectors. One register is assigned to
each input. The signals on A0, A1 and A2 choose 1-of-8
inputs for transfer out to the 3-STATE data bus. A fourth
signal, labelled Dis, disables one of the CD4512 selectors,
assuring transfer of data from only one register.
In addition to a choice of input registers, 1–16, the rate of
transfer of the sequential information can also be varied.
That is, if the CD4512 were addressed at a rate that is 8
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6
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide
Package Number N24A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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