CD4011BCM [FAIRCHILD]
Quad 2-Input NOR Buffered B Series Gate . Quad 2-Input NAND Buffered B Series Gate; 四2输入或非缓冲B系列门。四2输入与非缓冲B系列门
| 型号： | CD4011BCM |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad 2-Input NOR Buffered B Series Gate . Quad 2-Input NAND Buffered B Series Gate |
| 文件： | 总9页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised March 2002
CD4001BC/CD4011BC
Quad 2-Input NOR Buffered B Series Gate •
Quad 2-Input NAND Buffered B Series Gate
General Description
Features
■ Low power TTL:
The CD4001BC and CD4011BC quad gates are monolithic
complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement mode tran-
sistors. They have equal source and sink current
capabilities and conform to standard B series output drive.
The devices also have buffered outputs which improve
transfer characteristics by providing very high gain.
Fan out of 2 driving 74L compatibility: or 1 driving 74LS
■ 5V–10V–15V parametric ratings
■ Symmetrical output characteristics
■ Maximum input leakage 1 µA at 15V over full
temperature range
All inputs are protected against static discharge with diodes
to VDD and VSS
.
Ordering Code:
Order Number
CD4001BCM
CD4001BCSJ
CD4001BCN
CD4011BCM
CD4011BCN
Package Number
Package Description
M14A
M14D
N14A
M14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC and SOP
CD4001BC
Pin Assignments for DIP and SOIC
CD4011BC
Top View
Top View
© 2002 Fairchild Semiconductor Corporation
DS005939
www.fairchildsemi.com
Schematic Diagrams
CD4001BC
1
/
4 of device shown
J = A + B
Logical “1” = HIGH
Logical “0” = LOW
All inputs protected by standard
CMOS protection circuit.
CD4011BC
1
/
4 of device shown
J = A • B
Logical “1” = HIGH
Logical “0” = LOW
All inputs protected by standard
CMOS protection circuit.
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2
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Voltage at any Pin
Power Dissipation (PD)
Dual-In-Line
−0.5V to VDD +0.5V
Operating Range (VDD
)
3 VDC to 15 VDC
Operating Temperature Range
CD4001BC, CD4011BC
700 mW
500 mW
−55°C to +125°C
Small Outline
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The Electrical Characteristics tables provide conditions
for actual device operation.
V
DD Range
−0.5 VDC to +18 VDC
−65°C to +150°C
Storage Temperature (TS)
Lead Temperature (TL)
(Soldering, 10 seconds)
Note 2: All voltages measured with respect to VSS unless otherwise speci-
260°C
fied.
DC Electrical Characteristics (Note 2)
−55°C
+25°C
Typ
0.004
0.005
0.006
0
+125°C
Symbol
IDD
Parameter
Conditions
Units
Min
Max
Min
Max
0.25
0.50
1.0
Min
Max
Quiescent Device
Current
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD = 5V, VIN = VDD or VSS
DD = 10V, VIN = VDD or VSS
DD = 15V, VIN = VDD or VSS
DD = 5V
0.25
0.5
7.5
15
µA
1.0
30
VOL
VOH
VIL
LOW Level
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
Output Voltage
DD = 10V
DD = 15V
DD = 5V
|IO| < 1 µA
0
V
V
0
HIGH Level
4.95
9.95
4.95
9.95
5
4.95
9.95
Output Voltage
DD = 10V
DD = 15V
|IO| < 1 µA
10
14.95
14.95
15
14.95
LOW Level
DD = 5V, VO = 4.5V
DD = 10V, VO = 9.0V
DD = 15V, VO = 13.5V
DD = 5V, VO = 0.5V
DD = 10V, VO = 1.0V
DD = 15V, VO = 1.5V
DD = 5V, VO = 0.4V
DD = 10V, VO = 0.5V
DD = 15V, VO = 1.5V
DD = 5V, VO = 4.6V
DD = 10V, VO = 9.5V
DD = 15V, VO = 13.5V
DD = 15V, VIN = 0V
DD = 15V, VIN = 15V
1.5
3.0
4.0
2
1.5
3.0
4.0
1.5
3.0
4.0
Input Voltage
4
V
6
VIH
IOL
IOH
IIN
HIGH Level
3.5
7.0
3.5
7.0
3
3.5
7.0
Input Voltage
6
V
11.0
0.64
1.6
11.0
0.51
1.3
9
11.0
0.36
0.9
LOW Level Output
Current
0.88
2.25
8.8
−0.88
−2.25
−8.8
mA
(Note 3)
4.2
3.4
2.4
HIGH Level Output
Current
−0.64
−1.6
−4.2
−0.51
−1.3
−3.4
−0.36
−0.9
−2.4
mA
(Note 3)
−5
Input Current
−0.10
−10
−0.10
−1.0
µA
−5
0.1
10
0.10
1.0
Note 3: IOL and IOH are tested one output at a time.
AC Electrical Characteristics (Note 4)
CD4001BC: TA = 25°C, Input tr; tf = 20 ns. CL = 50 pF, RL = 200k. Typical temperature coefficient is 0.3%/°C.
Symbol
Parameter
Conditions
Typ
120
50
35
110
50
35
90
50
40
5
Max
250
100
70
Units
tPHL
Propagation Delay Time,
V
V
V
V
V
V
V
V
V
DD = 5V
HIGH-to-LOW Level
DD = 10V
DD = 15V
DD = 5V
ns
ns
ns
tPLH
Propagation Delay Time,
LOW-to-HIGH Level
250
100
70
DD = 10V
DD = 15V
DD = 5V
tTHL, tTLH
Transition Time
200
100
80
DD = 10V
DD = 15V
CIN
Average Input Capacitance
Power Dissipation Capacity
Any Input
Any Gate
7.5
pF
pF
CPD
14
Note 4: AC Parameters are guaranteed by DC correlated testing.
3
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AC Electrical Characteristics (Note 5)
CD4011BC: T = 25°C, Input tr; tf = 20 ns. CL = 50 pF, RL = 200k. Typical Temperature Coefficient is 0.3%/°C.
A
Symbol
Parameter
Propagation Delay,
Conditions
Typ
120
50
35
85
40
30
90
50
40
5
Max
250
100
70
Units
tPHL
V
V
V
V
V
V
V
V
V
DD = 5V
HIGH-to-LOW Level
DD = 10V
DD = 15V
DD = 5V
ns
tPLH
Propagation Delay,
LOW-to-HIGH Level
250
100
70
DD = 10V
DD = 15V
DD = 5V
ns
ns
tTHL, tTLH Transition Time
200
100
80
DD = 10V
DD = 15V
CIN
Average Input Capacitance
Power Dissipation Capacity
Any Input
Any Gate
7.5
pF
pF
CPD
14
Note 5: AC Parameters are guaranteed by DC correlated testing.
Typical Performance Characteristics
Typical
Transfer Characteristics
Typical
Transfer Characteristics
Typical
Transfer Characteristics
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4
Typical Performance Characteristics (Continued)
Typical Transfer Characteristics
5
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Typical Performance Characteristics (Continued)
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6
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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