AN-6861 [FAIRCHILD]

a Flyback Power Supply with Peak Load Current Profile; 反激式电源供应器与峰值负载电流档案


型号：	AN-6861
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	a Flyback Power Supply with Peak Load Current Profile 反激式电源供应器与峰值负载电流档案
文件：	总12页 (文件大小：462K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

www.fairchildsemi.com

AN-6861

Applying FAN6861 to a Flyback Power Supply with Peak

Load Current Profile

The frequency-hopping function reduces electro-magnetic

interference (EMI) of a power supply by spreading the

energy over a wider frequency range. The constant power

1. Introduction

Highly integrated PWM controller, FAN6861, is optimized

limit function minimizes the component stress in abnormal

for applications with motor load, such as printers and

condition and helps to optimize the power stage. Protection

scanners, that inherently impose some kind of overload

functions; such as OCP, OLP, OVP, and OTP are fully

condition on the power supply during acceleration mode.

integrated into FAN6861, which improves the SMPS

The two-level OCP function allows the SMPS to stably

deliver peak power during the motor acceleration without

reliability without increasing system cost.

causing premature shutdown, while protecting the SMPS

from overload condition.

This application note presents design considerations to apply

FAN6861 to a flyback power supply with peak load current

profile. It covers designing the transformer, selecting the

components, and closing the feedback loop. Figure 1 shows

a typical application circuit using FAN6861.

The green-mode and burst-mode functions with a low

operating current (2.2mA maximum in green mode)

maximize the light-load efficiency so that the power supply

can meet stringent standby power regulations.

C_SN2

R_SN2

R_SN1C_SN1

EMI

AC input

V_{O +}

Filter

D_OUT

V_IN

C_IN

C_OUT1

V_{O -}

D_SN

R_DAMP

D_DD1

D_DD2

C_OUT2

R_START

C_{DD 1}

C_DD2

R_G

VDD

GATE

SENSE

R_CSF

GND

R_CS

C_CSF

R_BIAS

C_FB

FAN6861

R₁

R_DB

C_F

R₂

KA431

Figure 1. Typical Application

Rev. 1.0.1 • 6/9/09

www.fairchildsemi.com

AN-6861

APPLICATION NOTE

(Design Example) The specifications of the target

system are:

2. Design Considerations

•

V_LINE^MIN=90V_RMSV_LINE^MAX)=264V_RMS

Flyback converters have two operation modes; continuous

conduction mode (CCM) and discontinuous conduction

mode (DCM). CCM and DCM have their own advantages

and disadvantages, respectively. In general, DCM provides

better switching conditions for the rectifier diodes, since the

diodes are operating at zero current just before becoming

reverse biased and the reverse recovery loss is minimized.

The transformer size can be reduced using DCM because

the average energy storage is low compared to CCM.

However, DCM inherently causes high RMS current, which

increases the conduction loss of the MOSFET severely for

low line condition. Thus, especially for applications with

peak load profile, such as printer and scanner; it is typical to

design the converter such that the converter operates in

CCM for low line and peak load condition to maximize

efficiency.

Line frequency (f_L) = 60Hz

Nominal output power (P_NO) = 20W (32V/0.625A)

Peak output power (P_PO) = 50W (32V/1.56A)

Peak load duration (t_PO) < 500ms

Estimated efficiency: η_N= 0.87 and η_P= 0.82

= 61W

INP

η_P0.82

= 23W

INN

η_N

0.87

FAN6861 can be used for this application because

the peak load duration is less than the OCP delay

time of 780ms.

In this section, a design procedure is presented using the

schematic of Figure 1 as a reference. An off line SMPS with

20W/32V nominal output power and 50W/32V peak output

power has been selected as a design example.

[STEP-2] Determine the Input Capacitor (C_IN) and the

Input Voltage Range

It is typical to select the input capacitor as 1.5~2μF per watt

of peak input power for universal input range (85-265V_RMS

)

and 0.7~0.8μF per watt of peak input power for European

input range (195V-265V_RMS). With the input capacitor

chosen, the minimum input capacitor voltage at peak load

condition is obtained as:

[STEP-1] Define the System Specifications

Designing a power supply with peak load current profile,

the following specifications should be determined first:

MAX

Line voltage range (V_LINE^MINand V_LINE

Line frequency (f_L).

)

MIN

_INP⋅(1 − D_CH)

C_IN⋅ f_L

(3)

V_INP

= 2⋅(V_LINE^MIN)²−

The minimum input capacitor voltage at nominal load

condition is obtained as:

Nominal output power (P_NO

)

Peak output power (P_PO) and its duration (t_PO)

⋅(1 − D_CH)

C_IN⋅ f_L

MIN

INN

(4)

V_INN

= 2⋅(V_LINE^MIN)²−

Estimated efficiencies for nominal load (η_N) and peak

load (η_P): The power conversion efficiency must be

estimated to calculate the input powers for each

condition. Typically, the efficiency at peak load

condition is lower than that of nominal load since most

of the components of power supply are selected for

nominal load condition. If no reference data is available,

set η_N= 0.7~0.75 and η_P= 0.65~0.7 for low-voltage

where D_CHis the input capacitor charging duty ratio defined

as shown in Figure 2, which is typically about 0.2.

The maximum input capacitor voltage is given as

MAX

(5)

V_IN

= 2V_LINE

output applications and η_N= 0.8~0.85 and η_P

0.75~0.8 for high-voltage output applications.

With the estimated efficiency, the input power for peak

load condition is given by:

(1)

INP

η_P

The input power for nominal load condition is given by:

Figure 2. Input Capacitor Voltage Waveform

(2)

INN

η_N

Rev. 1.0.1 • 6/9/09

www.fairchildsemi.com

AN-6861

APPLICATION NOTE

As can be seen in Equation (7), the voltage stress across the

MOSFET can be reduced by reducing V_RO. However, this

increases the voltage stresses on the rectifier diodes in the

secondary side. Therefore, V_ROshould be determined by a

trade-off between the voltage stresses of MOSFET and

diode. Because the actual drain voltage rises above the

nominal MOSFET voltage due to the leakage inductance of

(Design Example) By choosing a 100μF capacitor for

the input capacitor, the minimum input voltages for

peak and nominal load are obtained, respectively, as:

_INP⋅(1 − D_CH)

MIN

V_INP

= 2⋅(V_LINE^MIN)²−

C_IN⋅ f_L

61⋅(1− 0.2)

the transformer, as shown in Figure 3, it is typical to set V_RO

NOM

= 2⋅(90)²−

= 90V

around 70~100V so that V_DS

is 430~450V for 600V

100×10⁻⁶⋅60

⋅(1 − D_CH

MOSFET (73~78% of MOSFET voltage rating).

)

MIN

V_INN

= 2⋅(V_LINE^MIN)²−

INN

(Design Example) By determining V_ROas 100V:

C_IN⋅ f_L

V_RO

100

23⋅(1− 0.2)

100×10⁻⁶⋅60

D_MAX

= 0.53

= 2⋅(90)²−

=115V

MIN

100 + 90

V_RO+V_INP

NOM

MAX

The maximum input voltage is obtained as

V_DS

= V_IN

+V_RO= 273 +100 = 473V

MAX

V_IN

2 ⋅V_LINE

= 2 ⋅264 = 373V

[STEP-3] Determine the Reflected Output Voltage (V_RO

)

[STEP-4] Determine the Transformer Primary-Side

Inductance (L_M)

When the MOSFET is turned off, the input voltage (V_IN),

together with the output voltage reflected to the primary,

(V_RO) are imposed across the MOSFET, as shown in Figure

3. With a given V_RO, the maximum duty cycle (D_MAX) and

the maximum nominal MOSFET voltage (V_DS^NOM) are

obtained as:

The transformer primary-side inductance is determined for

the minimum input voltage and peak load condition. With

the D_MAXfrom Step-3, the primary-side inductance (L_M) of

the transformer is obtained as

V_RO

(V_INP^MIN⋅ D_MAX

2P _INPf_SWK_RF

)

(6)

D_MAX

MIN

(8)

L_M=

V_RO+V_INP

NOM

MAX

(7)

V_DS

= V_IN

+V_RO

where f_SWis the switching frequency and K_RFis the ripple

factor at peak load and minimum input voltage condition, as

shown in Figure 4.

The ripple factor is closely related to the transformer size

and the RMS value of the MOSFET current. Even though

the conduction loss in the MOSFET can be reduced by

reducing the ripple factor, too small a ripple factor forces an

increase in transformer size. From practical point of view, it

is reasonable to set K_RF= 0.3~0.6 for the universal input

range and K_RF= 0.4~0.8 for the European input range.

Once L_Mis calculated by determining K_RFfrom Equation

(8), the peak current and RMS current of the MOSFET for

minimum input voltage and peak load condition are

obtained as:

ΔI

(9)

(10)

(11)

I_DS= I_EDC

ΔI

MAX

⎡

⎣

⎤

RMS

I_DS

3(I_EDC)²+ (

)

⎢

⎥

⎦

INP

where:

I_EDC

MIN

V_INP⋅ D_MAX

Figure 3. The Output Voltage Reflected to the

Primary

MIN

V_INP

MAX

and

(12)

ΔI =

L_Mf_SW

Rev. 1.0.1 • 6/9/09

www.fairchildsemi.com

AN-6861

APPLICATION NOTE

The peak drain current at minimum input voltage and peak

load condition was obtained from Equation (9) in Step-4.

The peak drain current at minimum input voltage and

nominal load condition is given as:

ΔI

2I_EDC

K_RF

MIN

_INN⋅(V_IN

+V_RO)

ΔI

I_DS.N

V_INN^MIN⋅V_RO

(13)

(14)

V_INN^MIN⋅V_RO

2L_Mf_SW⋅(V_INN

:CCM

I_DS

MIN

+V_RO)

2⋅ P

INN

Figure 4. MOSFET Current and Ripple Factor (K_RF

)

I_DS.N

: DCM

f_SW⋅ L_M

Whether the converter operates in CCM or DCM at

minimum input voltage and nominal load condition is

determined by:

(Design Example) Determining the ripple factor as 0.57

MIN

(V_INP⋅ D_MAX

2P _INPf_SWK_RF

= 503μH

)

(90 ⋅0.53)²

L_M

2⋅61⋅65×10³⋅0.57

MIN

(V_INN

+V_RO)

2P_INNL_Mf_SW

⋅

>1 :CCM

<1 : DCM

V_INN^MIN⋅V_RO

INP

MIN

(15)

I_EDC

=1.28A

90⋅0.53

MIN

V_INP

⋅ D_MAX

(V_INN

+V_RO)

MIN

V_INN^MIN⋅V_RO

V_INP

MAX

90⋅0.53

503×10⁻⁶⋅65×10³

ΔI =

=1.46A

L_Mf_SW

The condition for the sensing resistor is given as:

0.5

ΔI

I_DS= I_EDC

=1.28 + 0.73 = 2.01A

R_CS

ΔI

MAX

⎡

⎤

RMS

I_DS

3(I_EDC)²+ (

)

I_DS.N

⎢

⎥

⎦

(16)

⎣

0.89

R_CS

0.53

⎡

⎤

3(1.28) + (0.73)

= 0.98A

I_DS

⎣

⎦

(Design Example) For minimum input voltage and

nominal load condition, the operation mode is DCM as:

[STEP-5] Determine the Sensing Resistor Value

MIN

(V_INN

+V_RO)

The current sensing resistor value should be determined

considering the over-current protection threshold and the

pulse-by-pulse current limit threshold, as shown in Figure 5.

The peak value of current sensing voltage (V_CS) should be

lower than the pulse-by-pulse current limit level for peak

load condition. It should be lower than the OCP threshold

for nominal load conditions to prevent false triggering of

OCP protection during normal operation.

2P_INNL_Mf_SW

⋅

V_INN^MIN⋅V_RO

(115+100)

115⋅100

2⋅23⋅503×10⁻⁶⋅65×10³⋅

The peak drain current at minimum input voltage and

nominal power condition is given as:

2⋅ P

f_SW⋅ L_M

2⋅23

INN

I_DS.N

=1.19A

65×10³⋅503×10⁻⁶

The conditions for the sensing resistor are given as:

0.5

1.19

0.89

R_CS

= 0.42Ω

I_DS.N

0.89

= 0.44Ω

V_CS= I_DS⋅ R_CS

I_DS.P2

2.01

Figure 5. Determining Current Sensing Resistor

Thus, a 0.39Ω resistor is selected for the current-sensing

resistor

Rev. 1.0.1 • 6/9/09

www.fairchildsemi.com

AN-6861

APPLICATION NOTE

[STEP-6] Determine the Minimum Primary Turns

[STEP-7] Determine the Number of Turns for Each

Winding

With a given core, the minimum number of turns for the

transformer primary side to avoid the core saturation is

given by:

Figure 7 shows a simplified diagram of the transformer.

First, calculate the turn ratio (n) between the primary side

and the secondary side from the reflected output voltage

determined in Step-3, as:

L_MI_LIM

L_M⋅0.89 / R_CS

min

×10⁶=

×10⁶

(17)

N_P

B_SAT

B_SATA

N_P

V_RO

where A_eis the cross-sectional area of the core in mm², I_LIM

is the pulse-by-pulse current limit level determined by

0.89V threshold, R_CSis current sensing resistor, and B_SATis

the saturation flux density in Tesla.

(18)

n =

N_SV_O+V_F

where N_Pand N_Sare the number of turns for primary side

and secondary side, respectively, V_Ois the output voltage;

and V_Fis the diode (D_O) forward-voltage drop. Then,

determine the proper integer for N_Ssuch that the resulting

N_Pis larger than N_P^minobtained from Equation (17).

The pulse-by-pulse current limit level is included in

Equation (17) because the inductor current reaches the

pulse-by-pulse current limit level during the load transient

or overload condition. Figure 6 shows the typical

characteristics of ferrite core from TDK (PC40). Since the

saturation flux density (B_SAT) decreases as the temperature

goes high, the high temperature characteristics should be

considered. If there is no reference data, use B_MAX=0.3T.

The number of turns for the auxiliary winding for V_DD

supply is determined as:

V_DD^*+V_F

(19)

N_A=

⋅ N_S1

V_O+V_FA

where V_DDis the nominal value of the supply voltage and

_FAis the forward voltage drop of D_DDas defined in Figure

7. Since V_DDincreases as the output load increases, it is

proper to set V_DDat 3~5V higher than V_DDUVLO level

(9.5V) to avoid the over-voltage protection condition during

the peak load operation.

Figure 6. Typical B-H Characteristics of Ferrite Core

(TDK/PC40)

Figure 7. Simplified Transformer Diagram

(Design Example) Assuming the diode forward-

voltage drop is 1V, the turn ratio is obtained as:

(Design Example) A EF25/13/11 core is selected,

whose effective cross-sectional area is 78mm².

Choosing the saturation flux density as 0.25T, the

minimum number of turns for the primary side is

obtained as:

N_P

V_RO

100

n =

= 3.03

N_SV_O+V_F32 +1

Then, determine the proper integer for N_Ssuch that the

resulting N_Pis larger than N_P^minas:

L_M⋅0.89/ R_CS

min

N_P

×10⁶

min

N_S= 20, N_P= n ⋅ N_S= 61> N_P

B_SAT

Setting V_DD* as 12.5V, the number of turns for the

auxiliary winding is obtained as:

503×10⁻⁶⋅0.89/0.39

0.25⋅78

×10⁶= 59

V_DD^*+V_F

V_O+V_FA

12.5 +1

32 +1

N_A=

⋅ N_S=

⋅ 20 = 8

Rev. 1.0.1 • 6/9/09

www.fairchildsemi.com

AN-6861

APPLICATION NOTE

[STEP-8] Determine the Wire Diameter for Each Winding

Based on the RMS Current of Winding.

(Design Example) The diode voltage and current are

calculated as:

The maximum RMS current of the secondary winding is

obtained as:

MAX

V_IN

373

V_DO= V_O+

= 32 +

=154V

3.05

1− D_MAX

RMS

1− D_MAX

D_MAX

(20)

I_SEC

= n⋅ I_DS

RMS

I_DO

= n ⋅ I_DS

D_MAX

The current density is typically 6~10A/mm²when the wire

is long (>1m). When the wire is short with a small number

of turns, a current density of 8~14A/mm²is also acceptable.

These current densities are based on the peak load condition

and therefore almost twice of conventional power supply

design. Avoid using wire with a diameter larger than 1mm

to avoid severe eddy current losses and to make winding

easier. For high current output, use parallel windings with

multiple strands of thinner wire to minimize skin effect.

1− 0.53

0.53

= 3.05⋅0.98

= 2.8A

10A and 200V diode is selected assuming very small

heat-sink is used for the diode

[STEP-10] Feedback Circuit Configuration

The FAN6861 employs peak-current-mode control as

shown in Figure 8 . A current-to-voltage conversion is

accomplished externally with current-sense resistor R_CS.

Under normal operation, the FB level controls the peak

inductor current as:

(Design Example) The RMS current of the primary-

side winding is obtained from Step-4 as 1.01A. The

RMS current of the secondary-side winding is

calculated as:

V_FB-1.2

(25)

I_DS⋅ R_CS+V_SLOPE= I_DS⋅ R_CS+ 0.35⋅ D =

1− D_MAX

D_MAX

RMS

I_SEC

= n ⋅ I_DS

where V_FBis the voltage of FB pin, V_SLOPEis synchronized

positive-going ramp, and D is duty cycle ratio.

1− 0.53

0.53

= 3.05⋅0.98

= 2.8A

0.4mm (8A/mm²) and 0.55mm (12A/mm²) diameter

wires are selected for primary and secondary windings,

respectively.

[STEP-9] Choose the Rectifier Diode in the Secondary-

Side Based on the Voltage and Current Ratings.

The maximum reverse voltage and the RMS current of the

rectifier diode are obtained as:

MAX

V_IN

(21)

(22)

V_DO=V_O+

1− D_MAX

D_MAX

RMS

I_DO

= n⋅ I_DS

Figure 8. Peak Current Mode Circuit

Figure 9 is a typical feedback circuit mainly consisting of a

shunt regulator and a photo-coupler. R1 and R2 form a

voltage divider for output voltage regulation. R_Fand C_Fare

adjusted for control-loop compensation. A small-value RC

filter (e.g. R_FB= 100Ω, C_FB= 1nF) placed from the FB pin to

GND can increase stability substantially. The maximum

source current of the FB pin is about 325μA. The

phototransistor must be capable of sinking this current to

pull the FB level down at no load. The value of the biasing

resistor, R_BIAS, is determined as:

The typical voltage and current margins for the rectifier

diode are as:

(23)

V_RRM>1.3⋅V_DO

RMS

(24)

I_F>1.5⋅ I_DO

where V_RRMis the maximum reverse voltage and I_Fis the

current rating of the diode.

Rev. 1.0.1 • 6/9/09

www.fairchildsemi.com

AN-6861

APPLICATION NOTE

[STEP-11] Design the Startup Circuit

V_O−V_OPD−V_KA

⋅CTR > 325×10⁻⁶

(26)

R_BIAS

Figure 10 shows the typical startup circuit for FAN6861.

Connecting startup resistor to AC line allows the reset of

latch protection by unplugging the AC line from the power

supply. Two-stage hold-up capacitor configuration (C_DD1

and C_DD2) is typically used to increase the hold-up time

while minimizing the startup time.

where V_OPDis the drop voltage of photodiode, about 1.2V:

V_KAis the minimum cathode to anode voltage of shunt

regulator (2.5V); and CTR is the current transfer rate of the

opto-coupler.

Initially, FAN6861 consumes only startup current

(maximum 15μA) before it begins normal switching

operation. Therefore, the current supplied through the

startup resistor (R_START) can charge capacitor C_DD1while

supplying the startup current to FAN6861. When V_DD

reaches turn-on voltage of 17.5V (V_DD-ON), FAN6861 begins

switching operation and the current consumed by FAN6861

increases to normal operating current (typical 3mA). Then,

the current required by FAN6861 is supplied from the

auxiliary winding of transformer.

The average current supplied through the startup resistor for

minimum line voltage condition is

MIN

2V_LINE

V_DD−ON

(28)

(29)

I_RST= (

−

)

> I_DD−ST

R_START

Figure 9. Feedback Circuit

V_DD−ON

MAX

T_START

= C_DD1

MAX

I_RST− I_DD−ST

The feedback compensation network transfer function of

Figure 9 is obtained as:

The maximum power dissipation of R_STARTis:

MAX

(V_LINE

)

v_FB

ω_I1+ s /ω_ZC

(30)

(27)

≅

= −

⋅

RST

2R_START

v_o

s 1+ s /ω_PC

R_B

where

ω_I=

ω_ZC=

R R_DBC_F

(R_F+ R )C_O

R_BC_FB

ω_pc

R_Bis the internal feedback bias resistor of FAN6861; and R₁,

R_D, R_F, C_F, and C_FBare shown in Figure 9.

(Design Example) Assuming CTR is 100%;

V_O−V_OPD−V_KA

⋅CTR > 325×10⁻⁶

R_BIAS

V_O−V_OPD−V_KA32 −1.2 − 2.5

R_BIAS

= 87kΩ

325×10⁻⁶

3kΩ resistor is selected for R_DB.

The voltage divider resistors for V_Osensing are

selected as 120kΩ and 10kΩ.

Figure 10. Startup Circuit

Rev. 1.0.1 • 6/9/09

www.fairchildsemi.com

AN-6861

APPLICATION NOTE

Thermal Protection

(Design Example) 510kΩ resistor and 10μF capacitor

are selected for R_STARTand C_DD1, respectively.

Figure 12 shows the internal blocks for thermal protection.

A constant current, I_RT, of 99μA is provided from the RT

pin. For over-temperature protection, an NTC thermistor in

series with a resistor can be connected between the RT and

GND pins. As temperature increases, the impedance of

NTC thermister decreases and RT pin voltage drops. When

the voltage of the RT pin is less than 1V longer than 17ms

(t_DOTP-LATCH), OTP is triggered. When RT pin voltage is less

than 0.7V, OTP is triggered after the 100μs debounce time.

Then, the current through the startup resistor for

minimum line voltage is:

MIN

2V_LINE

V_DD−ON

I_RST= (

−

)

R_START

2 ⋅90 17.5

= (

−

)

= 62μ A

510×10³

Then, the maximum startup time is obtained as

If the thermal protection is not used, connect a small

capacitor (around 0.47nF is recommended) from the RT pin

to the GND pin to prevent noise interference. This RT

capacitor should not be larger than 1nF; otherwise, the

thermal protection is triggered before a successful build-up

of output voltage.

V_DD−ON

MAX

T_START

= C_DD1

MAX

I_RST− I_DD−ST

17.5

(62 −15)×10⁻⁶

=10×10⁻⁶

= 3.7sec

The maximum power dissipation of R_STARTis:

MAX

(V_LINE

)

265²

2⋅510×10³

≅

= 68mW

RST

2R_START

Leading-Edge Blanking (LEB)

Each time the power MOSFET is switched on, a turn-on

spike occurs across the sense resistor, caused by primary-

side capacitance and secondary-side rectifier reverse

recovery. To avoid premature termination of the switching

pulse, a leading-edge blanking time is built in. During this

blanking period (360ns), the PWM comparator is disabled

and cannot switch off the gate driver. Thus, an RC filter

with a small RC time constant is enough for current sensing

(e.g. 200Ω + 470pF). A non-inductive resistor is

recommended for R_CS.

Figure 12. Thermal Protection Circuit

Figure 11. Current sensing

Rev. 1.0.1 • 6/9/09

www.fairchildsemi.com

AN-6861

APPLICATION NOTE

Printed Circuit Board (PCB) Layout

PCB layout is a very important design issue for high-

frequency switching current/voltage application. Good PCB

layout minimizes excessive EMI and helps the power supply

survive during surge/ESD tests.

Two suggestions with different pro and cons for ground

connections are offered:

GND3 → 2 → 4 → 1: This could avoid common

impedance interference for sense signal.

Guidelines:

GND3 → 2 → 1 → 4: This could be better for ESD

testing where the earth ground is not available on the

power supply. Regarding the ESD discharge path, the

charges go from secondary through the transformer

stray capacitance to GND2 first. The charges then go

from GND2 to GND1 and back to the mains. Note that

control circuits should not be placed on the discharge

path. Point discharge for common choke can decrease

high-frequency impedance and increase ESD immunity.

To get better EMI performance and reduce line

frequency ripples, the output of the bridge rectifier

should be connected to capacitor C1 first, then to the

switching circuits.

The high-frequency current loop is in C1

–

transformer – MOSFET – R_S– C1. The area enclosed

by this current loop should be as small as possible.

Keep the traces (especially 4→1) short, direct, and

wide. High-voltage traces related to the drain of

MOSFET and RCD snubber should be kept far way

from control circuits to prevent unnecessary

interference. If a heatsink is used for the MOSFET,

connect this heatsink to ground.

Should a Y-cap between primary and secondary be

required, connect this Y-cap to the positive terminal of

C1. If this Y-cap is connected to the primary GND, it

should be connected to the negative terminal of C1

(GND1) directly. Point discharge of this Y-cap also

helps for ESD. However, the creepage between these

two pointed ends should be large enough to satisfy the

requirements of applicable standards.

As indicated by 3, the ground of control circuits should

be connected first, then to other circuitry.

As indicated by 2, the area enclosed by transformer

auxiliary winding, D1, C2, D2, and C3 should also be

kept small. Place C3 close to the FAN6861 for good

decoupling.

V_DC

AC Input

Common-Mode

Choke

VDD

GATE 6

R_T

R_FB

SENSE

GND

C_FB

Y-cap

FAN6861

Figure 13. Layout Considerations

Rev. 1.0.1 • 6/9/09

www.fairchildsemi.com

AN-6861

APPLICATION NOTE

Design Summary

Figure 1 shows the final schematic of the 20W (50W peak) power supply of the design example.

470pF

C_SN2

R_SN2

R_SN1C_SN1

1.6µH

EMI

AC input

O+

O-

Filter

100 µ F

D _OUT

100 k

10 A/200 V

V_IN

10nF

C_IN

C_{O UT 1}

470 µ F

D_SN

R_DAMP

D_DD1

D_{DD 2}

C_OUT2

510 k

220 µ F

R_START

C_{DD 1}

C_{DD 2}

100µ F

10µ F

R_G

VDD

82k

GATE

4N60

300

SE NSE

R_CSF

0.39

GND

120 k

R_CS

C_CSF

R_BIAS

C_{F B}

1nF

FAN 6861

470 pF

R₁

R_DB

R_F

C_F

2.2k

4.7k

10nF

R₂

KA431

10k

Figure 14. Final Schematic of Design Example

Rev. 1.0.1 • 6/9/09

www.fairchildsemi.com

AN-6861

APPLICATION NOTE

Figure 14.

Figure 15. Transformer Specification

Winding Specification

Diameter / Thickness

0.4mm

Turns

5 Æ 3

Insulation Tape

Shielding lead to Pin 2

Insulation Tape

6, 7 Æ 8, 9

Insulation Tape

0.55mm

Shielding lead to Pin 2

Insulation Tape

3 Æ 4

Insulation Tape

1 Æ 2

Insulation Tape

0.4mm

0.2mm

Core: EF25/13/11 (Ae=78 mm²)

Bobbin: EF25/13/11

Inductance: 500μH

Rev. 1.0.1 • 6/9/09

www.fairchildsemi.com

AN-6861

APPLICATION NOTE

Related Datasheets

FAN6861 — Low Cost and Highly Integrated Green-Mode PWM Controller for Peak Power Management

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS

PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS

WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems which,

(a) are intended for surgical implant into the body, or (b)

support or sustain life, or (c) whose failure to perform when

properly used in accordance with instructions for use provided

in the labeling, can be reasonably expected to result in

significant injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

Rev. 1.0.1 • 6/9/09

www.fairchildsemi.com

AN-6861 [FAIRCHILD]

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