ACE1502VN14_技术文档

October 2002

ACE1502 Product Family

Arithmetic Controller Engine (ACEx™)

for Low Power Applications

ꢀ Hardware Bit–Coder (HBC)

General Description

ꢀ On-chip oscillator

The ACE1502 (Arithmetic Controller Engine) family of microcon-

trollers is a dedicated programmable monolithic integrated circuit

for applications requiring high performance, low power, and small

size. It is a fully static part fabricated using CMOS technology.

— No external components

— 1µs instruction cycle time +/-2% accuracy

ꢀ Instruction set geared for block encryption

ꢀ On-chip Power-on Reset

The ACE1502 product family has an 8-bit microcontroller core,

64 bytes of RAM, 64 bytes of data EEPROM and 2K bytes of

code EEPROM. Its on-chip peripherals include a multifunction

16-bit timer, a watchdog/idle timer, and programmable under-

voltage detection circuitry. On-chip clock and reset functions

reduce the number of required external components. The

ACE1502 product family is available in 8- and 14-pin SOIC,

TSSOP and DIP packages.

ꢀ Programmable read and write disable functions

ꢀ Memory mapped I/O

ꢀ 32-level Low Voltage Detection

ꢀ Brown-out Reset

ꢀ Software selectable I/O option

— Push-pull outputs with tri-state option

— Weak pull-up or high impedance inputs

ꢀ Fully static CMOS

Features

ꢀ Arithmetic Controller Engine

ꢀ 2K bytes on-board code EEPROM

ꢀ 64 bytes data EEPROM

— Low power HALT mode (100nA @ 2.7V)

— Power saving IDLE mode

ꢀ Single supply operation

— 1.8-3.6V

ꢀ 40 years data retention

ꢀ 64 bytes RAM

ꢀ 1.8V data EEPROM min writing voltage

ꢀ 1,000,000 data changes

ꢀ Watchdog

ꢀ Multi-input wake-up on all eight general purpose I/O pins

ꢀ 16-bit multifunction timer with difference capture

ꢀ 8- and 14-pin SOIC, TSSOP and DIP packages

ꢀ In-circuit programming

Block and Connection Diagram

VCC¹

Brown-out Reset/Low

Battery Detect

GND¹

Power-on Reset

RESET²

HALT & IDLE Power

Internal Oscillator

(CKO) G0

(CKI) G1

(T1/TX) G2

G3

Saving Modes

12-bit Timer0 with

Watchdog Timer

GPORT

ACE1502 core

16-bit Multi-function

general

purpose

I/O with

multi-

input

wakeup

(4 interrupt

sources

Timer1 with Difference

Capture

and vectors)

G4

Hardware Bit-Coder

64 bytes of RAM

(TX) G5

G6²

Programming Interface

2K bytes of Code

EEPROM

64 bytes of Data

EEPROM

G7²

1. 100nf Decoupling capacitor recommended

2. Available only in the 14-pin package option

ACE1502 Product Family Rev. 1.7

1

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Figure 2. ACEx Application Example (Remote Keyless Entry)

V

CC

Optional

LED

G4

V

G3

CC

RF Interface

G0

G1

G5

G2

RF Stage

GND

Figure 3. ACE1502 8-pin SOIC and DIP Device Pinout

a) Normal Mode Operation b) Programming Mode Operation

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

LOAD

SFT_IN

NC/VCC

NC

VCC

G3

G4

G5

G0

VCC

GND

G2

GND

SFT_OUT

CKI

G1

Figure 4. ACE1502 8-pin TSSOP Device Pinout

a) Normal Mode Operation

b) Programming Mode Operation

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

GND

VCC

G3

G2

G1

G0

G5

GND

VCC

SFT_OUT

CKI

LOAD

SFT_IN

NC

G4

NC/VCC

Figure 5. ACE1502 14-pin SOIC,TSSOP and DIP Device Pinout

a) Normal Mode Operation b) Programming Mode Operation

1

2

3

4

5

6

7

14

13

12

11

10

9

G3

G4

NC

G6

G7

G5

G0

VCC

GND

NC

1

2

3

4

5

6

7

14

13

12

11

10

9

LOAD

SFT_IN

NC

VCC

GND

NC

G2

NC

SFT_OUT

NC

NC/VCC

NC

RESET

CKI

RESET

G1

8

2

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ACE1502 Product Family Rev. 1.7

2. Electrical Characteristics

Absolute Maximum Ratings

Operating Conditions

Ambient Storage Temperature

-65 °C to +150 °C

Relative Humidity (non-condensing)

95%

Input Voltage

-0.3V to V + 0.3V

EEPROM write limits

See DC Electrical Characteristics

CC

Lead Temperature (10s max)

Electrostatic Discharge on all pins

+300°C

2000V min

Part Number

ACE1502E

Operating Voltage

1.8 to 3.6V

Ambient Operating Temperature

-40°C to +85°C

-40°C to +125°C

ACE1502V

1.8 to 3.6V

ACE1502 DC Electrical Characteristics, V = 1.8 to 3.6V

CC

All measurements are valid for ambient operating temperature unless otherwise stated.

Symbol

Parameter

Conditions

MIN

TYP

MAX Units

3

Icc

Suppy Current - no data EEPROM 1.8V

write in progress

0.4

0.5

0.6

0.7

1.0

mA

2.2V

2.7V

3.6V

Icc

HALT Mode current

2.7V @ 25°C

2.7V @ -40°C to +85°C

400

5000

nA

H

100

3.6V @ 25°C

3.6V @ -40°C to +85°C

1000

10

nA

µA

0.25

4

Icc

IDLE Mode current

1.8V

3.6V

210

250

µA

L

400

3.6

Vcc

EEPROM write voltage

Code EEPROM in Programming Mode

Data EEPROM in Operating Mode

3.0

1.8

3.3

V

W

3.6

S

V

Power Supply Slope

1µs/V

10ms/V

0.2Vcc

0.15Vcc

Vcc

Input Low with Schmitt Trigger buffer Vcc = 2.2 - 3.6V

Vcc < 2.2V

V

IL

V

Input High with Schmitt Trigger buffer Vcc = 1.8 - 3.6V

0.8Vcc

30

V

IH

I

Input Pull-up Current

Tri-State Leakage

Vcc = 3.6V, V = 0V

65

2

350

200

µA

nA

IP

TL

IN

Vcc = 3.6V

V

Output Low Voltage:

G0, G1, G2, G3, G4, G5, G6, G7

Vcc = 1.8 - 2.7V

2 mA sink

OL

0.2Vcc

V

Output Low Voltage:

G0, G1, G2, G3, G4, G5, G6, G7

Vcc = 3.3 - 3.6V

7.0 mA sink

V

Output High Voltage:

G0, G1, G2, G3, G4, G5, G6, G7

Vcc = 2.2 - 2.7V

2 mA source

0.8Vcc

OH

Output High Voltage:

G0, G1, G2, G3, G4, G5, G6, G7

Vcc = 3.3 - 3.6V

7 mA source

V

3. Icc active current is dependant on the program code.

4. Based on a continuous IDLE looping program.

3

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ACE1502 Product Family Rev. 1.7

ACE1502 AC Electrical Characteristics, Vcc = 1.8 to 3.6V

All measurements are valid for ambient operating temperature unless otherwise stated.

Parameter

Conditions

MIN TYP MAX Units

Instruction cycle time from internal clock -

setpoint

3.3V at +25°C

0.98

1.0

1.02

µs

Internal clock frequency variation

1.8V to 3.6V at constant temperature

1.2

%

1.8V to 3.6V at full temperature range (Note 6)

6

25

8

Crystal oscillator frequency

External clock frequency

EEPROM write time

(Note 5)

MHz

ms

5.5

10

2

Internal clock start up time

Oscillator start up time

(Note 6)

ms

2400

cycles

5. The maximum permissible frequency is guaranteed by design but is not 100% tested

6. The parameter is characterized but is not 100% tested, contact Fairchild for additional characterization data.

ACE1502 Electrical Characteristics for programming

All data valid at ambient temperature between 3.0V and 3.6V.The following characteristics are guaranteed

by design but are not 100% tested. See “EEPROM write time” in the AC Electrical Characteristics for

deﬁnition of the programming ready time.

Parameter

Description

MIN

500

100

900

3.2

MAX

DC

Units

ns

t

CLOCK high time

HI

CLOCK low time

DC

ns

LO

SHIFT_IN setup time

SHIFT_IN hold time

SHIFT_OUT setup time

SHIFT_OUT hold time

Power On Reset time

LOAD timing

ns

DIS

DIH

DOS

DOH

ns

T

4.5

ms

µs

RESET

t

, t

5

LOAD1 LOAD2 LOAD3 LOAD4

ACE1502 Low Battery Detect (LBD) Characteristics, Vcc = 1.8 to 3.6V

Parameter

Conditions

MIN

TYP

MAX

Units

LBD voltage threshold variation

-40°C to +85°C

-5

+5

%

ACE1502 Brown-out Reset (BOR) Characteristics, Vcc = 1.8 to 3.6V

Parameter

Conditions

MIN

TYP

MAX

Units

BOR voltage threshold variation

-40°C to +85°C

1.72

1.83

1.92

V

4

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ACE1502 Product Family Rev. 1.7

AC & DC Electrical Characteristic Graphs

The graphs in this section are for design guidance and are based on preliminary test data.

Figure 6. Internal Oscillator Frequency

Internal Oscillator Frequency vs. Temperature

2.01

2

1.99

1.98

1.97

1.96

1.95

1.94

1.93

3.6V

3.3V

2.8V

2.6V

2.2V

2.0V

1.8V

-40

0

25

85

125

Temperature [°C]

Figure 7. LBD and BOR Threshold Levels

LBD Levels 1,16 and 32

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

Level 1

Level 16

Level 32

-40

0

25

85

125

Temperature [°C]

BOR Level

1.840

1.835

1.830

1.825

1.820

1.815

1.810

1.805

1.800

BOR Level

-40

0

25

85

125

Temperature [°C]

5

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ACE1502 Product Family Rev. 1.7

Figure 8. Icc Active

Icc Active (no data EEPROM writes) vs. Temperature

0.90

0.80

0.70

0.60

0.50

0.40

0.30

0.20

0.10

0.00

4.0V

3.6V

2.7V

2.2V

1.8V

1.6V

-40

0

25

85

125

Temperature [°C]

Icc Active (data EEPROM writes) vs. Temperature

4.50

4.00

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

4.0V

3.6V

2.7V

2.2V

1.8V

1.6V

-40

0

25

85

125

Temperature [°C]

Figure 9. HALT Mode Currents

HALT current vs. Temperature

20.000

18.000

16.000

14.000

12.000

10.000

8.000

4.0V

3.6V

2.7V

2.2V

1.8V

1.6V

6.000

4.000

2.000

0.000

-40

0

25

85

125

Temperature [°C]

6

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ACE1502 Product Family Rev. 1.7

Figure 10. IDLE Mode Currents

IDLE Mode Current

350.00

300.00

250.00

200.00

150.00

100.00

50.00

4.0V

3.6V

2.7V

2.2V

1.8V

1.6V

0.00

-40

0

25

85

125

Temperature [°C]

Figure 11. V /V vs. Current

OL OH

V_OLvs. I_OL

3.00

2.50

2.00

1.50

1.00

0.50

0.00

3.6V

4.0V

2.7V

2.2V

1.8V

0

2

5

7

9

12

15

I_OL(mA)

V

_OHvs. I_OH@ 25 °C

4.50

4.00

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

4.0V

3.6V

2.7V

2.2V

1.8V

0

2

5

7

9

12

15

I_OHcurrent (mA)

7

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ACE1502 Product Family Rev. 1.7

3. Arithmetic Controller Core

The ACEx microcontroller core is speciﬁcally designed for low

cost applications involving bit manipulation, shifting and block

encryption. It is based on a modiﬁed Harvard architecture

meaning peripheral, I/O, and RAM locations are addressed sep-

arately from instruction data.

the overall code efﬁciency of the ACEx microcontroller and

takes advantage of the ﬂexibility found on Von Neumann style

machines.

3.1 CPU Registers

The ACEx microcontroller has ﬁve general-purpose registers.

These registers are the Accumulator (A), X-Pointer (X), Pro-

gram Counter (PC), Stack Pointer (SP), and Status Register

(SR). The X, SP, and SR registers are all memory-mapped.

The core differs from the traditional Harvard architecture by

aligning the data and instruction memory sequentially. This

allows the X-pointer (12-bits) to point to any memory location in

either segment of the memory map. This modiﬁcation improves

Figure 12. Programming Model

A

7

0

N

8-bit accumulator register

12-bit X pointer register

11-bit program counter

4-bit stack pointer

X

11

PC

SP

SR

10

3

R

0

G

Z

C

H

8-bit status register

NEGATIVE flag

HALF CARRY flag (from bit 3)

CARRY flag (from MSB)

ZERO flag (bit 4)

GLOBAL INTERRUPT enable

READY flag (from EEPROM)

Bit 11 = 1, then the LD A, [00,X] instruction will take a value

from address range 0x800 to 0xFFF and load it into A.

3.1.1 Accumulator (A)

The Accumulator is a general-purpose 8-bit register that is used

to hold data and results of arithmetic calculations or data manip-

ulations.

The X register can also serve as a counter or temporary storage

register. However, this is true only for the 11-LSBs since the

th

12 bit is dedicated for memory space selection.

3.1.2 X-Pointer (X)

3.1.3 Program Counter (PC)

The X-Pointer register allows for a 12-bit indexing value to be

added to an 8-bit offset creating an effective address used for

reading and writing between the entire memory space. (Soft-

ware can only read from code EEPROM.) This provides soft-

ware with the ﬂexibility of storing lookup tables in the code

EEPROM memory space for the core’s accessibility during nor-

mal operation.

The 11-bit program counter register contains the address of the

next instruction to be executed. After a reset, if in normal mode

the program counter is initialized to 0x800.

3.1.4 Stack Pointer (SP)

The ACEx microcontroller has an automatic program stack with

a 4-bit stack pointer. The stack can be initialized to any location

between addresses 0x30-0x3F. Normally, the stack pointer is

initialized by one of the ﬁrst instructions in an application pro-

gram. After a reset, the stack pointer is defaulted to 0xF pointing

to address 0x3F.

The ACEx core allows software to access the entire 12-bit X-

Pointer register using the special X-pointer instructions e.g. LD

X, #000H. (See Table 8.) However, software may also access

the register through any of the memory-mapped instructions

using the XHI (X[11:8]) and XLO (X[7:0]) variables located at

0xBE and 0xBF, respectively. (See Table 10.)

The stack is conﬁgured as a data structure which decrements

from high to low memory. Each time a new address is pushed

onto the stack, the core decrements the stack pointer by two.

Each time an address is pulled from the stack, the core incre-

ments the stack pointer is by two. At any given time, the stack

pointer points to the next free location in the stack.

The X register is divided into two sections. The 11 least signiﬁ-

cant bits (LSBs) of the register is the address of the program or

data memory space. The most signiﬁcant bit (MSB) of the reg-

ister is write only and selects between the data (0x000 to

0x0FF) or program (0x800 to 0xFFF) memory space.

When a subroutine is called by a jump to subroutine (JSR)

instruction, the address of the instruction is automatically

pushed onto the stack least signiﬁcant byte ﬁrst. When the

Example: If Bit 11 = 0, then the LD A, [00,X] instruction will take

a value from address range 0x000 to 0x0FF and load it into A. If

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ACE1502 Product Family Rev. 1.7

subroutine is ﬁnished,

a

return from subroutine (RET)

return from interrupt instruction is normally executed to restore

the PC to the value that was present before the interrupt

occurred. The G bit is the reset to one after a return from inter-

rupt is executed. Although the G bit can be set within an inter-

rupt service routine, “nesting” interrupts in this way should only

be done when there is a clear understanding of latency and of

the arbitration mechanism.

instruction is executed. The RET instruction pulls the previously

stacked return address from the stack and loads it into the

program counter. Execution then continues at the recovered

return address.

3.1.5 Status Register (SR)

The 8-bit Status register (SR) contains four condition code indi-

cators (C, H, Z, and N), one interrupt masking bit (G), and an

EEPROM write ﬂag (R.) The condition codes are automatically

updated by most instructions. (See Table 9.)

3.2 Interrupt handling

When an interrupt is recognized, the current instruction com-

pletes its execution. The return address (the current value in the

program counter) is pushed onto the stack and execution con-

tinues at the address speciﬁed by the unique interrupt vector

(see Table 10.). This process takes ﬁve instruction cycles. At

the end of the interrupt service routine, a return from interrupt

(RETI) instruction is executed. The RETI instruction causes the

saved address to be pulled off the stack in reverse order. The G

bit is set and instruction execution resumes at the return

address.

Carry/Borrow (C)

The carry ﬂag is set if the arithmetic logic unit (ALU) performs a

carry or borrow during an arithmetic operation and by its dedi-

cated instructions. The rotate instruction operates with and

through the carry bit to facilitate multiple-word shift operations.

The LDC and INVC instructions facilitate direct bit manipulation

using the carry ﬂag.

The ACEx microcontroller is capable of supporting four inter-

rupts. Three are maskable through the G bit of the SR and the

fourth (software interrupt) is not inhibited by the G bit (Figure

13.) The software interrupt is generated by the execution of the

INTR instruction. Once the INTR instruction is executed, the

ACEx core will interrupt whether the G bit is set or not. The

INTR interrupt is executed in the same manner as the other

maskable interrupts where the program counter register is

stacked and the G bit is cleared. This means, if the G bit was

enabled prior to the software interrupt the RETI instruction must

be used to return from interrupt in order to restore the G bit to its

previous state. However, if the G bit was not enabled prior to

the software interrupt the RET instruction must be used.

Half Carry (H)

The half carry ﬂag indicates whether an overﬂow has taken

place on the boundary between the two nibbles in the accumu-

lator. It is primarily used for Binary Coded Decimal (BCD) arith-

metic calculation.

Zero (Z)

The zero ﬂag is set if the result of an arithmetic, logic, or data

manipulation operation is zero. Otherwise, it is cleared.

Negative (N)

The negative ﬂag is set if the MSB of the result from an arith-

metic, logic, or data manipulation operation is set to one. Other-

wise, the ﬂag is cleared. A result is said to be negative if its MSB

is a one.

In case of multiple interrupts occurring at the same time, the

ACEx microcontroller core has prioritized the interrupts. The

interrupt priority sequence in shown in Table 7.

Interrupt Mask (G)

Table 7: Interrupt Priority Sequence

The interrupt request mask (G) is a global mask that disables all

maskable interrupt sources. If the G Bit is cleared, interrupts

can become pending, but the operation of the core continues

uninterrupted. However, if the G Bit is set an interrupt is recog-

nized. After any reset, the G bit is cleared by default and can

only be set by a software instruction. When an interrupt is rec-

ognized, the G bit is cleared after the PC is stacked and the

interrupt vector is fetched. Once the interrupt is serviced, a

Priority (4 highest, 1 lowest)

Interrupt

MIW (EDGEI)

4

3

2

1

Timer0 (TMRI0)

Timer1 (TMRI1)

Software (INTR)

Figure 13. Basic Interrupt Structure

INTR

T1PND

T1

T0PND

T0

Interrupt

WKPND

MIW

Interrupt

Pending

Flags

T0INT

EN

WKINT

EN

G

T1EN

Global Interrupt

Enable

Interrupt Enable Bits

9

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ACE1502 Product Family Rev. 1.7

3.3 Addressing Modes

Immediate

The ACEx microcontroller has seven addressing modes

indexed, indirect, direct, immediate, absolute jump, and relative

jump.

The instruction contains an 8-bit immediate ﬁeld as an operand.

Inherent

This instruction has no operands associated with it.

Indexed

Absolute

The instruction allows an 8-bit unsigned offset value to be

added to the 11-LSBs of the X-pointer yielding a new effective

address. This mode can be used to address either data or pro-

gram memory space.

The instruction contains an 11-bit address that directly points to

a location in the program memory space. There are two oper-

ands associated with this addressing mode. Each operand con-

tains a byte of an address. This mode is used only for the long

jump (JMP) and JSR instructions.

Indirect

The instruction allows the X-pointer to address any location

within the data memory space.

Relative

This mode is used for the short jump (JP) instructions where the

operand is a value relative to the current PC address. With this

instruction, software is limited to the number of bytes it can

jump, -31 or +32.

Direct

The instruction contains an 8-bit address ﬁeld that directly

points to the data memory space as an operand.

Table 8. Instruction Addressing Modes

Instruction

Immediate

Direct

Indexed Indirect Inherent Relative Absolute

ADC

ADD

AND

OR

SUBC

XOR

A, #

A, M

A, [#, X]

A, [X]

CLR

INC

DEC

M

A

X

IFEQ

IFGT

IFNE

IFLT

A, #

X, #

M,#

A, M

A, [#, X]

A, [X]

SC

RC

IFC

IFNC

INVC

LDC

STC

no-op

#, M

RLC

RRC

M

A

LD

ST

A, #

M, #

X, #

A, M

M, M

A, [#, X]

A, [X]

NOP

no-op

IFBIT

#, A

#, M

[#, X]

IFNBIT

SBIT

RBIT

#, M

[#, X]

JP

Rel

JSR

JMP

RET

RETI

INTR

[#, X]

M

no-op

10

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ACE1502 Product Family Rev. 1.7

Table 9. Instruction Cycles and Bytes

Flags

Mnemonic Operand Bytes Cycles affected

Flags

Mnemonic Operand Bytes Cycles affected

ADC

ADD

AND

CLR

A, [X]

A, [#,X]

A, M

A, #

A, [X]

A, [#,X]

A, M

A, #

A, [X]

A, [#,X]

A, M

A, #

X

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

3

2

1

2

3

1

2

1

2

1

2

3

1

2

1

3

2

1

3

2

1

3

2

1

2

1

2

1

3

1

2

3

1

2

3

1

2

1

3

1

2

3

1

2

C,H,Z,N

Z,N

INC

INTR

INVC

JMP

JP

X

1

3

2

1

3

2

1

2

3

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

5

1

4

3

1

5

2

3

1

2

3

2

1

3

2

1

5

1

2

1

2

1

3

1

2

1

3

2

1

3

2

Z

None

C

M

None

C

[#, X]

Z,N

JSR

LD

M

[#, X]

A, #

Z,N

LD

A, [#,X]

A, [X]

A, M

M, #

Z,N

LD

Z,N

LD

Z

LD

CLR

A

C,H,Z,N

Z

LD

M, M

X, #

CLR

M

LD

DEC

IFBIT

IFC

X

LDC

NOP

OR

#, M

A

Z,N

None

Z, N

M

Z,N

A, [X]

A, [#,X]

A, M

#, A

#, M

#, [X]

None

Z,N

OR

Z,N

OR

Z,N

OR

A, #

Z,N

RBIT

RC

#, [X]

#, M

Z,N

IFEQ

IFGT

IFLT

A, [#, X]

A, [X]

A, #

Z,N

C,H

RET

RETI

RLC

RRC

SBIT

SC

None

C,Z,N

Z,N

A, M

M, #

A

M

X, #

A, [#, X]

A, [X]

A, #

A

M

#, [X]

#, M

A, M

X, #

Z,N

C,H

X, #

ST

A, [#,X]

A, [X]

A, M

None

Z,N

IFNBIT

IFNC

IFNE

INC

#, A

ST

#, M

ST

#, [X]

STC

SUBC

XOR

#, M

A, [X]

A, [#,X]

A, M

C,H,Z,N

Z,N

A, [#, X]

A, [X]

A, #

A, M

X, #

M, #

A

A, #

A, [X]

A, [#,X]

A, M

Z,N

A, #

Z,N

INC

M

Z,N

11

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ACE1502 Product Family Rev. 1.7

3.4 Memory Map

All I/O ports, peripheral registers, and core registers (except the accumulator and the program counter) are mapped into the memory

space.

Table 10. Memory Mapped Registers

Address

0x00 - 0x3F

0x40 - 0x7F

0x80-0x9F

0xA0

Memory Space

Data

Block

SRAM

EEPROM

Reserved

HBC

Contents

Data RAM

Data

Data EEPROM

Data

HBCNTRL register

PSCALE register

HPATTERN register

LPATTERN register

BPSEL register

0xA1

Data

HBC

0xA2

Data

HBC

0xA3

Data

HBC

0xA4

Data

HBC

0xA7

Data

Timer1

HBC

T1RBLO register

T1RBHI register

DAT0 register

0xA8

Data

0xA9

Data

0xAA

Data

Timer1

MIW

T1RALO register

T1RAHI register

TMR1LO register

TMR1HI register

T1CNTRL register

WKEDG register

WKPND register

WKEN register

0xAB

Data

0xAC

Data

0xAD

Data

0xAE

Data

0xAF

Data

0xB0

Data

MIW

0xB1

Data

MIW

0xB2

Data

I/O

PORTGD register

PORTGC register

PORTGP register

WDSVR register

T0CNTRL register

HALT mode register

0xB3

Data

I/O

0xB4

Data

I/O

0xB5

Data

Timer0

Clock

0xB6

Data

0xB7

Data

0xB8-0xBA

0xBB

Data

Reserved

Init. Register

LBD

Data

Initialization Register 1

Initialization Register 2

LBD register

0xBC

Data

0xBD

Data

0xBE

Data

Core

XHI register

0xBF

Data

Core

XLO register

0xC0

Data

Clock

Power Mode Clear (PMC) Register

SP register

0xCE

Data

Core

0xCF

Data

Core

Status register (SR)

0xD0 - 0xFF

0x800 - 0xFF5

0xFF6 - 0xFF7

0xFF8 - 0xFF9

0xFFA - 0xFFB

0xFFC - 0xFFD

0xFFE - 0xFFF

Data

Reserved

EEPROM

Core

Program

Code EEPROM

Timer0 Interrupt vector

Timer1 Interrupt vector

MIW Interrupt vector

Soft Interrupt vector

Core

Reserved

12

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ACE1502 Product Family Rev. 1.7

read, write, or enter HALT/IDLE mode while the data EEPROM

is busy (R = 0) can affect the current data being written.

3.5 Memory

The ACEx microcontroller has 64 bytes of SRAM and 64 bytes

of EEPROM available for data storage. The device also has 2K

bytes of EEPROM for program storage. Software can read and

write to SRAM and data EEPROM but can only read from the

code EEPROM. While in normal mode, the code EEPROM is

protected from any writes. The code EEPROM can only be

rewritten when the device is in program mode and if the write

disable (WDIS) bit of the initialization register is not set to 1.

3.6 Initialization Registers

The ACEx microcontroller has two 8-bit wide initialization

registers. These registers are read from the memory space on

power-up to initialize certain on-chip peripherals. Figure 14

provides a detailed description of Initialization Register 1. The

Initialization Register 2 is used to trim the internal oscillator to

its appropriate frequency. This register is pre-programmed in

the factory to yield an internal instruction clock of 1MHz.

While in normal mode, the user can write to the data EEPROM

array by 1) polling the ready (R) ﬂag of the SR, then 2) execut-

ing the appropriate instruction. If the R ﬂag is 1, the data

EEPROM block is ready to perform the next write. If the R ﬂag is

0, the data EEPROM is busy. The data EEPROM array will

reset the R ﬂag after the completion of a write cycle. Attempts to

The Initialization Registers 1 and 2 can be read from and written

to during programming mode. However, re-trimming the inter-

nal oscillator (writing to the Initialization Register 2) once it has

left the factory is discouraged.

Figure 14. Initialization Register 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CMODE[0]

CMODE[1]

WDEN

BOREN

LDBEN

UBD

WDIS

RDIS

(0) RDIS

If set, disables attempts to read the contents from the memory while in programming mode. Once this bit is

set, it is no longer possible to unset this option even though the write disable option is not enabled.

(1) WDIS

If set, disables attempts to write new contents to the memory while in programming mode

If set, the device will not allow any writes to occur in the upper block of data EEPROM (0x60-0x7F)

If set, the Low Battery Detection circuit is enabled

(2) UBD

(3) LBDEN

(4) BOREN

(5) WDEN

(6) CMODE[1]

(7) CMODE[0]

If set, allows a BOR to occur if Vcc falls below the voltage reference level

If set, enables the on-chip processor watchdog circuit

Clock mode select bit 1 (See Table 16)

Clock mode select bit 0 (See Table 16)

4. Timer 1

Timer 1 is a versatile 16-bit timer that can operate in one of four

modes:

The timer can be started or stopped through the T1CNTRL reg-

ister bit T1C0. When running, the timer counts down (decre-

ments) every clock cycle. Depending on the operating mode,

the timer’s clock is either the instruction clock or a transition on

the T1 input. In addition, occurrences of timer underﬂow (transi-

tions from 0x0000 to 0xFFFF/T1RA/T1RB value) can either

generate an interrupt and/or toggle the T1 output pin.

•

Pulse Width Modulation (PWM) mode, which generates

pulses of a speciﬁed width and duty cycle

External Event Counter mode, which counts occurrences of

an external event

Standard Input Capture mode, which measures the elapsed

time between occurrences of external events

Timer 1’s interrupt (TMRI1) can be enabled by interrupt enable

(T1EN) bit in the T1CNTRL register. When the timer interrupt is

enabled, depending on the operating mode, the source of the

interrupt is a timer underﬂow and/or a timer capture.

Difference Input Capture mode, which automatically mea-

sures the difference between edges.

Timer 1 contains a 16-bit timer/counter register (TMR1), a 16-bit

auto-reload/capture register (T1RA), a secondary 16-bit auto-

reload register (T1RB), and an 8-bit control register

(T1CNTRL). All register are memory-mapped for simple access

through the core with both the 16-bit registers organized as a

pair of 8-bit register bytes {TMR1HI, TMR1LO}, {T1RAHI,

T1RALO}, and {T1RBHI, T1RBLO}. Depending on the operating

mode, the timer contains an external input or output (T1) that is

multiplexed with the I/O pin G2. By default, the TMR1 is reset to

0xFFFF, T1RA/T1RB is reset to 0x0000, and T1CNTRL is reset

to 0x00.

4.1 Timer control bits

Reading and writing to the T1CNTRL register controls the

timer’s operation. By writing to the control bits, the user can

enable or disable the timer interrupts, set the mode of operation,

and start or stop the timer. The T1CNTRL register bits are

described in Table 11 and Table 12.

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ACE1502 Product Family Rev. 1.7

Table 11.Timer 1 Control Register (T1CNTRL)

T1CNTRL Register

Bit Name

T1C3

Function

Bit 7

Bit 6

Bit 5

Bit 4

Timer TIMER1 control bit 3 (see Table 12)

T1C2

Timer TIMER1 control bit 2 (see Table 12)

Timer TIMER1 control bit 1 (see Table 12)

T1C1

T1C0

Timer TIMER1 run: 1= Start timer, 0 = Stop timer;

or Timer TIMER1 underﬂow interrrupt pending ﬂag in input capture mode

Bit 3

Bit 2

T1PND

T1EN

Timer1 interrupt pending ﬂag: 1 = Timer1 interrupt

Pending, 0 = Timer1 interrupt not pending

Timer1 interrupt enable bit: 1 = Timer1 interrupt enabled,

0 = Timer1 interrupt disabled

Bit 1

Bit 0

M1S1

Capture type: 0 = Pulse capture, 1 = Cycle capture (see Table 12)

T1RBEN

PWM Mode: 0 = Timer1 reload on T1RA, 1 = TIMER1 reload on T1RA and T1RB

(always starting with T1RA)

Table 12.Timer 1 Operating Modes

T1

C3

T1

C2

T1

C1

M4

S1 RB

T1

Timer Mode Source

MODE 2

Interrupt

TIMER1 Underﬂow

Autoreload T1RA

Timer Counts-on

T1 Pos. Edge

0

1

0

1

0

1

0

1

0

X

0

1

X

MODE 2

T1 Neg. Edge

MODE 1 T1 Toggle

MODE 1 No T1 Toggle

MODE 1 T1 Toggle

MODE 1 No T1 Toggle

Instruction Clock

Autoreload T1RA

Autoreload T1RA/T1RB

Pos. T1 Edge

MODE 3 Captures:

T1 Pos Edge

0

1

X

MODE 3 Captures:

T1 Neg Edge

Neg. T1 Edge

Instruction Clock

1

0

1

0

1

0

1

X

MODE 4

Pos. to Neg.

Pos. to Pos.

Neg. to Pos.

Neg. to Neg.

Instruction Clock

4.2 Mode 1: Pulse Width Modulation (PWM) Mode

In the PWM mode, the timer counts down at the instruction

clock rate. When an underﬂow occurs, the timer register is

reloaded from T1RA/T1RB and the count down proceeds from

the loaded value. At every underﬂow, a pending ﬂag (T1PND)

located in the T1CNTRL register is set. Software must then

clear the T1PND ﬂag and load the T1RA/T1RB register with an

alternate PWM value (if desired.) In addition, the timer can be

conﬁgured to toggle the T1 output bit upon underﬂow. Conﬁgur-

ing the timer to toggle T1 results in the generation of a signal

outputted from port G2 with the width and duty cycle controlled

by the values stored in the T1RA/T1RB. A block diagram of the

timer’s PWM mode of operation is shown in Figure 15.

the T1RA and T1RB registers. A hardware select logic is imple-

mented to select between T1RA and T1RB alternately, always

starting with T1RA, every timer underﬂows to auto-reload the

timer registers. This feature is useful when a signal with variable

duty cycle needs to be generated without software intervention.

The timer has one interrupt (TMRI1) that is maskable through

the T1EN bit of the T1CNTRL register. However, the core is only

interrupted if the T1EN bit and the G (Global Interrupt enable)

bit of the SR is set. If interrupts are enabled, the timer will gen-

erate an interrupt each time T1PND ﬂags is set (whenever the

timer underﬂows provided that the pending ﬂag was cleared.)

The interrupt service routine is responsible for proper handling

of the T1PND ﬂag and the T1EN bit.

The PWM timer can be conﬁgured to use the T1RA register only

for auto-reloading the timer registers or can be conﬁgured to

use both T1RA and T1RB alternately. If the T1RBEN bit of the

T1CNTRL register is 0, the PWM timer will reload using only

T1RA ignoring any value store in the T1RB register. However, if

the T1RBEN bit is 1 the PWM timer will be reloaded using both

The interrupt will be synchronous with every rising and falling

edge of the T1 output signal. Generating interrupts only on ris-

ing or falling edges of T1 is achievable through appropriate han-

dling of the T1EN bit or T1PND ﬂag through software.

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ACE1502 Product Family Rev. 1.7

The following steps show how to properly conﬁgure Timer 1 to

operate in the PWM mode. For this example, the T1 output sig-

nal is toggled with every timer underﬂow and the “high” and

“low” times for the T1 output can be set to different values. The

T1 output signal can start out either high or low depending on

the conﬁguration of G2; the instructions below are for starting

with the T1 output high. Follow the instructions in parentheses

to start the T1 output low.

4.3 Mode 2: External Event Counter Mode

The External Event Counter mode operates similarly to the

PWM mode; however, the timer is not clocked by the instruction

clock but by transitions of the T1 input signal. The edge is

selectable through the T1C1 bit of the T1CNTRL register. A

block diagram of the timer’s External Event Counter mode of

operation is shown in Figure 16.

The T1 input should be connected to an external device that

generates a positive/negative-going pulse for each event. By

clocking the timer through T1, the number of positive/negative

transitions can be counted therefore allowing software to cap-

ture the number of events that occur. The input signal on T1

must have a pulse width equal to or greater than one instruction

clock cycle.

1. Conﬁgure T1 as an output by setting bit 2 of PORTGC.

- SBIT 2, PORTGC

; Conﬁgure G2 as an output

2. Initialize T1 to 1 (or 0) by setting (or clearing) bit 2 of

PORTGD.

- SBIT 2, PORTGD

; Set G2 high

3. Load the initial PWM high (low) time into the timer register.

- LD TMR1LO, #6FH

(1MHz clock)

; High (Low) for 1.391ms

The counter can be conﬁgured to sense either positive-going or

negative-going transitions on the T1 pin. The maximum fre-

quency at which transitions can be sensed is one-half the fre-

quency of the instruction clock.

- LD

TMR1HI, #05H

4. Load the PWM low (high) time into the T1RA register.

- LD T1RALO, #2FH

(1MHz clock)

- LD T1RAHI, #01H

; Low (High) for .303ms

As with the PWM mode, when the counter underﬂows the

counter is reloaded from the T1RA register and the count down

proceeds from the loaded value. At every underﬂow, a pending

ﬂag (T1PND) located in the T1CNTRL register is set. Software

must then clear the T1PND ﬂag and can then load the T1RA

register with an alternate value.

5. Write the appropriate control value to the T1CNTRL register

to select PWM mode with T1 toggle, to clear the enable bit

and pending ﬂag, and to start the timer. (See Table 11 and

Table 12.)

The counter has one interrupt (TMRI1) that is maskable through

the T1EN bit of the T1CNTRL register. However, the core is only

interrupted if the T1EN bit and the G (Global Interrupt enable)

bit of the SR is set. If interrupts are enabled, the counter will

generate an interrupt each time the T1PND ﬂag is set (when-

ever timer underﬂows provided that the pending ﬂag was

cleared.) The interrupt service routine is responsible for proper

handling of the T1PND ﬂag and the T1EN bit.

- LD T1CNTRL, #0B0H ; Setting the T1C0 bit starts the

timer

6. After every underﬂow, load T1RA with alternate values. If the

user wishes to generate an interrupt on a T1 output transi-

tion, reset the pending ﬂags and then enable the interrupt

using T1EN. The G bit must also be set. The interrupt

service routine must reset the pending ﬂag and perform

whatever processing is desired.

The following steps show how to properly conﬁgure Timer 1 to

operate in the External Event Counter mode. For this example,

the counter is clocked every falling edge of the T1 input signal.

Follow the instructions in parentheses to clock the counter every

rising edge.

- RBIT T1PND, T1CNTRL ; T1PND equals 3

- LD T1RALO, #6FH

(1MHz clock)

; High (Low) for 1.391ms

- LD T1RAHI, #05H

1. Conﬁgure T1 as an input by clearing bit 2 of PORTGC.

Figure 15. Pulse Width Modulation Mode

- RBIT

2. Initialize T1 to input with pull-up by setting bit 2 of PORTGD.

- SBIT 2, PORTGD ; Set G2 high

3. Enable the global interrupt enable bit.

- SBIT 4, STATUS

2, PORTGC

; Conﬁgure G2 as an input

16-bit Auto-Reload

Register (T1RA)

0

1

S

4. Load the initial count into the TMR1 and T1RA registers.

When the number of external events is detected, the counter

will reach zero; however, it will not underﬂow until the next

event is detected. To count N pulses, load the value N-1 into

the registers. If it is only necessary to count the number of

occurrences and no action needs to be taken at a particular

count, load the value 0xFFFF into the registers.

16-bit Auto-Reload

Register (T1RB)

Data

Bus

Reload select logic

T1RBEN

- LD

TMR1LO, #0FFH

TMR1HI, #0FFH

T1RALO, #0FFH

T1RAHI, #0FFH

Data

Latch

16-bit Timer (TMR1)

T1

Underflow

Instruction

Clock

Interrupt

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ACE1502 Product Family Rev. 1.7

5. Write the appropriate control value to the T1CNTRL register

to select External Event Counter mode, to clock every falling

edge, to set the enable bit, to clear the pending ﬂag, and to

start the counter. (See Table 11 and Table 12 )

- LD T1CNTRL, #34H (#00h) ;Setting the T1C0 bit starts

the timer

For this operating mode, the T1C0 control bit serves as the

timer underﬂow interrupt pending ﬂag.The Timer 1 interrupt ser-

vice routine must read both the T1PND and T1C0 ﬂags to deter-

mine the cause of the interrupt. A set T1C0 ﬂag means that a

timer underﬂow occurred whereas a set T1PND ﬂag means that

a capture occurred in T1RA. It is possible that both ﬂags will be

found set, meaning that both events occurred at the same time.

The interrupt service routine should take this possibility into

consideration.

6. When the counter underﬂows, the interrupt service routine

must clear the T1PND ﬂag and take whatever action is

required once the number of events occurs. If the software

wishes to merely count the number of events and the antici-

pated number may exceed 65,536, the interrupt service

routine should record the number of underﬂows by incre-

menting a counter in memory. Software can then calculate

the correct event count.

Because the T1C0 bit is used as the underﬂow interrupt pend-

ing ﬂag, it is not available for use as a start/stop bit as in the

other modes.

The TMR1 register counts down continuously at the instruction

clock rate starting from the time that the input capture mode is

selected. (See Table 11 and Table 12) To stop the timer from

running, you must change the mode to an alternate mode

(PWM or External Event Counter) while resetting the T1C0 bit.

- RBIT T1PND, T1CNTRL ; T1PND equals 3

Figure 16. External Event Counter Mode

The input pins can be independently conﬁgured to sense posi-

tive-going or negative-going transitions. The edge sensitivity of

pin T1 is controlled by bit T1C1 as indicated in Table 12.

16-bit Auto-Reload

Register (T1RA)

Data

Bus

The edge sensitivity of a pin can be changed without leaving the

input capture mode even while the timer is running. This feature

allows you to measure the width of a pulse received on an input

pin.

Underflow

Interrupt

16-bit Counter (TMR1)

For example, the T1 pin can be programmed to be sensitive to a

positive-going edge. When the positive edge is sensed, the

TMR1 register contents is transferred to the T1RA register and

a Timer 1 interrupt is generated. The Timer 1 interrupt service

routine records the contents of the T1RA register, changes the

edge sensitivity from positive to negative-going edge, and

clears the T1PND ﬂag. When the negative-going edge is sensed

another Timer 1 interrupt is generated. The interrupt service

routine reads the T1RA register again. The difference between

the previous reading and the current reading reﬂects the

elapsed time between the positive edge and negative edge of

the T1 input signal i.e. the width of the positive-going pulse.

T1

Edge Selector

Logic

4.4 Mode 3: Input Capture Mode

In the Input Capture mode, the timer is used to measure

elapsed time between edges of an input signal. Once the timer

is conﬁgured for this mode, the timer starts counting down

immediately at the instruction clock rate. The Timer 1 will then

transfer the current value of the TMR1 register into the T1RA

register as soon as the selected edge of T1 is sensed. The input

signal on T1 must have a pulse width equal to or greater than

one instruction clock cycle. At every T1RA capture, software

can then store the values into RAM to calculate the elapsed

time between edges on T1. At any given time (with proper con-

sideration of the state of T1) the timer can be conﬁgured to cap-

ture on positive-going or negative-going edges. A block diagram

of the timer’s Input Capture mode of operation is shown in Fig-

ure 17.

Remember that the Timer1 interrupt service routine must test

the T1C0 and T1PND ﬂags to determine the cause of the inter-

rupt. If the T1C0 ﬂag caused the interrupt, the interrupt service

routine should record the occurrence of an underﬂow by incre-

menting a counter in memory or by some other means. The

software that calculates the elapsed time between captures

should take into account the number of underﬂow that occurred

when making its calculation.

The following steps show how to properly conﬁgure Timer 1 to

operate in the Input Capture mode.

1. Conﬁgure T1 as an input by clearing bit 2 of PORTGC.

The timer has one interrupt (TMRI1) that is maskable through

the T1EN bit of the T1CNTRL register. However, the core is only

interrupted if the T1EN bit and the G (Global Interrupt enable)

bit of the SR is set. The Input Capture mode contains two inter-

rupt pending ﬂags 1) the TMR1 register capture in T1RA

(T1PND) and 2) timer underﬂow (T1C0). If interrupts are

enabled, the timer will generate an interrupt each time a pend-

ing ﬂag is set (provided that the pending ﬂag was previously

cleared.) The interrupt service routine is responsible for proper

handling of the T1PND ﬂag, T1C0 ﬂag, and the T1EN bit.

- RBIT 2, PORTGC

2. Initialize T1 to input with pull-up by setting bit 2 of PORTGD.

- SBIT 2, PORTGD ; Set G2 high

; Conﬁgure G2 as an input

3. Enable the global interrupt enable bit.

- SBIT 4, STATUS

4. With the timer stopped, load the initial time into the TMR1

register (typically the value is 0xFFFF.)

- LD TMR1LO, #0FFH

- LD TMR1HI, #0FFH

5. Write the appropriate control value to the T1CNTRL register

to select Input Capture mode, to sense the appropriate

edge, to set the enable bit, and to clear the pending ﬂags.

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ACE1502 Product Family Rev. 1.7

(See Table 11 and Table 12)

- LD T1CNTRL, #64H

the standard Input Capture mode both the capture (T1PND) and

the underﬂow (T1C0) ﬂags must be monitored and handled

appropriately. This feature allows the ACEx microcontroller to

capture very small pulses where standard microcontrollers

might have missed cycles due to the limited bandwidth.

; T1C1 is the edge select bit

6. As soon as the input capture mode is enabled, the timer

starts counting. When the selected edge is sensed on T1,

the T1RA register is loaded and a Timer 1 interrupt is

triggered.

Figure 18. Difference Capture Mode

Figure 17. Input Capture Mode

Capture

Interrupt

16-bit Input Capture

Register (T1RA)

Capture

Interrupt

Difference

Logic

16-bit Input Capture

Register (T1RA)

T1

Data

Bus

Edge Selector

Logic

Edge Selector

Data

Bus

Logic

Underflow

Interrupt

16-bit Timer (TMR1)

Underflow

Interrupt

16-bit Timer (TMR1)

Instruction

Clock

Instruction

Clock

4.5 Mode 4: Difference Input Capture Mode

The Difference Input Capture mode works similarly to the stan-

dard Input Capture mode. However, for the Difference Input

Capture the timer automatically captures the elapsed time

between the selected edges without the core needing to per-

form the calculation.

5. Timer 0

Timer 0 is a 12-bit free running idle timer. Upon power-up or any

reset, the timer is reset to 0x000 and then counts up continu-

ously based on the instruction clock of 1MHz (1 µs). Software

cannot read from or write to this timer. However, software can

monitor the timer's pending (T0PND) bit that is set every 8192

cycles (initially 4096 cycles after a reset). The T0PND ﬂag is set

every other time the timer overﬂows (transitions from 0xFFF to

0x000) through a divide-by-2 circuit. After an overﬂow, the timer

will reset and restart its counting sequence.

For example, the standard Input Capture mode requires that the

timer be conﬁgured to capture a particular edge (rising or fall-

ing) at which time the timer’s value is copied into the capture

register. If the elapsed time is required, software must move the

captured data into RAM and reconﬁgure the Input Capture

mode to capture on the next edge (rising or falling). Software

must then subtract the difference between the two edges to

yield useful information.

Software can either poll the T0PND bit or vector to an interrupt

subroutine. In order to interrupt on a T0PND, software must be

sure to enable the Timer 0 interrupt enable (T0INTEN) bit in the

Timer 0 control (T0CNTRL) register and also make sure the G

bit is set in SR. Once the timer interrupt is serviced, software

should reset the T0PND bit before exiting the routine. Timer 0

supports the following functions:

The Difference Capture mode eliminates the need for software

intervention and allows for capturing very short pulse or cycle

widths. It can be conﬁgured to capture the elapsed time

between:

1. rising edge to falling edge

2. rising edge to rising edge

3. falling edge to rising edge

4. falling edge to falling edge

1. Exiting from IDLE mode (See Section 16 for details.)

2. Start up delay from HALT mode

3. Watchdog pre-scalar (See Section 6 for details.)

The T0INTEN bit is a read/write bit. If set to 0, interrupt requests

from the Timer 0 are ignored. If set to 1, interrupt requests are

accepted. Upon reset, the T0INTEN bit is reset to 0.

Once conﬁgured, the Difference Capture timer waits for the ﬁrst

selected edge. When the edge transition has occurred, the 16-

bit timer starts counting up based every instruction clock cycle.

It will continue to count until the second selected edge transition

occurs at which time the timer stops and stores the elapse time

into the T1RA register.

The T0PND bit is a read/write bit. If set to 1, it indicates that a

Timer 0 interrupt is pending. This bit is set by a Timer 0 overﬂow

and is reset by software or system reset.

The WKINTEN bit is used in the Multi-input Wakeup/Interrupt

block. See Section 8 for details.

Software can now read the difference between transitions

directly without using any processor resources. However, like

Figure 19. Timer 0 Control Register Deﬁnition (T0CNTRL)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WKINTEN

x

T0PND

T0INTEN

17

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ACE1502 Product Family Rev. 1.7

6. Watchdog

The Watchdog timer is used to reset the device and safely

recover in the rare event of a processor “runaway condition.”

The 12-bit Timer 0 is used as a pre-scalar for Watchdog timer.

The Watchdog timer must be serviced before every 61,440

cycles but no sooner than 4096 cycles since the last Watchdog

reset. The Watchdog is serviced through software by writing the

value 0x1B to the Watchdog Service (WDSVR) register (see

Figure 20). The part resets automatically if the Watchdog is ser-

viced too frequent, or not frequent enough.

can only be set while the device is in programming mode. Once

set, the Watchdog will always be powered-up enabled. Software

cannot disable the Watchdog. The Watchdog timer can only be

disabled in programming mode by resetting the WDEN bit as

long as the memory write protect (WDIS) feature is not enabled.

WARNING

Ensure that the Watchdog timer has been serviced before

entering IDLE mode because it remains operational during this

time.

The Watchdog timer must be enabled through the Watchdog

enable bit (WDEN) in the initialization register. The WDEN bit

Figure 20. Watchdog Service Register (WDSVR)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

0

1

7. Hardware Bit-Coder

The Hardware Bit-Coder is a dedicated hardware bit-encoding

peripheral block, Hardware Bit-Coder (HBC), for IR/RF data

transmission (see Figure 21.) The HBC is completely software

programmable and can be conﬁgured to emulate various bit-

encoding formats. The software developer has the freedom to

encode each bit of data into a desired pattern and output the

encoded data at the desired frequency through either the G2 or

G5 output (TX) ports.

pattern bits to be transmitted from each register. Upon a reset,

BPSEL is initially 0 disabling the HBC from transmitting pattern

bits from either register.

The Data (DAT0) register is used to store up to 8 bits of data to

be encoded and transmitted by the HBC. This data is shifted, bit

by bit, MSB to LSB into a 1-bit decision register. If the active bit

shifted into the decision register is 1, the pattern in the HPAT-

TERN register is shifted out of the output port. Similarly, if the

active bit is 0 the pattern in the LPATTERN register is shifted

out.

The HBC contains six 8-bit memory-mapped conﬁguration reg-

isters PSCALE, HPATTERN, LPATTERN, BPSEL, HBCNTRL,

and DAT0. The registers are used to select the transmission fre-

quency, store the data bit-encoding patterns, conﬁgure the data

bit-pattern/frame lengths, and control the data transmission

ﬂow.

The HBC control (HBCNTRL) register is used to conﬁgure and

control the data transmission. HBCNTRL is divided in 5 different

controlling signal FRAME[2:0], IOSEL, TXBUSY, START

STOP, and OCFLAG (see Figure 23.)

/

To select the IR/RF transmission frequency, an 8-bit divide con-

stant must be written into the IR/RF Pre-scalar (PSCALE) regis-

ter. The IR/RF transmission frequency generator divides the

1MHz instruction clock down by 4 and the PSCALE register is

used to select the desired IR/RF frequency shift. Together, the

transmission frequency range can be conﬁgured between

976Hz (PSCALE = 0xFF) and 125kHz (PSCALE = 0x01). Upon

a reset, the PSCALE register is initialized to zero disabling the

IR/RF transmission frequency generator. However, once the

PSCALE register is programmed, the desired IR/RF frequency

is maintained as long as the device is powered.

FRAME[2:0] selects the number of bits of DAT0 to encode and

transmit.The HBC allows from 2 (0x1) to 8 (0x7) DAT0 bits to be

encoded and transmitted. Upon a reset, FRAME is initialized to

zero disabling the DAT0’s decision register transmitting no data.

The IOSEL signal selects the transmission to output (TX)

through either port G2 or G5. If IOSEL is 1, G5 is selected as

the output port otherwise G2 is selected.

The TXBUSY signal is read only and is used to inform software

that a transmission is in progress. TXBUSY goes high when the

encoded data begins to shift out of the output port and will

remains high during each consecutive DAT0 frame bit transmis-

sion (see Figure 25). The HBC will clear the TXBUSY signal

when the last DAT0 encoded bit of the frame is transmitted and

the STOP signal is 0.

Once the transmission frequency is selected, the data bit-

encoding patterns must be stored in the appropriate registers.

The HBC contains two 8-bit bit-encoding pattern registers,

High-pattern (HPATTERN) and Low-pattern (LPATTERN). The

encoding pattern stored in the HPATTERN register is transmit-

ted when the data bit value to be encoded is a 1. Similarly, the

pattern stored in the LPATTERN register is transmitted when the

data bit value to be encoded is a 0. The HBC transmits each

encoded pattern MSB ﬁrst.

The START / STOP signal controls the encoding and transmis-

sion process for each data frame. When software sets the

START / STOP bit the DAT0 frame transmission process begins.

The START signal will remain high until the beginning of the last

encoded DAT0 frame bit transmission. The HBC then clears the

START / STOP bit allowing software to elect to either continue

with a new DAT0 frame transmission or stop the transmission all

together (see Figure 25). If TXBUSY is 0 when the START sig-

nal is enabled, a synchronization period occurs before any data

is transmitted lasting the amount of time to transmit a 0 encoded

bit (see Figure 24).

The number of bits transmitted from the HPATTERN and LPAT-

TERN registers is software programmable through the Bit

Period Conﬁguration (BPSEL) register (see Figure 22). During

the transmission of HPATTERN, the number of bits transmitted

is conﬁgured by BPH[2:0] (BPSEL[2:0]) while BPL[2:0]

(BPSEL[5:3]) conﬁgures the number of transmitted bits for the

LPATTERN. The HBC allows from 2 (0x1) to 8 (0x7) encoding

18

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ACE1502 Product Family Rev. 1.7

The OCFLAG signal is read only and goes high when the last

encoded bit of the DAT0 frame is transmitting.The OCFLAG sig-

nal is used to inform software that the DAT0 frame transmission

operation is completing (see Figure 25). If multiple DAT0 frames

are to be transmitted consecutively, software should poll the

OCFLAG signal for a 1. Once OCFLAG is 1, DAT0 must be

reload and the START / STOP bit must be restored to 1 in order

to begin the new frame transmission without interruptions (the

synchronization period). Since OCFLAG remains high during

the entire last encoded DAT0 frame bit transmission, software

should wait for the HBC to clear the OCFLAG signal before poll-

ing for the new OCFLAG high pulse. If new data is not reloaded

into DAT0 and the START signal (STOP is active) is not set

before the OCFLAG is 0, the transmission process will end

(TXBUSY is cleared) and a new process will begin starting with

the synchronization period.

LD PSCALE, #03H

LD BPSEL, #012H

LD HPATTERN, #0C0H

LD LPATTERN, #090H

LD DAT0, #052H

; (1MHz ?? 4) ?? 4 = 62.5KHz

; BPH = 2, BPL = 2 (3 bits each)

; HPATTERN = 0xC0

; LPATTERN = 0x90

; DAT0 = 0x52

Once the basic registers are initialized, the HBC can be started.

(At the same time, software must set the number of data bits per

data frame and select the desired output port.)

LD HBCNTRL, #27H

; START / STOP = 1,

FRAME = 7, IOSEL = 0

After the HBC has started, software must then poll the OCFLAG

for a high pulse and restore the DAT0 register and the START

signal to continue with the next data transmission.

LOOP_HI:

IFBIT OCFLAG, HBCNTRL

; Wait for OCFLAG = 1

Figure 24 and Figure 25 shows how the HBC performs its data

encoding. In the example, two frames are encoded and trans-

mitted consecutively with the following bit encoding format spec-

iﬁcation:

JP

NXT_FRAME

LOOP_HI

NXT_FRAME:

LD

DAT0, #092H

; DAT0 = 0x92

; START / STOP = 1

1. Transmission frequency = 62.5KHz

SBIT START, HBCNTRL

2. Data to be encoded = 0x52, 0x92 (all 8-bits)

If software is to proceed with another data transmission, the

OCFLAG must be zero before polling for the next OCFLAG high

pulse. However, since the speciﬁcation in the example requires

no other data transmission software can proceed as desired.

3. Each bit should be encoded as a 3-bit binary value,

‘1’ = 110b and ‘0’ = 100b

4. Transmission output port : G2

LOOP_LO:

To perform the data transmission, software must ﬁrst initialize

the PSCALE, BPSEL, HPATTERN, LPATTERN, and DAT0

registers with the appropriate values.

IFBIT OCFLAG, HBCNTRL

; Wait for OCFLAG = 0

JP

LOOP_LO

Etc.

; Program proceeds

as desired

Figure 21. Hardware Bit-coder (HBC) Block Diagram

IR/RF

CLOCK

RFCLK

b7

HPATTERN

LPATTERN

A

B

StopShift

Y

G2

G5

Fixed

Clock Divider

by 4

CPU

CLOCK

PSCALE

RFCLK

b7

StopShift

8

IOSEL

[PSCALE]

HBCNTRL[6]

ShiftCLK

Down

Counter

b7

DAT0

OCFLAG

NoShift

Sync

LOGIC

3

FRAME[2:0]

[HBCNTRL]

OCFLAG

HBCNTRL[7]

START/STOP

HBCNTRL[5]

Y

A

B

TXBUSY

HBCNTRL[4]

3

BPH[2:0]

[BPSEL]

BPL[2:0]

[BPSEL]

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ACE1502 Product Family Rev. 1.7

Figure 22. Bit Period Conﬁguration (BPSEL) Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

BPL[2:0]

BPH[2:0]

Figure 23. HBC Control (HBCNTRL) Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 1

OCFLAG

IOSEL

START / STOP

TXBUSY

0

FRAME[2:0]

Figure 24. HBC signals for one byte message in PWM format

Condition:

BPSEL = 0x12 [ "1", " 0 " = 3 * IR/RF Clocks]

DAT0 = 0x52

No. bit to encode = 8 (HBCNTRL = XXXX0111b)

TXBUSY

START/STOP

ShiftCLK

OCFLAG

Bit 7

"0"

"1"

"0"

"1"

"0"

"1"

DAT0

G2/G5

Output

IR/RF

CLOCK

Figure 25. Sending series of encoded messages

Conditions:

BPSEL = 0x12 [ "1", " 0 " = 3 * IR/RF Clocks]

DAT0 = 0x52 , 0x92

No. bit to encode = 8 (HBCNTRL = XXXX0111b)

Software must set the START bit while OCFLAG is set in

order to send another message without introducing a delay.

TXBUSY

STOP bit clear,

transmission ends.

START/STOP

ShiftCLK

OCFLAG

Bit 7

"0"

"0" "0" "1" "0" "1" "0" "0" "1" "0" "1" "0" "0" "1" "0" "0" "1"

DAT0

G2/G5

Output

IR/RF

CLOCK

20

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ACE1502 Product Family Rev. 1.7

6. Set the WKEN bits associated with the pins to be used, thus

enabling those pins for the Wakeup/Interrupt function.

8. Multi-Input Wakeup/Interrupt Block

The Multi-Input Wakeup (MIW)/Interrupt contains three

memory-mapped registers associated with this circuit: WKEDG

(Wakeup Edge), WKEN (Wakeup Enable), and WKPND

(Wakeup Pending). Each register has 8-bits with each bit

corresponding to an input pins as shown in Figure 27. All three

registers are initialized to zero upon reset.

- LD WKEN, #10H

; Enabling G4

Once the Multi-Input Wakeup/Interrupt function has been con-

ﬁgured, a transition sensed on any of the I/O pins will set the

corresponding bit in the WKPND register. The WKPND bits,

where the corresponding enable (WKEN) bits are set, will bring

the device out of the HALT mode and can also trigger an inter-

rupt if interrupts are enabled. The interrupt service routine can

read the WKPND register to determine which pin sensed the

interrupt.

The WKEDG register establishes the edge sensitivity for each

of the wake-up input pin: either positive going-edge (0) or

negative-going edge (1).

The WKEN register enables (1) or disables (0) each of the port

pins for the Wakeup/Interrupt function. The wakeup I/Os used

for the Wakeup/Interrupt function must also be conﬁgured as an

input pin in its associated port conﬁguration register. However,

an interrupt of the core will not occur unless interrupts are

enabled for the block via bit 7 of the T0CNTRL register (see Fig-

ure 19) and the G (global interrupt enable) bit of the SR is set.

The interrupt service routine or other software should clear the

pending bit. The device will not enter HALT mode as long as a

WKPND pending bit is pending and enabled. The user has the

responsibility of clearing the pending ﬂags before attempting to

enter the HALT mode.

Upon reset, the WKEDG register is conﬁgured to select posi-

tive-going edge sensitivity for all wakeup inputs. If the user

wishes to change the edge sensitivity of a port pin, use the fol-

lowing procedure to avoid false triggering of a Wakeup/Interrupt

condition.

The WKPND register contains the pending ﬂags corresponding

to each of the port pins (1 for wakeup/interrupt pending, 0 for

wakeup/interrupt not pending). If an I/O is not selected to

become a wakeup input, the pending ﬂag will not be generated.

1. Clear the WKEN bit associated with the pin to disable that

pin.

To use the Multi-Input Wakeup/Interrupt circuit, perform the

steps listed below making sure the MIW edge is selected before

enabling the I/O to be used as a wakeup input thus preventing

false pending ﬂag generation. This same procedure should be

used following any type of reset because the wakeup inputs are

left ﬂoating after resets resulting in unknown data on the port

inputs.

2. Clear the WKPND bit associated with the pin.

3. Write the WKEDG register to select the new type of edge

sensitivity for the pin.

4. Set the WKEN bit associated with the pin to re-enable it.

PORTG provides the user with three fully selectable, edge sen-

sitive interrupts that are all vectored into the same service sub-

routine.The interrupt from PORTG shares logic with the wakeup

circuitry. The WKEN register allows interrupts from PORTG to

be individually enabled or disabled. The WKEDG register speci-

ﬁes the trigger condition to be either a positive or a negative

edge. The WKPND register latches in the pending trigger condi-

tions.

1. Clear the WKEN register.

- CLR WKEN

2. Clear the WKPND register to cancel any pending bits.

- CLR WKPND

3. If necessary, write to the port conﬁguration register to select

the desired port pins to be conﬁgured as inputs.

- RBIT 4, PORTGC

; G4

Since PORTG is also used for exiting the device from the HALT

mode, the user can elect to exit the HALT mode either with or

without the interrupt enabled. If the user elects to disable the

interrupt, then the device restarts execution from the point at

which it was stopped (ﬁrst instruction cycle of the instruction fol-

lowing HALT mode entrance instruction). In the other case, the

device ﬁnishes the instruction that was being executed when

the part was stopped and then branches to the interrupt service

routine. The device then reverts to normal operation.

4. If necessary, write to the port data register to select the

desired port pins input state.

- SBIT 4, PORTGD

; Pull-up

5. Write the WKEDG register to select the desired type of edge

sensitivity for each of the pins used.

- LD

WKEDG, #0FFH

; All negative-going edges

Figure 26. Multi-input Wakeup (MIW) Register bit assignments

WKEDG, WKEN, WKPND

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

9

G7

G6

G5

G4

G3

G2

G1

G0

9. Available only on the 14-pin package option

21

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ACE1502 Product Family Rev. 1.7

Figure 27. Multi-input Wakeup (MIW) Block Diagram

Data Bus

7

0

WKEN[7:0]

0

G0

G7

WKOUT

EDGEI

7

WKINTEN¹⁰

WKPND[0:7]

WKEDG[0:7]

10.

WKINTEN: Bit 7 of T0CNTRL

9. I/O Port

The eight I/O pins (six on 8-pin package option) are bi-

directional (see Figure 28). The bi-directional I/O pins can be

individually conﬁgured by software to operate as high-

impedance inputs, as inputs with weak pull-up, or as push-pull

outputs. The operating state is determined by the contents of

the corresponding bits in the data and conﬁguration registers.

Each bi-directional I/O pin can be used for general purpose I/O,

or in some cases, for a speciﬁc alternate function determined by

the on-chip hardware.

9.1 I/O registers

The I/O pins (G0-G7) have three memory-mapped port regis-

ters associated with the I/O circuitry: a port conﬁguration regis-

ter (PORTGC), a port data register (PORTGD), and a port input

register (PORTGP). PORTGC is used to conﬁgure the pins as

inputs or outputs. A pin may be conﬁgured as an input by writing

a 0 or as an output by writing a 1 to its corresponding PORTGC

bit. If a pin is conﬁgured as an output, its PORTGD bit repre-

sents the state of the pin (1 = logic high, 0 = logic low). If the pin

is conﬁgured as an input, its PORTGD bit selects whether the

pin is a weak pull-up or a high-impedance input. Table 13 pro-

vides details of the port conﬁguration options. The port conﬁgu-

ration and data registers can both be read from or written to.

Reading PORTGP returns the value of the port pins regardless

of how the pins are conﬁgured. Since this device supports MIW,

PORTG inputs have Schmitt triggers.

Figure 28. PORTGD Logic Diagram

GXPULLEN

GXBUFEN

GX

GXOUT

GXIN

Figure 29. I/O Register bit assignments

PORTGC, PORTGD, PORTGD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

11

12

G7

G6

G5

G4

G3

G2

G1

G0

11. Available only on the 14-pin package option

12. G3 after reset is an input with weak pull-up

Table 13. I/O conﬁguration options

Conﬁguration Bit

Data Bit

Port Pin Conﬁguration

0

1

0

1

0

1

High-impedence input (TRI-STATE input)

Input with pull-up (weak one input)

Push-pull zero output

Push-pull one output

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ACE1502 Product Family Rev. 1.7

10. In-circuit Programming Speciﬁcation

The ACEx microcontroller supports in-circuit programming of

the internal data EEPROM, code EEPROM, and the initializa-

tion registers.

SHIFT_OUT pin. It is recommended that the external program-

mer samples this signal t (500 ns) after the rising edge

of the CLOCK signal. The serial response word, sent immedi-

ately after entering programming mode, contains indeterminate

data.

ACCESS

In order to enter into program mode a 10-bit opcode (0x34B)

must be shifted into the ACE1502 while the device is executing

the internal power on reset (T

lows the same timing rules as the programming protocol deﬁned

in Figure 30.

). The shifting protocol fol-

After 32 bits have been shifted into the device, the external pro-

grammer must set the LOAD signal to 0V, and then apply two

clock pulses as shown in Figure 30 to complete program cycle.

RESET

The opcode is shifted into the ACE1502 serially, MSB ﬁrst, with

the data being valid by the rising edge of the clock. Once the

pattern is shifted into the device, the current 10-bit pattern is

matched to protocol entrance opcode of 0x34B. If the 10-bit

pattern is a match, the device will enable the internal program

mode ﬂag so that the device will enter into program mode once

reset has completed (see Figure 30.)

The SHIFT_OUT pin acts as the handshaking signal between

the device and programming hardware once the LOAD signal is

brought low. The device sets SHIFT_OUT low by the time the

programmer has sent the second rising edge during the LOAD

= 0V phase (if the timing speciﬁcations in Figure 30 are

obeyed).

The device will set the R bit of the Status register when the write

operation has completed. The external programmer must wait

for the SHIFT_OUT pin to go high before bringing the LOAD sig-

nal to Vcc to initiate a normal command cycle.

The opcode must be shifted in after Vcc settles to the nominal

level and should end before the power on reset sequence

(T

) completes; otherwise, the device will start normal

reset

execution of the program code. If the external reset is applied by

bringing the reset pin low, once the reset pin is release the

opcode may now be shifted in and again should end before the

reset sequence completes.

10.3.2 Read Sequence

When reading the device after a write, the external programmer

must set the LOAD signal to Vcc before it sends the new com-

mand word. Next, the 32-bit serial command word (for during a

READ) should be shifted into the device using the SHIFT_IN

and the CLOCK signals while the data from the previous com-

mand is serially shifted out on the SHIFT_OUT pin. After the

Read command has been shifted into the device, the external

programmer must, once again, set the LOAD signal to 0V and

apply two clock pulses as shown in Figure 30 to complete

READ cycle. Data from the selected memory location, will be

latched into the lower 8 bits of the command word shortly after

the second rising edge of the CLOCK signal.

10.3 Programming Protocol

After placing the device in program, the programming protocol

and commands may be issued.

An externally controlled four-wire interface consisting of a LOAD

control pin (G3), a serial data SHIFT-IN input pin (G4), a serial

data SHIFT-OUT output pin (G2), and a CLOCK pin (G1) is

used to access the on-chip memory locations. Communication

between the ACEx microcontroller and the external programmer

is made through

a 32-bit command and response word

described in Table 14. Be sure to either ﬂoat or tie G5 to Vcc for

proper programming functionality.

Writing a series of bytes to the device is achieved by sending a

series of Write command words while observing the devices

handshaking requirements.

The serial data timing for the four-wire interface is shown in Fig-

ure 31 and the programming protocol is shown in Figure 30.

Reading a series of bytes from the device is achieved by send-

ing

a series of Read command words with the desired

10.3.1 Write Sequence

addresses in sequence and reading the following response

words to verify the correct address and data contents.

The external programmer brings the ACEx microcontroller into

programming then needs to set the LOAD pin to Vcc before

shifting in the 32-bit serial command word using the SHIFT_IN

and CLOCK signals. By deﬁnition, bit 31 of the command word

is shifted in ﬁrst. At the same time, the ACEx microcontroller

shifts out the 32-bit serial response to the last command on the

The addresses of the data EEPROM and code EEPROM

locations are the same as those used in normal operation.

Powering down the device will cause the part to exit program-

ming mode.

Table 14 32-Bit Command and Response Word

Bit Number

bits 31-30

bit 29

Input Command Word

Output Response Word

Must be set to 0

X

Set to 1 to read/write data EEPROM, or the initialization

registers, otherwise 0

X

bit 28

Set to 1 to read/write code EEPROM, otherwise 0

Must be set to 0

X

bits 27-25

bit 24

X

Set to 1 to read, 0 to write

X

bits 23-19

bits 18 -8

bits 7-0

Must be set to 0

X

Address of the byte to be read or written

Data to be programmed or zero if data is to be read

Same as Input command word

Programmed data or data read at speciﬁed address

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ACE1502 Product Family Rev. 1.7

13

Figure 30. Programming Protocol

A

VCC

T_reset

RESET

A

t_load1t_load2

t_ready

t_load3t_load4

LOAD (G3)

32 clock pulses

CLOCK (G1)

1

0

1

0

1

0

1

SHIFT_IN (G4)

bit 31

bit 30

bit 0

bit 31

10-bit Opcode = 0x34B

BUSY low by

2nd clock pulse

READY

SHIFT_OUT (G2)

(in write mode)

BUSY

SHIFT_OUT (G2)

(in read mode)

A: start of programming cycle

13. During in-circuit programming, G5 must be either not connected or driven high.

Figure 31. Serial Data Timing

t_HI

t_LO

CLOCK (G1)

t_DIS

t_DIH

Valid

SHIFT_IN (G4)

t_DOS

t_DOH

Valid

SHIFT_OUT (G2)

t_ACCESS

11. Brown-out/Low Battery Detect Circuit

The Brown-out Reset (BOR) and Low Battery Detect (LBD)

circuits on the ACEx microcontroller have been designed to

offer two types of voltage reference comparators. The sections

below will describe the functionality of both circuits.

Figure 32. BOR/LBD Block Diagram

+1.8V

Vref

_

BOR

to RESET logic

+

0

Vcc

1

G4

S

_

LBD

+

Adjust Reference Voltage

LBD

Control

Register

7

6

5

4

3

2

1

X

0

LBD

BL[4]

BL[3]

BL[2]

BL[1]

BL[0]

VSEL

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ACE1502 Product Family Rev. 1.7

Vcc does not fall below ~1.5V.The Power-on Reset circuit works

best when Vcc starts from zero and rises sharply. In applica-

tions where Vcc is not constant, the BOR will give added device

stability.

11.1 Brown-out Reset

The Brown-out Reset (BOR) function is used to hold the device

in reset when Vcc drops below a ﬁxed threshold (1.83V.) While

in reset, the device is held in its initial condition until Vcc rises

above the threshold value. Shortly after Vcc rises above the

threshold value, an internal reset sequence is started. After the

reset sequence, the core fetches the ﬁrst instruction and starts

normal operation.

The BOR circuit must be enabled through the BOR enable bit

(BOREN) in the initialization register. The BOREN bit can only

be set while the device is in programming mode. Once set, the

BOR will always be powered-up enabled. Software cannot dis-

able the BOR. The BOR can only be disabled in programming

mode by resetting the BOREN bit as long as the global write

protect (WDIS) feature is not enabled.

The BOR should be used in situations when Vcc rises and falls

slowly and in situations when Vcc does not fall to zero before

rising back to operating range. The Brown-out Reset can be

thought of as a supplement function to the Power-on Reset if

Figure 33. BOR and POR Circuit Relationship Diagram

Vcc (Pin8)

BOR

output

VCC

1.75

0

VCC

0

Reset

circuit

output

Global Reset

to Logic

Time

BOR Output

A

POR

External

Reset

B

(14-Pin Only)

output

VCC

The Reset circuit will trigger

when inputs A or B transition

from High to Low. At that time

the Global Reset signal will go

high which will reset all

controller logic. The Global

Reset will go high and stay high

for around 1us.

5.0V

1.8V

(Pin 7)

0

VCC

POR

POR Output

Pulse

output

0

resetting the LBDEN bit as long as the global write protect

(WDIS) feature is not enabled.

11.2 Low Battery Detect

The Low Battery Detect (LBD) circuit allows software to monitor

the Vcc level at the lower voltage ranges. LBD has a 32-level

software programmable voltage reference threshold that can be

changed on the ﬂy. Once Vcc falls below the selected threshold,

the LBD ﬂag in the LBD control register is set. The LBD ﬂag will

hold its value until Vcc rises above the threshold. (See Table 15)

The LBD circuit is disabled during HALT/IDLE mode. After exit-

ing HALT/IDLE, software must wait at lease 10 µs before read-

ing the LBD bit to ensure that the internal circuit has stabilized.

The LBD bit is read only. If LBD is 0, it indicates that the Vcc

level is higher than the selected threshold. If LBD is 1, it indi-

cates that the Vcc level is below the selected threshold. The

threshold level can be adjusted up to eight levels using the three

trim bits (BL[4:0]) of the LBD control register. The LBD ﬂag does

not cause any hardware actions or an interruption of the proces-

sor. It is for software monitoring only.

The VSEL bit of the LBD control register can be used to select

an external voltage source rather than Vcc. If VSEL is 1, the

voltage source for the LBD comparator will be an input voltage

provided through G4. If VSEL is 0, the voltage source will be

Vcc.

The LBD circuit must be enabled through the LBD enable bit

(LBDEN) in the initialization register. The LBDEN bit can only be

set while the device is in programming mode. Once set, the LBD

will always be powered-up enabled. Software cannot disable the

LBD. The LBD can only be disabled in programming mode by

25

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ACE1502 Product Family Rev. 1.7

Table 15. LBD Control Register Deﬁnition

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

VSEL

X

LBD

BL[4:0]

Level

BL[4]

BL[3]

BL[2]

BL[1]

BL[0]

Voltage Reference Range (Typical)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.81V

1.87V

1.93V

1.99V

2.05V

2.11V

2.17V

2.23V

2.29V

2.36V

2.42V

2.48V

2.54V

2.60V

2.66V

2.72V

2.77V

2.84V

2.91V

2.97V

3.03V

3.09V

3.16V

3.22V

3.28V

3.34V

3.41V

3.47V

3.54V

3.60V

3.67V

3.73V

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

26

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ACE1502 Product Family Rev. 1.7

12. RESET block

When a RESET sequence is initiated, all I/O registers will be

reset setting all I/Os to high-impedence inputs. The system

clock is restarted after the required clock start-up delay. A reset

is generated by any one of the following four conditions:

•

Power-on Reset (as described in Section 13)

Brown-out Reset (as described in Section 11.1)

Watchdog Reset (as described in Section 6)

18

External Reset (as described in Section 13)

18. Available only on the 14-pin package option

13. Power-On Reset

The Power-On Reset (POR) circuit is guaranteed to work if the

rate of rise of Vcc is no slower than 10ms/1volt. The POR circuit

was designed to respond to fast low to high transitions between

0V and Vcc. The circuit will not work if Vcc does not drop to 0V

before the next power-up sequence. In applications where 1)

the Vcc rise is slower than 10ms/1 volt or 2) Vcc does not drop

to 0V before the next power-up sequence the external reset

option should be used.

The external reset provides a way to properly reset the ACEx

microcontroller if POR cannot be used in the application. The

external reset pin contains an internal pull-up resistor. There-

fore, to reset the device the reset pin should be held low for at

least 2ms so that the internal clock has enough time to stabilize.

14. CLOCK

The ACEx microcontroller has an on-board oscillator trimmed to

a frequency of 2MHz who is divided down by two yielding a

1MHz frequency. (See AC Electrical Characteristics) Upon

power-up, the on-chip oscillator runs continuously unless enter-

ing HALT mode or using an external clock source.

Figure 34. Crystal

CKI

CKO

If required, an external oscillator circuit may be used depending

on the states of the CMODE bits of the initialization register.

(See Table 16) When the device is driven using an external

clock, the clock input to the device (G1/CKI) can range between

DC to 4MHz. For external crystal conﬁguration, the output clock

(CKO) is on the G0 pin. (See Figure 34.) If the device is conﬁg-

ured for an external square clock, it will not be divided.

R2

R1

Table 16. CMODEx Bit Deﬁnition

C2

C1

CMODE [1] CMODE [0]

Clock Type

Internal 1 MHz clock

External square clock

External crystal/resonator

Reserved

0

1

0

1

0

1

15. HALT Mode

The HALT mode is a power saving feature that almost com-

pletely shuts down the device for current conservation. The

device is placed into HALT mode by setting the HALT enable bit

(EHALT) of the HALT register through software using only the

“LD M, #” instruction. EHALT is a write only bit and is automati-

cally cleared upon exiting HALT. When entering HALT, the inter-

nal oscillator and all the on-chip systems including the LBD and

the BOR circuits are shut down.

The device can exit HALT mode only by the MIW circuit. There-

fore, prior to entering HALT mode, software must conﬁgure the

MIW circuit accordingly. (See Section 8) After a wakeup from

HALT, a 1ms start-up delay is initiated to allow the internal oscil-

lator to stabilize before normal execution resumes. Immediately

after exiting HALT, software must clear the Power Mode Clear

(PMC) register by only using the “LD M, #” instruction. (See Fig-

ure 36)

Figure 35. HALT Register Deﬁnition

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Undeﬁned

undeﬁned

EIDLE

EHALT

27

www.fairchildsemi.com

ACE1502 Product Family Rev. 1.7

Figure 36. Recommended HALT Flow

Normal Mode

LD HALT, #01H

Multi-Input

HALT Mode

Wakeup

LD PMC, #00H

Resume Normal

Mode

16. IDLE Mode

In addition to the HALT mode power saving feature, the device

also supports an IDLE mode operation. The device is placed

into IDLE mode by setting the IDLE enable bit (EIDLE) of the

HALT register through software using only the “LD M, #” instruc-

tion. EIDLE is a write only bit and is automatically cleared upon

exiting IDLE. The IDLE mode operation is similar to HALT

except the internal oscillator, the Watchdog, and the Timer 0

remain active while the other on-chip systems including the LBD

and the BOR circuits are shut down.

The device automatically wakes from IDLE mode by the Timer 0

overﬂow every 8192 cycles (see Section 5). Before entering

IDLE mode, software must clear the WKEN register to disable

the MIW block. Once a wake from IDLE mode is triggered, the

core will begin normal operation by the next clock cycle. Imme-

diately after exiting IDLE mode, software must clear the Power

Mode Clear (PMC) register by using only the “LD M, #” instruc-

tion. (See Figure 37.)

Figure 37. Recommended IDLE Flow

Normal Mode

LD

HALT, #02H

Timer0

Underflow

IDLE Mode

Multi-Input

Wakeup

LD PMC, #00H

Resume Normal

Mode

28

www.fairchildsemi.com

ACE1502 Product Family Rev. 1.7

Ordering Information

Max.#

Program

Operating

Core Type I/Os Memory Size Voltage Range

Package

Tape

&

-40 to -40 to 8-pin 14-pin 8-pin 14-pin 8-pin 14-pin

Part Number

ACE1502EM8

ACE1502EM8X

ACE1502EM

0

1

2

5

X

8

X

1K

2K

X

1.8 – 3.6V

+85°C +125°C SOIC SOIC

DIP

DIP TSSOP TSSOP Reel

X

ACE1502EMX

ACE1502EMT8

ACE1502EMT8X

ACE1502EMT

ACE1502EMTX

ACE1502EN

X

ACE1502EN14

ACE1502VM8

ACE1502VM8X

ACE1502VM

X

ACE1502VMX

ACE1502VMT8

ACE1502VMT8X

ACE1502VMT

ACE1502VMTX

ACE1502VN

X

ACE1502VN14

X

29

www.fairchildsemi.com

ACE1502 Product Family Rev. 1.7

Physical Dimensions inches (millimeters) unless otherwise noted)

0.189 - 0.197

(4.800 - 5.004)

8

7

6

5

0.228 - 0.244

(5.791 - 6.198)

1

2

3

4

Lead #1

IDENT

0.150 - 0.157

(3.810 - 3.988)

0.053 - 0.069

(1.346 - 1.753)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45¡

8¡ Max, Typ.

All leads

Seating

Plane

0.004

(0.102)

All lead tips

0.0075 - 0.0098

(0.190 - 0.249)

Typ. All Leads

0.014

(0.356)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

0.050

(1.270)

Typ

0.014 - 0.020

Typ.

(0.356 - 0.508)

Molded Small Out-Line Package (M8)

Order Number ACE1502EM8/ACE1502VM8

Package Number M08A

0.373 - 0.400

(9.474 - 10.16)

0.090

(2.286)

8

7

0.032 0.005

(0.813 0.127)

RAD

8

7

6

5

4

0.092

(2.337)

DIA

0.250 - 0.005

(6.35 0.127)

Pin #1

IDENT

+

Pin #1 IDENT

1

Option 1

1

2

3

Option 2

0.280

MIN

0.040

(1.016)

Typ.

(7.112)

0.030

0.145 - 0.200

0.039

(0.991)

MAX

(0.762)

0.300 - 0.320

(7.62 - 8.128)

(3.683 - 5.080)

20° 1°

0.130 0.005

(3.302 0.127)

0.125 - 0.140

95° 5°

(3.175 - 3.556)

0.065

(1.651)

0.125

(3.175)

DIA

0.020

90° 4°

Typ

0.009 - 0.015

(0.508)

Min

(0.229 - 0.381)

NOM

0.018 0.003

(0.457 0.076)

+0.040

-0.015

0.325

0.100 0.010

+1.016

-0.381

8.255

(2.540 0.254)

0.045 0.015

(1.143 0.381)

0.060

(1.524)

0.050

(1.270)

8-Pin DIP (N)

Order Number ACE1502EN/ACE1502VN

Package Number N08A

30

www.fairchildsemi.com

ACE1502 Product Family Rev. 1.7

Physical Dimensions inches (millimeters) unless otherwise noted)

0.114 - 0.122

(2.90 - 3.10)

8

5

(7.72) Typ

(4.16) Typ

0.169 - 0.177

(4.30 - 4.50)

0.246 - 0.256

(6.25 - 6.5)

(1.78) Typ

(0.42) Typ

0.123 - 0.128

(3.13 - 3.30)

(0.65) Typ

Land pattern recommendation

1

4

Pin #1 IDENT

0.0433

Max

(1.1)

0.0035 - 0.0079

See detail A

0.002 - 0.006

(0.05 - 0.15)

0.0256 (0.65)

Typ.

Gage

plane

0.0075 - 0.0118

(0.19 - 0.30)

0 -8

DETAIL A

Typ. Scale: 40X

0.0075 - 0.0098

(0.19 - 0.25)

0.020 - 0.028

(0.50 - 0.70)

Seating

plane

Notes: Unless otherwise specified

1. Reference JEDEC registration MO153. Variation AA. Dated 7/93

8-Pin TSSOP

Order Number ACE1502EMT8/ACE1502VMT8

Package Number MT08A

5.0 –0.1

- A -

14

8

(7.72) Typ

(4.16) Typ

4.4 – 0.1

- B -

6.4

(1.78) Typ

(0.42) Typ

3.2

(0.65) Typ

Land pattern recommendation

1

7

0.2

C B A

All Lead Tips

Pin #1 IDENT

1.1 Max

TYP

0.1

C

See detail A

All Lead Tips

(0.9)

0.9 - 0.20 TYP

- C -

0.10 – 0.05 TYP

0.65 Typ.

Gage

plane

0.19 - 0.30 TYP

0.25

M

s

C

0.13

A

B

0¡-8¡

Dimensions are in millimeters

0.6 –0.1

Seating

plane

DETAIL A

Typ. Scale: 40X

Notes: Unless otherwise specified

1. Reference JEDED registration MO153. Variation AB.

Ref. Note 6, dated 7/93

14-Pin TSSOP

Order Number ACE1502EMT/ACE1502VMT

Package Number MT14A

31

www.fairchildsemi.com

ACE1502 Product Family Rev. 1.7

Physical Dimensions inches (millimeters) unless otherwise noted)

0.335 - 0.344

(8.509 - 8.788)

14 13 12 11 10

9

6

8

7

0.228 - 0.244

0.010

(0.254)

(5.791 - 6.198)

Max.

1

2

3

4

5

Lead #1

IDENT

30 Typ.

0.150 - 0.157

0.053 - 0.069

(1.346 - 1.753)

(3.810 - 3.988)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45

8

Max, Typ.

All leads

Seating

Plane

0.04

0.014

(0.356)

(0.102)

All lead tips

0.008 - 0.010

(0.203 - 0.254)

Typ. all leads

0.050

(1.270)

Typ

0.014 - 0.020

(0.356 - 0.508)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

Typ.

0.008

(0.203)

Typ

Molded Small Out-Line Package (M)

Order Number ACE1502EM/ACE1502EM

Package Number M14A

14-Pin DIP (N14)

Order Number ACE1502EN14/ACE1502VN14

Package Number N14A

32

www.fairchildsemi.com

ACE1502 Product Family Rev. 1.7

Prototype Board Kits: Fairchild offers two solutions for the sim-

pliﬁcation of the breadboard operation so that ACEx Applica-

tions can be quickly tested.

ACEx Development Tools

General Information:

1) ACEDEMO can be used for general purpose applications

Fairchild Semiconductor offers different possibilities to evaluate

and emulate software written for ACEx.

2) ACETXRX is for transmitting / receiving (RF, IR, RS232,

RS485) applications.

Simulator: Is a Windows program able to load, assemble, and

debug ACEx programs. It is possible to place as many break-

points as needed, trace the program execution in symbolic for-

mat, and program a device with the proper options. The ACEx

Simulator is available free-of-charge and can be downloaded

from Fairchild’s web site at www.fairchildsemi.com/products/

memory/ace

ACEDEMO has 8 switches, 8 LEDs, RS232 voltage translator,

buzzer, and a lamp with a small breadboard area.

Factory Programming:

Fairchild offers factory pre-programming and serialization (for

justiﬁed quantities) for a small additional cost. Please refer to

your local distributor for details regarding factory programming.

Ordering P/Ns

Emulator Kit and Programming adapters:

Please refer to your local distributor for details regarding devel-

opment tools.

ACEx Emulator Kit: Fairchild also offers a low cost real-time in-

circuit emulator kit that includes:

Emulator board

Emulator software

Assembler and Manuals

Power supply

DIP14 target cable

PC cable

The ACEx emulator allows for debugging the program code in a

symbolic format. It is possible to place one breakpoint and

watch various data locations. It also has built-in programming

capability.

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a) are intended for surgical implant into the body, or (b) support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a signiﬁcant

injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

Fairchild Semiconductor

Americas

Customer Response Center

Tel. 1-888-522-5372

Fairchild Semiconductor

Europe

Fairchild Semiconductor

Hong Kong

8/F, Room 808, Empire Centre

68 Mody Road, Tsimshatsui East

Kowloon. Hong Kong

Fairchild Semiconductor

Japan Ltd.

4F, Natsume Bldg.

2-18-6, Yushima, Bunkyo-ku

Tokyo, 113-0034 Japan

Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

Fax: +44 (0) 1793-856858

Deutsch

English

Français

Italiano

Tel: +49 (0) 8141-6102-0

Tel: +44 (0) 1793-856856

Tel: +33 (0) 1-6930-3696

Tel: +39 (0) 2-249111-1

Tel; +852-2722-8338

Fax: +852-2722-8383

33

www.fairchildsemi.com

ACE1502 Product Family Rev. 1.7


型号：	ACE1502VN14
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Arithmetic Controller Engine for Low Power Applications 运算控制器引擎针对低功耗应用控制器
文件：	总33页 (文件大小：1185K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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