ACE12022MX_技术文档

PRELIMINARY

August 2001

ACE1202 Product Family

Arithmetic Controller Engine (ACEx™)

for Low Power Applications

General Description

I Hardware Bit - Coder (HBC) (ACE1202-2 only)

I On-chip oscillator

— No external components

— 1µs instruction cycle time

The ACE1202 (Arithmetic Controller Engine) family of

microcontrollers is a dedicated programmable monolithic inte-

grated circuit for applications requiring high performance, low

power, and small size. It is a fully static part fabricated using

CMOS technology.

I On-chip Power-on Reset

I Programmable read and write disable functions

I Memory mapped I/O

The ACE1202 product family has an 8-bit microcontroller core, 64

bytes of RAM, 64 bytes of data EEPROM and 2K bytes of code

EEPROM. Its on-chip peripherals include a multi-function 16-bit

timer, watchdog/idle timer, and programmable undervoltage de-

tection circuitry. The on-chip clock and reset functions reduce the

number of required external components. The ACE1202 product

family is available in 8- and 14-pin SOIC and DIP packages.

I Multilevel Low Voltage Detection

I Brown-out Reset

I Software selectable I/O option

— Push-pull outputs with tri-state option

—

Weak pull-up or high impedance

I Fully static CMOS

— Low power HALT mode (100nA @ 3.3V)

— Power saving IDLE mode

Features

I Arithmetic Controller Engine

I 2K bytes on-board code EEPROM

I 64 bytes data EEPROM

I Single supply operation

— 1.8-5.5V (P.N. ACE1202L)

— 2.2-5.5V (P.N. ACE1202, ACE12022)

— 2.7-5.5V (P.N. ACE1202B, ACE12022B)

I 64 bytes RAM

I Instruction set geared for block encryption

I 40 years data retention

I 1,000,000 data changes

I Watchdog

I Multi-input wake-up on all I/O pins

I 16-bit multifunction timer with difference capture

I 12-bit idle timer

I 8 and 14-pin SOIC, 8 and 14-pin DIP packages. (CSP

package available upon request)

I In-circuit programming

Block and Connection Diagram

VCC¹

Brown-out Reset/Low

Battery Detect

GND¹

Power-on Reset

RESET²

HALT & IDLE Power

Internal Oscillator

(CKO) G0

(CKI) G1

(T1/TX³) G2

(Input only) G3

G4

Saving Modes

12-bit Timer0 with

Watchdog Timer

GPORT

ACE1202 core

16-bit Multi-function

general

purpose

I/O with

multi-

input

wakeup

(4 interrupt

sources

Timer1 with Difference

Capture

and vectors)

Hardware Bit-Coder³

64 bytes of RAM

(TX³) G5

G6²

Programming Interface

2K bytes of Code

EEPROM

64 bytes of Data

EEPROM

G7²

1. 100nf Decoupling capacitor recommended

2. Available only in the 14-pin package option

3. Available only on the ACE1202-2 device

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1

ACE1202 Product Family Rev. B.1

Figure 2: ACEx Application Example (Remote Keyless Entry)

V

CC

Optional

LED

G4

V

G3

CC

RF Interface

G0

G1

G5

G2

RF Stage

GND

Figure 3: ACE1202/ACE1202-2 8-pin Device Pinout

a) Normal Mode Operation

b) Programming Mode Operation

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

LOAD

SFT_IN

NC/VCC

NC

VCC

G3

G4

G5

G0

VCC

GND

G2

GND

SFT_OUT

CKI

G1

Figure 4: ACE1202/ACE1202-2 14-pin Device Pinout

a) Normal Mode Operation

b) Programming Mode Operation

1

2

3

4

5

6

7

14

13

12

11

10

9

1

2

3

4

5

6

7

14

13

12

11

10

9

G3

G4

NC

G6

G7

G5

G0

VCC

GND

NC

LOAD

SFT_IN

NC

VCC

GND

NC

G2

NC

SFT_OUT

NC

NC/VCC

NC

RESET

G1

RESET

CKI

8

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2

ACE1202 Product Family Rev. B.1

2.0 Electrical Characteristics

Absolute Maximum Ratings

Operating Conditions

Relative Humidity (non-condensing)

EEPROM write limits

Ambient Storage Temperature

-65°C to +150°C

95%

Input Voltage not including G3

G3 Input Voltage

-0.3V to V_CC+0.3V

0.3V to 13V

+300°C

See DC Electrical

Characteristics

Lead Temperature (10s max)

Electrostatic Discharge on all pins

2000V min

Part Number Operating Voltage Ambient Operating Temperature

ACE1202

2.2 to 5.5V

2.7 to 5.5V

1.8 to 5.5V

0°C to 70°C

ACE12022

ACE1202E

ACE12022E

ACE1202V

ACE1202B

ACE12022B

ACE1202BE

ACE12022BE

ACE1202BV

ACE12022BV

ACE1202L

-40°C to +85°C

-40°C to +125°C

0°C to 70°C

-40°C to +85°C

-40°C to +125°C

0°C to 70°C

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3

ACE1202 Product Family Rev. B.1

Preliminary ACE1202/ACE1202-2 DC Electrical Characteristics

V_CC= 1.8/2.2/2.7 to 5.5V

All measurements valid for ambient operating temperature range unless otherwise stated.

Symbol

Parameter

Conditions

MIN

TYP

MAX

Units

4

I_CC

Supply Current –

no data EEPROM write in

progress

1.8V

2.2V

2.7V

3.3V

5.5V

0.2

0.4

0.7

1.2

3.7

0.5

1.0

1.2

2.0

5.5

mA

I_CCH

HALT Mode current

3.3V @ -40°C to +25°C

5.5V @ -40°C to +25°C

3.3V @ +85°C

5.5V @ +85°C

3.3V @ +125°C

10

60

75

400

600

1550

100

nA

1000

2500

5000

8000

5.5V @+125°C

5

I_CCL

IDLE Mode Current

3.3V

5.5V

150

200

300

µA

V_CCW

EEPROM Write Voltage

Code EEPROM in

Programming Mode

4.5

2.4

5.0

5.5

V

Data EEPROM in

Operating Mode

5.5

V

S_VCC

V_IL

Power Supply Slope

1µs/V

10ms/V

0.2V_CC

Input Low with Schmitt

Trigger Buffer

V_CC= 1.8 -5.5V

V_CC= 1.8 - 5.5V

V

V_IH

Input High with Schmitt

Trigger Buffer

0.8V_CC

30

I_IP

Input Pull-up Current

TRI-STATE Leakage

Output Low Voltage

G0, G1, G2, G4, G6, G7

G5

V_CC=5.5V, V_IN=0V

V_CC=5.5V

65

2

350

200

µA

I_TL

nA

V_OL

V_CC= 1.8 - 2.2V

0.8 mA sink

0.2V_CC

V

1.0 mA sink

Output Low Voltage

G0, G1, G2, G4, G6, G7

G5

V_CC= 2.2V – 3.3V

3.0 mA sink

0.2V_CC

V

5.0 mA sink

Output Low Voltage

G0, G1, G2, G4, G6, G7

G5

V_CC= 3.3V – 5.5V

5.0 mA sink

0.2V_CC

V

10.0 mA sink

V_OH

Output High Voltage

G0, G1, G2, G4, G6, G7

G5

V_CC= 1.8 - 2.2V

0.1 mA source

0.2 mA source

V_CC= 3.3V – 5.5V

0.4 mA source

0.8 mA source

V_CC= 3.3V – 5.5V

0.4 mA source

1.0 mA source

0.8V_CC

V

Output High Voltage

G0, G1, G2, G4, G6, G7

G5

0.8V_CC

V

Output High Voltage

G0, G1, G2, G4, G6, G7

G5

0.8V_CC

V

⁴I_CCactive current is dependent on the program code.

⁵Based on a continuous IDLE looping program.

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4

ACE1202 Product Family Rev. B.1

Preliminary ACE1202/ACE1202-2 AC Electrical Characteristics

_CC= 1.8/2.2/2.7 to 5.5V

V

All measurements valid for ambient operating temperature range unless otherwise stated.

Parameter

Conditions

MIN

TYP

MAX

Units

Instruction cycle time from

internal clock - setpoint

5.0V at +25°C

0.9

1.0

1.1

µs

Internal clock voltage dependent 3.0V to 5.5V,

+5

+10

+2

%

frequency variation

constant temperature

Internal clock temperature

3.0V to 5.5V,

dependent frequency variation

full temperature range

Internal clock frequency

deviation for 0.5V drop

3.0V to 4.5V,

constant temperature

Crystal oscillator frequency

External clock frequency

EEPROM write time

(Note 6)

(Note 7)

4

MHz

ms

3

10

2

Internal clock start up time

Oscillator start up time

(Note 7)

ms

2400

cycles

⁶The maximum permissible frequency is guaranteed by design but not 100% tested.

⁷The parameter is guaranteed by design but not 100% tested.

Preliminary ACE1202/ACE1202-2 Electrical Characteristics for programming

All data following is valid between 4.5V and 5.5V at ambient temperature. The following charac-

teristics are guaranteed by design but are not 100% tested. See "EEPROM write time" in the AC

Electrical Characteristics for definition of the programming ready time.

Parameter

Description

MIN

500

100

900

50

MAX

DC

Units

ns

t_HI

CLOCK high time

t_LO

CLOCK low time

DC

ns

t_DIS

SHIFT_IN setup time

SHIFT_IN hold time

SHIFT_OUT setup time

SHIFT_OUT hold time

LOAD supervoltage timing

LOAD timing

ns

t_DIH

ns

t_DOS

t_DOH

t_SV1, t_SV2

ns

µs

t_LOAD1, t_LOAD2, t_LOAD3, t_LOAD4

V_SUPERVOLTAGE

5

µs

Supervoltage level

11.5

12.5

V

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5

ACE1202 Product Family Rev. B.1

Preliminary ACE1202/ACE1202-2 Low Battery Detect (LBD) Characteristics

V_CC= 2.2/1.8 to 5.5V

The following characteristics are guaranteed by design but are not 100% tested.

Parameter

Conditions

Level 1 @ -40°C

Level 8 @ -40°C

Level 1 @ 0°C

MIN

TYP

2.84

2.02

2.98

2.05

3.08

2.12

3.31

2.27

3.36

2.40

MAX

Units

LBD Voltage Threshold

V

Level 8 @ 0°C

Level 1 @ -25°C

Level 8 @ +25°C

Level 1 @ +85°C

Level 8 @ +85°C

Level 1 @ +125°C

Level 8 @ +125°C

Preliminary ACE1202/ACE1202-2 Brown-out Reset (BOR) Characteristics

V_CC= 2.2 to 5.5V

The following characteristics are guaranteed by design but are not 100% tested.

Parameter

Conditions

-40°C

MIN

TYP

1.98

2.06

2.12

2.27

2.37

MAX

Units

BOR Trigger Threshold

V

0°C

+25°C

+85°C

+125°C

Preliminary ACE1202L Brown-out Reset (BOR) Characteristics

V_CC= 1.8 to 5.5V

The following characteristics are guaranteed by design but are not 100% tested.

Parameter

Conditions

0°C

MIN

TYP

1.78

1.82

1.96

MAX

Units

BOR Trigger Threshold

V

+25°C

+70°C

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6

ACE1202 Product Family Rev. B.1

3.0 AC & DC Electrical Characteristic Graphs

Figure 5: RC Oscillator Frequency vs. Temperature (V_CC=5.0V)

2.600

2.400

2.200

2.000

1.800

1.600

1.400

1.200

1.000

Avg

Min

Max

3.3k/82pF

5.6k/100pF

6.8K/100pF

Resistor & Capacitor Values [k & pF]

Figure 6: RC Oscillator Frequency vs. Temperature(V_CC=2.5V)

1.600

1.400

1.200

1.000

0.800

0.600

Avg

Min

Max

3.3k/82pF

5.6k/100pF

6.8K/100pF

Resistor & Capacitor Values [k & pF]

Figure 7: Internal Oscillator Frequency

Temperature [°C]

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7

ACE1202 Product Family Rev. B.1

Figure 8: Power Supply Rise Time

V_CC

V_BATT

1V

t_{S min}

t_{S actual}

t_{S max}

time

Name

Parameter

Unit

V_CC

Supply Voltage

[V]

V_BATT

t_{S min}

t_{S actual}

t_{S max}

S_VCC

Battery Voltage (Nominal Operating Voltage)

Minimum Time for V_CCto Rise by 1V

Actual Time for V_CCto Rise by 1V

Maximum Time for V_CCto Rise by 1V

Power Supply Slope

[ms]

[ms/V]

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8

ACE1202 Product Family Rev. B.1

Figure 9: I_CCActive

I_CCActive (no data EEPROM writes) vs. Temperature

Temperature [°C]

I_CCActive (data EEPROM writes) vs. Temperature

Temperature [°C]

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ACE1202 Product Family Rev. B.1

Figure 10: HALT Mode Currents

HALT current vs. Temperature

Temperature [°C]

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10

ACE1202 Product Family Rev. B.1

Figure 11: IDLE Mode Currents

IDLE current vs. Temperature

Temperature [°C]

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11

ACE1202 Product Family Rev. B.1

segment of the memory map. This modification improves the

overall code efficiency of the ACEx microcontroller and takes

advantage of the flexibility found on Von Neumann style ma-

chines.

4.0 Arithmetic Controller Core

The ACEx microcontroller core is specifically designed for low

cost applications involving bit manipulation, shifting and block

encryption.ItisbasedonamodifiedHarvardarchitecturemeaning

peripheral,I/O, andRAMlocationsareaddressedseparatelyfrom

instruction data.

4.1 CPU Registers

The ACEx microcontroller has five general-purpose registers.

These registers are the Accumulator (A), X-Pointer (X), Program

Counter (PC), Stack Pointer (SP), and Status Register (SR). The

X, SP, and SR registers are all memory-mapped.

The core differs from the traditional Harvard architecture by

aligningthedataandinstructionmemorysequentially. Thisallows

the X-pointer (12-bits) to point to any memory location in either

Figure 12: Programming Model

7

0

A

8-bit accumulator register

12-bit X pointer register

11-bit program counter

4-bit stack pointer

11

10

X

PC

SP

SR

3

8-bit status register

R 0 0 G Z C H N

NEGATIVE flag

HALF CARRY flag (from bit 3)

CARRY flag (from MSB)

ZERO flag

GLOBAL Interrupt Mask

READY flag (from EEPROM)

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12

ACE1202 Product Family Rev. B.1

from the stack and loads it into the program counter. Execution

then continues at the recovered return address.

4.1.1 Accumulator (A)

The Accumulator is a general-purpose 8-bit register that is used to

holddataandresultsofarithmeticcalculationsordatamanipulations.

4.1.5 Status Register (SR)

The 8-bit Status register (SR) contains four condition code indicators

(C, H, Z, and N), one interrupt masking bit (G), and an EEPROM write

flag (R). The condition codes are automatically updated by most

instructions. (See Table 10)

4.1.2 X-Pointer (X)

TheX-Pointerregisterallowsfora12-bitindexingvaluetobeadded

to an 8-bit offset creating an effective address used for reading and

writing between the entire memory space. (Software can only read

from code EEPROM.) This provides software with the flexibility of

storing lookup tables in the code EEPROM memory space for the

core’s accessibility during normal operation.

Carry/Borrow (C)

The carry flag is set if the arithmetic logic unit (ALU) performs a carry

or borrow during an arithmetic operation and by its dedicated

instructions. The rotate instruction operates with and through the

carry bit to facilitate multiple-word shift operations. The LDC and

INVCinstructionsfacilitatedirectbitmanipulationusingthecarryflag.

The ACEx core allows software to access the entire 12-bit X-Pointer

registerusingthespecialX-pointerinstructions(e.g. LDX, #000H). (See

Table 9) However, software may also access the register through any of

the memory-mapped instructions using the XHI (X[11:8]) and XLO

(X[7:0])variableslocatedat0xBEand0xBF,respectively.(SeeTable11)

Half Carry (H)

Thehalfcarryflagindicateswhetheranoverflowhastakenplaceonthe

boundary between the two nibbles in the accumulator. It is primarily

used for Binary Coded Decimal (BCD) arithmetic calculation.

The X register is divided into two sections. The 11 least significant

bits (LSBs) of the register is the address of the program or data

memory space. The most significant bit (MSB) of the register is

write only and selects between the data (0x000 to 0x0FF) or

program (0x800 to 0xFFF) memory space.

Zero (Z)

The zero flag is set if the result of an arithmetic, logic, or data

manipulation operation is zero. Otherwise, it is cleared.

Example: If Bit 11 = 0, then the LD A, [00,X] instruction will take a

value from address range 0x000 to 0x0FF and load it into A. If Bit

11 = 1, then the LD A, [00,X] instruction will take a value from

address range 0x800 to 0xFFF and load it into A.

Negative (N)

The negative flag is set if the MSB of the result from an arithmetic,

logic, or data manipulation operation is set to one. Otherwise, the

flag is cleared. A result is said to be negative if its MSB is a one.

The X register can also serve as a counter or temporary storage

register. However, this is true only for the 11-LSBs since the 12^th

bit is dedicated for memory space selection.

Interrupt Mask (G)

The interrupt request mask (G) is a global mask that disables all

maskable interrupt sources. If the G Bit is cleared, interrupts can

become pending, but the operation of the core continues uninter-

rupted. However, if the G Bit is set an interrupt is recognized. After any

reset, the G bit is cleared by default and can only be set by a software

instruction. When an interrupt is recognized, the G bit is cleared after

thePCisstackedandtheinterruptvectorisfetched.Oncetheinterrupt

is serviced, a return from interrupt instruction is normally executed to

restore the PC to the value that was present before the interrupt

occurred. The G bit is reset to one after a return from interrupt is

executed. Although the G bit can be set within an interrupt service

routine,“nesting”interruptsinthiswayshouldonlybedonewhenthere

is a clear understanding of latency and of the arbitration mechanism.

4.1.3 Program Counter (PC)

The 10-bit program counter register contains the address of the

next instructionto beexecuted. Afterareset, ifinnormal modethe

program counter is initialized to 0x800.

4.1.4 Stack Pointer (SP)

The ACEx microcontroller has an automatic program stack with a 4-

bit stack pointer. The stack can be initialized to any location between

addresses0x30-0x3F.Normally,thestackpointerisinitializedbyone

of the first instructions in an application program. After a reset, the

stack pointer is defaulted to 0xF pointing to address 0x3F.

The stack is configured as a data structure which decrements

from high to low memory. Each time a new address is pushed

onto the stack, the core decrements the stack pointer by two.

Each time an address is pulled from the stack, the core incre-

ments the stack pointer is by two. At any given time, the stack

pointer points to the next free location in the stack.

4.2 Interrupt handling

When an interrupt is recognized, the current instruction completes its

execution. The return address (the current value in the program

counter) is pushed onto the stack and execution continues at the

address specified by the unique interrupt vector (see Table 11). This

process takes five instruction cycles. At the end of the interrupt service

routine,areturnfrominterrupt(RETI)instructionisexecuted.TheRETI

instruction causes the saved address to be pulled off the stack in

reverseorder.TheGbitissetandinstructionexecutionresumesatthe

return address.

When a subroutine is called by a jump to subroutine (JSR)

instruction, the address of the instruction is automatically pushed

onto the stack least significant byte first. When the subroutine is

finished, a return from subroutine (RET) instruction is executed.

The RET instruction pulls the previously stacked return address

Table 8: Interrupt Priority Sequence

Priority (4 highest, 1 lowest)

Interrupt

MIW (EDGEI)

Timer0 (TMRI0)

Timer1 (TMRI1)

Software (INTR)

4

3

2

1

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13

ACE1202 Product Family Rev. B.1

The ACEx microcontroller is capable of supporting four interrupts.

Three are maskable through the G bit of the SR and the fourth

(softwareinterrupt)isnotinhibitedbytheGbit(seeFigure13).The

software interrupt instruction is generated by the execution of the

INTR instruction. once the INTR instruction is executed, the ACEx

corewillinterruptwhethertheGbitissetornot. TheINTRinterrupt

is executed in the same manner as the other maskable interrupts

where the program counter register is stacked and the G bit is

cleared. This means, if the G bit was enabled prior to the software

interrupt the RETI instruction must be used to return from interrupt

in order to restore the G bit to its previous state. However, if the G

bit was not enabled prior to the software interrupt the RET

instruction must be used.

Indirect

TheinstructionallowstheX-pointertoaddressanylocationwithin

the data memory space.

Direct

The instruction contains an 8-bit address field that directly points

to the data memory space as an operand.

Immediate

The instruction contains an 8-bit immediate field as an operand.

Inherent

This instruction has no operands associated with it.

In case of multiple interrupts occurring at the same time, the ACEx

microcontroller core has prioritized the interrupts. The interrupt

priority sequence in shown in Table 8.

Absolute

The instruction contains a 11-bit address that directly points to a

location in the program memory space. There are two operands

associated with this addressing mode. Each operand contains a

byteofanaddress.Thismodeisusedonlyforthelongjump(JMP)

and JSR instructions.

4.3 Addressing Modes

The ACEx microcontroller has seven addressing modes indexed,

indirect, direct, immediate, absolute jump, and relative jump.

Indexed

Relative

The instruction allows an 8-bit unsigned offset value to be added to

the 11-LSBs of the X-pointer yielding a new effective address. This

modecanbeusedtoaddresseitherdataorprogrammemoryspace.

This mode is used for the short jump (JP) instructions where the

operand is a value relative to the current PC address. With this

instruction, software is limited to the number of bytes it can jump,

-31 or +32.

Figure 13: Basic Interrupt Structure

INTR

T1PND

T1

T0PND

T0

Interrupt

WKPND

MIW

Interrupt

Pending

Flags

T0INT

EN

WKINT

EN

G

T1EN

Global Interrupt

Enable

Interrupt Enable Bits

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14

ACE1202 Product Family Rev. B.1

Table 9: Instruction Addressing Modes

Instruction

Immediate

Direct

Indexed

Indirect

Inherent

Relative Absolute

ADC

ADD

AND

OR

A, #

A, M

A, [X]

A, #

SUBC

XOR

CLR

INC

M

A

X

DEC

IFEQ

IFGT

IFNE

IFLT

A, #

X, #

M,#

A, M

A, [00,X]

A, [X]

X, #

SC

no-op

RC

IFC

IFNC

INVC

LDC

STC

#, M

RLC

RRC

M

A

LD

ST

LD

A, #

#, A

X, #

M, #

A, M

M, M

A, [00,X]

A, [X]

NOP

no-op

IFBIT

SBIT

RBIT

#, M

#, [X]

JP

Rel

JSR

JMP

RET

RETI

INTR

[00,X]

M

no-op

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ACE1202 Product Family Rev. B.1

Table 10: Instruction Cycles and Bytes

Mnemonic Operand Bytes Cycles Flags

affected

Mnemonic Operand Bytes Cycles Flags

affected

ADC

ADD

AND

CLR

DEC

IFBIT

IFC

A, [X]

A, M

A, #

A, [X]

A, M

A, #

A, M

A, [X]

X

1

2

1

2

1

2

1

2

1

2

1

2

1

2

3

2

1

2

3

2

1

2

3

1

2

1

2

1

2

1

2

1

2

1

2

1

3

1

2

3

2

3

1

2

3

2

3

1

2

3

1

2

1

5

1

C,H,Z,N

Z,N

JMP

JP

M

3

2

1

3

2

1

2

3

2

3

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

4

3

1

5

2

3

1

2

3

2

3

1

2

1

2

1

5

1

2

1

2

1

3

1

2

1

2

1

2

None

C

[00,X]

JSR

LD

M

Z,N

[00,X]

A, #

Z,N

LD

A, [00,X]

A, [X]

A, M

M, #

Z,N

LD

Z,N

LD

Z

LD

A

C,H,Z,N

Z,N

LD

X, #

M

LDC

LD

#, M

A

M, M

None

Z,N

M

Z,N

NOP

OR

X

Z

A, #

#, A

#, M

None

Z,N

OR

A, [X]

A, M

#, [X]

#, M

Z,N

OR

Z,N

RBIT

RC

Z,N

IFEQ

IFGT

IFNE

IFLT

IFNC

INC

A, [00,X]

A, [X]

A, #

Z,N

C,H

RET

RETI

RLC

RRC

SBIT

SC

None

C,Z,N

Z,N

A, M

M, #

A

X, #

M

A, #

A

A, [00,X]

A, [X]

A, M

M

#, [X]

#, M

Z,N

X, #

C,H

A, #

ST

A, [00,X]

A, [X]

A, M

None

Z,N

A, [00,X]

A, [X]

A, M

ST

STC

SUBC

XOR

#, M

X, #

A, #

C,H,Z,N

Z,N

A, [X]

A, M

A

M

X

INC

Z,N

A, #

INC

Z

A, [X]

A, M

Z,N

INTR

INVC

None

C

Z,N

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16

ACE1202 Product Family Rev. B.1

4.4 Memory Map

All I/O ports, peripheral registers and core registers, except the accumulator and the program counter are mapped into memory space.

Table 11: Memory Map

Address

0x00 - 0x3F

0x40 - 0x7F

0xA0

Memory Space

Data

Block

SRAM

EEPROM

HBC

Contents

Data RAM

Data

Data EEPROM

Data

HBCNTRL register (ACE1202-2 only)

PSCALE register (ACE1202-2 only)

HPATTERN register (ACE1202-2 only)

LPATTERN register (ACE1202-2 only)

BPSEL register (ACE1202-2 only)

DAT0 register (ACE1202-2 only)

T1RALO register

0xA1

Data

HBC

0xA2

Data

HBC

0xA3

Data

HBC

0xA4

Data

HBC

0xA9

Data

HBC

0xAA

Data

Timer1

MIW

0xAB

Data

T1RAHI register

0xAC

Data

TMR1LO register

0xAD

Data

TMR1HI register

0xAE

Data

T1CNTRL register

WKEDG register

0xAF

Data

0xB0

Data

MIW

WKPND register

0xB1

Data

MIW

WKEN register

0xB2

Data

I/O

PORTGD register

0xB3

Data

I/O

PORTGC register

0xB4

Data

I/O

PORTGP register

0xB5

Data

Timer0

Clock

WDSVR register

0xB6

Data

T0CNTRL register

HALT mode register

Reserved

0xB7

Data

0xB8 - 0xBC

0xBD

Data

LBD

Core

LBD register

0xBE

XHI register

0xBF

Data

Core

XLO register

0xC0

Data

Core

Power mode clear (PMC) register

SP register

0xCE

Data

Core

0xCF

Data

Core

Status register (SR)

Code EEPROM

0x800 - 0xFF5

0xFF6 - 0xFF7

0xFF8 - 0xFF9

0xFFA - 0xFFB

0xFFC - 0xFFD

0xFFE - 0xFFF

Program

EEPROM

Core

Timer0 Interrupt vector

Timer1 Interrupt vector

MIW Interrupt vector

Software Interrupt vector

Reserved

Core

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17

ACE1202 Product Family Rev. B.1

enter HALT/IDLE mode while the data EEPROM is busy (R = 0)

can affect the current data being written.

4.5 Memory

The ACEx microcontroller device has 64 bytes of SRAM and 64

bytes of EEPROM available for data storage. The device also has

2KbytesofEEPROMforprogramstorage. Softwarecanreadand

writetoSRAManddataEEPROMbutcanonlyreadfromthecode

EEPROM. While in normal mode, the code EEPROM is protected

from any writes. The code EEPROM can only be rewritten when

the device is in program mode and if the write disable (WDIS) bit

of the initialization register is not set to 1.

4.6 Initialization Registers

The ACEx microcontroller has two 8-bit wide initialization regis-

ters. These registers are read from the memory space on power-

up to initialize certain on-chip peripherals. Figure 14 provides a

detailed description of Initialization Register 1. The Initialization

Register 2 is used to trim the internal oscillator to its appropriate

frequency. This register is pre-programmed in the factory to yield

an internal instruction clock of 1MHz.

While in normal mode, the user can write to the data EEPROM

array by 1) polling the ready (R) flag of the SR, then 2) executing

the appropriate instruction. If the R flag is 1, the data EEPROM

block is ready to perform the next write. If the R flag is 0, the data

EEPROM is busy. The data EEPROM array will reset the R flag

after the completion of a write cycle. Attempts to read, write, or

Both Initialization Registers 1 and 2 can be read from and written

to during programming mode. However, re-trimming the internal

oscillator (writing to the Initialization Register 2) once it has left the

factory is discouraged.

Figure 14: Initialization Register 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CMODE[0]

CMODE[1]

WDEN

BOREN

BLSEL ¹⁰

UBD ^8,9

WDIS ^8,9

RDIS ^8,9

(0) RDIS ^8,9

(1) WDIS ^8,9

(2) UBD ^8,9

(3) BLSEL ¹⁰

If set, disables attempts to read the contents from the memory while in programming mode

If set, disables attempts to write new contents to the memory while in programming mode

If set, the device will not allow any writes to occur in the upper block of data EEPROM (0x60-0x7F)

If set, the Brown-out Reset (BOR) voltage reference level is set to its higher range for P.N. ACE1202/ACE12022

If not set, the BOR voltage reference level is set to its lower range for P.N. ACE1202L

(4) BOREN

If set, allows a BOR to occur if VCC falls below the voltage reference level

If set, enables the on-chip processor watchdog circuit

Clock mode select bit 1 (See Table 17)

(5) WDEN

(6) CMODE[1]

(7) CMODE[0]

Clock mode select bit 0 (See Table 17)

⁸If both the WDIS and RDIS bits are set, the device will no longer be able to be placed into program mode.

⁹If the RDIS or UBD bits are not set while the WDIS bit is not set, then the RDIS and UBD bits can be reset.

¹⁰The BLSEL bit is set to its appropriate level in the factory. If writing to the initialization register is necessary, be sure to maintain BLSEL set value.

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18

ACE1202 Product Family Rev. B.1

default, the TMR1 is reset to 0xFFFF, T1RA is reset to 0x0000,

and T1CNTRL is reset to 0x00.

5.0 Timer 1

Timer 1 is a versatile 16-bit timer that can operate in one of four

modes:

The timer can be started or stopped through the T1CNTRL

register bit T1C0. When running, the timer counts down (decre-

ments) every clock cycle. Depending on the operating mode, the

timer’s clock is either the instruction clock or a transition on the T1

input. In addition, occurrences of timer underflow (transitions from

0x0000 to 0xFFFF/T1RA value) can either generate an interrupt

and/or toggle the T1 output pin.

• Pulse Width Modulation (PWM) mode, which generates

pulses of a specified width and duty cycle

• External Event Counter mode, which counts occurrences

of an external event

• Standard Input Capture mode, which measures the

elapsed time between occurrences of external events

Timer 1’s interrupt (TMRI1) can be enabled by interrupt enable

(T1EN) bit in the T1CNTRL register. When the timer interrupt is

enabled, depending on the operating mode, the source of the

interrupt is a timer underflow and/or a timer capture.

• Difference Input Capture mode, which automatically

measures the difference between edges

Timer 1 contains a 16-bit timer/counter register (TMR1), a 16-bit

auto-reload/capture register (T1RA), and an 8-bit control register

(T1CNTRL). All register are memory-mapped for simple access

through the core with both the 16-bit registers organized as a pair

of8-bitregisterbytes{TMR1HI,TMR1LO}and{T1RAHI,T1RALO}.

Depending on the operating mode, the timer contains an external

input or output (T1) that is multiplexed with the I/O pin G2. By

12 and 13.

5.1 Timer control bits

Reading and writing to the T1CNTRL register controls the timer’s

operation. By writing to the control bits, the user can enable or

disable the timer interrupts, set the mode of operation, and start or

stop the timer. The T1CNTRL register bits are described in Tables

Table 12: TIMER1 Control Register (T1CNTRL)

T1CNTRL Register

Name

T1C3

T1C2

T1C1

T1C0

Function

Bit 7

Bit 6

Bit 5

Bit 4

Timer TIMER1 control bit 3 (see Table 13)

Timer TIMER1 control bit 2 (see Table 13)

Timer TIMER1 control bit 1 (see Table 13)

Timer TIMER1 run: 1 = Start timer, 0 = Stop timer;

or Timer TIMER1 underflow interrupt pending flag

in input capture mode

Bit 3

Bit 2

T1PND

T1EN

Timer1 interrupt pending flag: 1 = Timer1 interrupt

pending, 0 = Timer1 interrupt not pending

Timer1 interrupt enable bit: 1 = Timer1 interrupt enabled,

0 = Timer1 interrupt disabled

Bit 1

Bit 0

M4S1

Capture type: 0 = Pulse capture, 1 = Cycle capture (see Table 13)

Reserved

-----------

Table 13: TIMER1 Operating Modes

T1 T1

C3 C2

T1 M4

C1 S1

Timer Mode

Source

Interrupt A

Timer Counts On

0

1

0

1

0

1

0

1

0

1

0

1

x

0

1

0

1

MODE 2

TIMER1 Underflow

Autoreload T1RA

Pos. T1 Edge

Neg. T1 Edge

Pos. to Neg.

T1 Pos. Edge

T1 Neg. Edge

MODE 1 T1 Toggle

Instruction Clock

MODE 1 No T1 Toggle

MODE 3 Captures: T1 Pos. edge

MODE 3 Captures: T1 Neg. Edge

MODE 4 Difference Capture

Pos. to Pos.

Neg. to Pos.

Neg. to Neg.

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19

ACE1202 Product Family Rev. B.1

1. Configure T1 as an output by setting bit 2 of PORTGC.

SBIT 2, PORTGC ; Configure G2 as an output

5.2 Mode1:PulseWidthModulation(PWM)Mode

-

In the PWM mode, the timer counts down at the instruction clock

rate. When an underflow occurs, the timer register is reloaded from

T1RAandthecountdownproceedsfromtheloadedvalue.Atevery

underflow, a pending flag (T1PND) located in the T1CNTRL regis-

ter is set. Software must then clear the T1PND flag and load the

T1RA register with an alternate PWM value. In addition, the timer

can be configured to toggle the T1 output bit upon underflow.

Configuring the timer to toggle T1 results in the generation of a

signal outputted from port G2 with the width and duty cycle

controlled by the values stored in the T1RA. A block diagram of the

timer’s PWM mode of operation is shown in Figure 15.

2. Initialize T1 to 1 (or 0) by setting (or clearing) bit 2 of

PORTGD.

-

SBIT 2, PORTGD

; Set G2 high

3. Load the initial PWM high (low) time into the timer register.

-

LD TMR1LO, #6FH

LD TMR1HI, #05H

; High (Low) for 1.391ms

(1MHz clock)

4. Load the PWM low (high) time into the T1RA register.

-

LD T1RALO, #2FH

; Low (High) for .303ms

(1MHz clock)

-

LD T1RAHI, #01H

The timer has one interrupt (TMRI1) that is maskable through the

T1EN bit of the T1CNTRL register. However, the core is only

interrupted if the T1EN bit and the G (Global Interrupt enable) bit of

the SR is set. If interrupts are enabled, the timer will generate an

interrupt each time T1PND flags is set (whenever the timer

underflows provided that the pending flag was cleared.) The

interrupt service routine is responsible for proper handling of the

T1PND flag and the T1EN bit.

5. Write the appropriate control value to the T1CNTRL

register to select PWM mode with T1 toggle, to clear the

enable bit and pending flag, and to start the timer. (See

Table 12 and 13)

-

LD T1CNTRL, #0B0H

; Setting the T1C0 bit starts

the timer

6. After every underflow, load T1RA with alternate values. If

the user wishes to generate an interrupt on a T1 output

transition, reset the pending flags and then enable the

interrupt using T1EN. The G bit must also be set. The

interrupt service routine must reset the pending flag and

perform whatever processing is desired.

The interrupt will be synchronous with every rising and falling edge

oftheT1outputsignal.Generatinginterruptsonlyonrisingorfalling

edgesofT1isachievablethroughappropriatehandlingoftheT1EN

bit or T1PND flag through software.

The following steps show how to properly configure Timer 1 to

operate in the PWM mode. For this example, the T1 output signal

is toggled with every timer underflow and the “high” and “low” times

for the T1 output can be set to different values. The T1 output signal

can start out either high or low depending on the configuration of

G2; the instructions below are for starting with the T1 output high.

Follow the instructions in parentheses to start the T1 output low.

-

RBIT T1PND, T1CNTRL

LD T1RALO, #6FH

; T1PND equals 3

; High (Low) for 1.391ms

(1MHz clock)

-

LD T1RAHI, #05H

Figure 15: Pulse Width Modulation Mode

16-bit Auto-Reload

Register (T1RA)

Underflow

Interrupt

Data

Bus

Data

Latch

16-bit Timer (TMR1)

T1

Instruction

Clock

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20

ACE1202 Product Family Rev. B.1

1. Configure T1 as an input by clearing bit 2 of PORTGC.

RBIT 2, PORTGC ; Configure G2 as an input

2. Initialize T1 to input with pull-up by setting bit 2 of PORTGD.

SBIT 2, PORTGD ; Set G2 high

3. Enable the global interrupt enable bit.

SBIT 4, STATUS

5.3 Mode 2: External Event Counter Mode

-

The External Event Counter mode operates similarly to the PWM

mode; however, the timer is not clocked by the instruction clock

but by transitions of the T1 input signal. The edge is selectable

through the T1C1 bit of the T1CNTRL register. A block diagram of

the timer’s External Event Counter mode of operation is shown in

Figure 16.

-

4. Load the initial count into the TMR1 and T1RA registers.

When the number of external events is detected, the counter

will reach zero; however, it will not underflow until the next

event is detected. To count N pulses, load the value N-1 into

the registers. If it is only necessary to count the number of

occurrences and no action needs to be taken at a particular

count, load the value 0xFFFF into the registers.

The T1 input should be connected to an external device that

generates a positive/negative-going pulse for each event. By

clocking the timer through T1, the number of positive/negative

transitions can be counted therefore allowing software to capture

the number of events that occur. The input signal on T1 must have

a pulse width equal to or greater than one instruction clock cycle.

-

LD TMR1LO, #0FFH

LD TMR1HI, #00H

LD T1RALO, #0FFH

LD T1RAHI, #00H

The counter can be configured to sense either positive-going or

negative-goingtransitionsontheT1pin. Themaximumfrequency

at which transitions can be sensed is one-half the frequency of the

instruction clock.

5. Write the appropriate control value to the T1CNTRL register

to select External Event Counter mode, to clock every falling

edge, to set the enable bit, to clear the pending flag, and to

start the counter. (See Table 12 and 13)

As with the PWM mode, when the counter underflows the counter

is reloaded from the T1RA register and the count down proceeds

fromtheloadedvalue.Ateveryunderflow,apendingflag(T1PND)

located in the T1CNTRL register is set. Software must then clear

the T1PND flag and can then load the T1RA register with an

alternate value.

-

LD T1CNTRL, #34H (#00h) ; Setting the T1C0 bit

starts the timer

6. When the counter underflows, the interrupt service routine

must clear the T1PND flag and take whatever action is

required once the number of events occurs. If the software

wishes to merely count the number of events and the

anticipated number may exceed 65,536, the interrupt service

routine should record the number of underflows by

incrementing a counter in memory. Software can then

calculate the correct event count.

The counter has one interrupt (TMRI1) that is maskable through

the T1EN bit of the T1CNTRL register. However, the core is only

interrupted if the T1EN bit and the G (Global Interrupt enable) bit

of the SR is set. If interrupts are enabled, the counter will generate

an interrupt each time the T1PND flag is set (whenever timer

underflows provided that the pending flag was cleared.) The

interrupt service routine is responsible for proper handling of the

T1PND flag and the T1EN bit.

-

RBIT T1PND, T1CNTRL

; T1PND equals 3

The following steps show how to properly configure Timer 1 to

operateintheExternalEventCountermode.Forthisexample,the

counter is clocked every falling edge of the T1 input signal. Follow

the instructions in parentheses to clock the counter every rising

edge.

Figure 16: External Event Counter Mode

16-bit Auto-Reload

Register (T1RA)

Data

Bus

Underflow

Interrupt

16-bit Counter (TMR1)

T1

Edge Selector

Logic

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21

ACE1202 Product Family Rev. B.1

For example, the T1 pin can be programmed to be sensitive to a

positive-going edge. When the positive edge is sensed, the TMR1

register contents is transferred to the T1RA register and a Timer 1

interrupt is generated. The Timer 1 interrupt service routine records

the contents of the T1RA register, changes the edge sensitivity from

positivetonegative-goingedge,andclearstheT1PNDflag.Whenthe

negative-goingedgeissensedanotherTimer1interruptisgenerated.

The interrupt service routine reads the T1RA register again. The

difference between the previous reading and the current reading

reflects the elapsed time between the positive edge and negative

edge of the T1 input signal i.e. the width of the positive-going pulse.

5.4 Mode 3: Input Capture Mode

IntheInputCapturemode,thetimerisusedtomeasureelapsedtime

betweenedgesofaninputsignal.Oncethetimerisconfiguredforthis

mode, the timer starts counting down immediately at the instruction

clockrate.TheTimer1willthentransferthecurrentvalueoftheTMR1

register into the T1RA register as soon as the selected edge of T1 is

sensed. The input signal on T1 must have a pulse width equal to or

greater than one instruction clock cycle. At every T1RA capture,

software can then store the values into RAM to calculate the elapsed

time between edges on T1. At any given time (with proper consider-

ation of the state of T1) the timer can be configured to capture on

positive-going or negative-going edges. A block diagram of the

timer’s Input Capture mode of operation is shown in Figure 17.

Remember that the Timer1 interrupt service routine must test the

T1C0andT1PNDflagstodeterminethecauseoftheinterrupt.Ifthe

T1C0 flag caused the interrupt, the interrupt service routine should

record the occurrence of an underflow by incrementing a counter in

memory or by some other means. The software that calculates the

elapsed time between captures should take into account the

number of underflow that occurred when making its calculation.

The timer has one interrupt (TMRI1) that is maskable through the

T1EN bit of the T1CNTRL register. However, the core is only

interruptediftheT1ENbitandtheG(GlobalInterruptenable)bitofthe

SR is set. The Input Capture mode contains two interrupt pending

flags 1) the TMR1 register capture in T1RA (T1PND) and 2) timer

underflow (T1C0). If interrupts are enabled, the timer will generate an

interrupteachtimeapendingflagisset(providedthatthependingflag

was previously cleared.) The interrupt service routine is responsible

for proper handling of the T1PND flag, T1C0 flag, and the T1EN bit.

The following steps show how to properly configure Timer 1 to

operate in the Input Capture mode.

1. Configure T1 as an input by clearing bit 2 of PORTGC.

-

RBIT 2, PORTGC

2. Initialize T1 to input with pull-up by setting bit 2 of PORTGD.

SBIT 2, PORTGD ; Set G2 high

3. Enable the global interrupt enable bit.

SBIT 4, STATUS

; Configure G2 as an input

For this operating mode, the T1C0 control bit serves as the timer

underflow interrupt pending flag. The Timer 1 interrupt service

routine must read both the T1PND and T1C0 flags to determine the

causeoftheinterrupt. AsetT1C0flagmeansthatatimerunderflow

occurred whereas a set T1PND flag means that a capture occurred

in T1RA. It is possible that both flags will be found set, meaning that

botheventsoccurredatthesametime.Theinterruptserviceroutine

should take this possibility into consideration.

-

4. With the timer stopped, load the initial time into the TMR1

register (typically the value is 0xFFFF.)

-

LD TMR1LO, #0FFH

LD TMR1HI, #00H

Because the T1C0 bit is used as the underflow interrupt pending

flag,itisnotavailableforuseasastart/stopbitasintheothermodes.

5. Write the appropriate control value to the T1CNTRL register

to select Input Capture mode, to sense the appropriate edge,

to set the enable bit, and to clear the pending flags. (See

Table 12 and 13)

The TMR1 register counts down continuously at the instruction

clock rate starting from the time that the input capture mode is

selected. (See Table 12 and 13) To stop the timer from running,

you must change the mode to an alternate mode (PWM or

External Event Counter) while resetting the T1C0 bit.

-

LD T1CNTRL, #64H

; T1C1 is the edge select bit

6. As soon as the input capture mode is enabled, the timer

starts counting. When the selected edge is sensed on T1,

the T1RA register is loaded and a Timer 1 interrupt is

triggered.

The input pins can be independently configured to sense positive-

going or negative-going transitions. The edge sensitivity of pin T1

is controlled by bit T1C1 as indicated in Table 13.

The edge sensitivity of a pin can be changed without leaving the

input capture mode even while the timer is running. This feature

allows you to measure the width of a pulse received on an input pin.

Figure 17: Input Capture Mode

Capture

Interrupt

16-bit Input Capture

Register (T1RA)

T1

Edge Selector

Logic

Data

Bus

Underflow

Interrupt

16-bit Timer (TMR1)

Instruction

Clock

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22

ACE1202 Product Family Rev. B.1

Once configured, the Difference Capture timer waits for the first

selected edge. when the edge transition has occurred, the 16-bit

timer starts counting up based every instruction clock cycle. It will

continue to count until the second selected edge transition occurs

at which time the timer stops and stores the elapse time into the

T1RA register.

5.5 Mode 4: Difference Input Capture Mode

The Difference Input Capture mode works similarly to the stan-

dard Input Capture mode. However, for the Difference Input

Capture the timer automatically captures the elapsed time be-

tween the selected edges without the core needing to perform the

calculation.

Software can now read the differnce between transitions directly

without using any processor resources. However, like the stan-

dard Input Capture mode both the capture (T1PND) and the

underflow (T1C0) flags must be monitored and handled appropri-

ately. ThisfeatureallowstheACExmicrocontrollertocapturevery

small pulses where standard microcontrollers might have missed

cycles due to the limited bandwidth.

For example, the standard Input Captrue mode requires that the

timer be configured to capture a particular edge (rising or falling)

at which time the timer's value is copied into the capture register.

if the elapsed time is required, software must move the captured

data into RAM and reconfigure the Input Capture mode to capture

onthenextedge(risingorfalling).Softwaremustthensubtractthe

difference between the two edges to yield useful information.

The Difference Capture mode eliminates the need for software

intervention and allows for capturing very short pulse or cycle

widths. it can be configured to capture the elapsed time between:

1. positive to negative-going edges

2. positive to positive-going edges

3. negative to positive-going edges

4. negative to negative-going edges

Figure 18: Difference Capture Mode

Capture

Interrupt

16-bit Input Capture

Register (T1RA)

Difference

Logic

T1

Data

Bus

Edge Selector

Logic

Underflow

Interrupt

16-bit Timer (TMR1)

Instruction

Clock

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23

ACE1202 Product Family Rev. B.1

reset by software or system reset.

6.0 Timer 0

The WKINTEN bit is used in the Multi-input Wakeup/Interrupt

block. See Section 8 for details.

Timer 0 is a 12-bit free running idle timer. Upon power-up or any

reset, the timer is reset to 0x000 and then counts up continuously

based on the instruction clock of 1MHz (1 µs). Software cannot

read from or write to this timer. However, software can monitor the

timer’s pending (T0PND) bit that is set every 8192 cycles (initially

4096 cycles after a reset). The T0PND flag is set every other time

the timer overflows (transitions from 0xFFF to 0x000) through a

divide-by-2circuit.Afteranoverflow,thetimerwillresetandrestart

its counting sequence.

7.0 Watchdog timer

TheWatchdogtimerisusedtoresetthedeviceandsafelyrecover

in the rare event of a processor “runaway condition.” The 12-bit

Timer0isusedasapre-scalerforWatchdogtimer.TheWatchdog

timer must be serviced before every 61,440 cycles but no sooner

than 4096 cycles since the last Watchdog reset. The Watchdog is

serviced through software by writing the value 0x1B to the

Watchdog Service (WDSVR) register (see Figure 20). The part

resets automatically if the Watchdog is serviced too frequent, or

not frequent enough.

Software can either poll the T0PND bit or vector to an interrupt

subroutine. In order to interrupt on a T0PND, software must be

sure to enable the Timer 0 interrupt enable (T0INTEN) bit in the

Timer 0 control (T0CNTRL) register and also make sure the G bit

is set in SR. Once the timer interrupt is serviced, software should

reset the T0PND bit before exiting the routine. Timer 0 supports

the following functions:

The Watchdog timer must be enabled through the Watchdog

enable bit (WDEN) in the initialization register. The WDEN bit can

onlybesetwhilethedeviceisinprogrammingmode.Onceset,the

Watchdog will always be powered-up enabled. Software cannot

disable the Watchdog. The Watchdog timer can only be disabled

in programming mode by resetting the WDEN bit as long as the

memory write protect (WDIS) feature is not enabled.

1. Exiting from IDLE mode (See Section 17.0 for details.)

2. Start up delay from HALT mode

3. Watchdog pre-scaler (See Section 7.0 for details.)

The T0INTEN bit is a read/write bit. If set to 0, interrupt requests

from the Timer 0 are ignored. If set to 1, interrupt requests are

accepted. Upon reset, the T0INTEN bit is reset to 0.

WARNING

Ensure that the Watchdog timer has been serviced before enter-

ing IDLE mode because it remains operational during this time.

TheT0PNDbitisaread/writebit.Ifsetto1,itindicatesthataTimer

0 interrupt is pending. This bit is set by a Timer 0 overflow and is

Figure 19: Timer 0 Control Register (T0CNTRL)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WKINTEN

x

T0PND

T0INTEN

Figure 20: Watchdog Server Register (WDSVR)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

0

1

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24

ACE1202 Product Family Rev. B.1

eitherportG2orG5.IfIOSELis1,G5isselectedastheoutputport

otherwise G2 is selected.

8.0 Hardware Bit-Coder (ACE1202-2 only)

The ACE1202-2 contains a dedicated hardware bit-encoding

peripheral block, Hardware Bit-Coder (HBC), for IR/RF data

transmission (see Figure 21.) The HBC is completely software

programmable and can be configured to emulate various bit-

encoding formats. The software developer has the freedom to

encode each bit of data into a desired pattern and output the

encodeddataatthedesiredfrequencythrougheithertheG2orG5

output (TX) ports.

The TXBUSY signal is read only and is used to inform software

that a transmission is in progress. TXBUSY goes high when the

encodeddatabeginstoshiftoutoftheoutputportandwillremains

high during each consecutive DAT0 frame bit transmission (see

Figure 25). The HBC will clear the TXBUSY signal when the last

DAT0 encodedbitof theframe istransmittedand the STOP signal

is 0.

TheSTART/STOPsignalcontrolstheencodingandtransmission

process for each data frame. When software sets the START /

STOP bit the DAT0 frame transmission process begins. The

START signal will remain high until the beginning of the last

encoded DAT0 frame bit transmission. The HBC then clears the

START / STOP bit allowing software to either continue with a new

DAT0 frame transmission or stop the transmission all together

(see Figure 25). If TXBUSY is 0 when the START signal is

enabled, a synchronization period occurs before any data is

transmitted lasting the amount of time to transmit a 0 encoded bit

(see Figure 24).

The HBC contains six 8-bit memory-mapped configuration regis-

tersPSCALE,HPATTERN,LPATTERN,BPSEL,HBCNTRL,and

DAT0. The registers are used to select the transmission fre-

quency, store the data bit-encoding patterns, configure the data

bit-pattern/frame lengths, and control the data transmission flow.

To select the IR/RF transmission frequency, an 8-bit divide

constant must be written into the IR/RF Pre-scalar (PSCALE)

register. The IR/RF transmission frequency generator divides the

1MHz instruction clock down by 4 and the PSCALE register is

used to select the desired IR/RF frequency shift. Together, the

transmission frequency range can be configured between 976Hz

(PSCALE = 0xFF) and 125kHz (PSCALE = 0x01). Upon a reset,

the PSCALE register is initialized to zero disabling the IR/RF

transmission frequency generator. However, once the PSCALE

register is programmed, the desired IR/RF frequency is main-

tained as long as the device is powered.

The OCFLAG signal is read only and goes high when the last

encoded bit of the DAT0 frame is transmitting. The OCFLAG

signalisusedtoinformsoftwarethattheDAT0frametransmission

operation is completing (see Figure 25). If multiple DAT0 frames

are to be transmitted consecutively, software should poll the

OCFLAG signal for a 1. Once OCFLAG is 1, DAT0 must be reload

and the START / STOP bit must be restored to 1 in order to begin

the new frame transmission without interruptions (the synchroni-

zation period). Since OCFLAG remains high during the entire last

encoded DAT0 frame bit transmission, software should wait for

the HBC to clear the OCFLAG signal before polling for the new

OCFLAGhighpulse. IfnewdataisnotreloadedintoDAT0andthe

START signal (STOP is active) is not set before the OCFLAG is

0, the transmission process will end (TXBUSY is cleared) and a

new process will begin starting with the synchronization period.

Once the transmission frequency is selected, the data bit-encod-

ing patterns must be stored in the appropriate registers. The HBC

contains two 8-bit bit-encoding pattern registers, High-pattern

(HPATTERN) and Low-pattern (LPATTERN). The encoding pat-

tern stored in the HPATTERN register is transmitted when the

data bit value to be encoded is a 1. Similarly, the pattern stored in

the LPATTERN register is transmitted when the data bit value to

be encoded is a 0. The HBC transmits each encoded pattern MSB

first.

The number of bits transmitted from the HPATTERN and

LPATTERN registers is software programmable through the Bit

PeriodConfiguration(BPSEL)register(seeFigure22). Duringthe

transmission of HPATTERN, the number of bits transmitted is

configuredbyBPH[2:0](BPSEL[2:0])whileBPL[2:0](BPSEL[5:3])

configures the number of transmitted bits for the LPATTERN. The

HBC allows from 2 (0x1) to 8 (0x7) encoding pattern bits to be

transmitted from each register. Upon a reset, BPSEL is initially 0

disabling the HBC from transmitting pattern bits from either

register.

Figure 24 and 25 shows how the HBC performs its data encoding.

Intheexample,twoframesareencodedandtransmittedconsecu-

tively with the following bit encoding format specification:

1. Transmission frequency = 62.5KHz

2. Data to be encoded = 0x52, 0x92 (all 8-bits)

3. Each bit should be encoded as a 3-bit binary value, ‘1’ =

110b and ‘0’ = 100b

4. Transmission output port : G2

To perform the data transmission, software must first initialize the

PSCALE, BPSEL, HPATTERN, LPATTERN, and DAT0 registers

with the appropriate values.

The Data (DAT0) register is used to store up to 8 bits of data to be

encoded and transmitted by the HBC. This data is shifted, bit by

bit,MSBtoLSBintoa1-bitdecisionregister.Iftheactivebitshifted

into the decision register is 1, the pattern in the HPATTERN

register is shifted out of the output port. Similarly, if the active bit

is 0 the pattern in the LPATTERN register is shifted out.

LD PSCALE, #03H

LD BPSEL, #012H

LD HPATTERN, #0C0H

LD LPATTERN, #090H

LD DAT0, #052H

; (1MHz ÷ 4) ÷ 4 = 62.5KHz

;BPH=2, BPL=2(3bitseach)

; HPATTERN = 0xC0

; LPATTERN = 0x90

The HBC control (HBCNTRL) register is used to configure and

control the data transmission. HBCNTRL is divided in 5 different

controlling signal FRAME[2:0], IOSEL, TXBUSY, START/STOP,

and OCFLAG (see Figure 23.)

; DAT0 = 0x52

Once the basic registers are initialized, the HBC can be started.

(At the same time, software must set the number of data bits per

data frame and select the desired output port.)

FRAME[2:0] selects the number of bits of DAT0 to encode and

transmit. The HBC allows from 2 (0x1) to 8 (0x7) DAT0 bits to be

encoded and transmitted. Upon a reset, FRAME is initialized to

zero disabling the DAT0’s decision register transmitting no data.

LD HBCNTRL, #27H

; START / STOP = 1,

FRAME = 7, IOSEL = 0

The IOSEL signal selects the transmission to output (TX) through

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25

ACE1202 Product Family Rev. B.1

After the HBC has started, software must then poll the OCFLAG

for a high pulse and restore the DAT0 register and the START

signal to continue with the next data transmission.

If software is to proceed with another data transmission, the

OCFLAG must be zero before polling for the next OCFLAG high

pulse.However,sincethespecificationintheexamplerequiresno

other data transmission software can proceed as desired.

LOOP_HI:

LOOP_LO:

IFBIT OCFLAG, HBCNTRL ; Wait for OCFLAG = 1

JP

NXT_FRAME

LOOP_HI

IFBIT OCFLAG, HBCNTRL ; Wait for OCFLAG = 0

JP

LOOP_LO

Etc.

; Program proceeds as desired

NXT_FRAME:

LD

DAT0, #092H

; DAT0 = 0x92

SBIT START, HBCNTRL

; START / STOP = 1

Figure 21: Hardware Bit-Coder (HBC) Block Diagram

IR/RF

CLOCK

RFCLK

b7

HPATTERN

LPATTERN

A

B

StopShift

Y

G2

G5

Fixed

Clock Divider

by 4

CPU

CLOCK

PSCALE

RFCLK

b7

StopShift

8

IOSEL

HBCNTRL[6]

[PSCALE]

ShiftCLK

Down

Counter

b7

DAT0

OCFLAG

NoShift

Sync

LOGIC

3

FRAME[2:0]

[HBCNTRL]

OCFLAG

HBCNTRL[7]

START/STOP

HBCNTRL[5]

Y

A

B

TXBUSY

HBCNTRL[4]

3

BPH[2:0]

[BPSEL]

BPL[2:0]

[BPSEL]

Figure 22: Bit Period Configuration (BPSEL) Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

BPL[2:0]

BPH[2:0]

Figure 23: HBC Control (HBCNTRL) Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

OCFLAG

IOSEL

START/STOP

TXBUSY

0

FRAME[2:0]

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26

ACE1202 Product Family Rev. B.1

Figure 24: HBC signals for one byte message in PWM format

Condition:

BPSEL = 0x12 [ "1", " 0 " = 3 * IR/RF Clocks]

DAT0 = 0x52

No. bit to encode = 8 (HBCNTRL = XXXX0111b)

TXBUSY

START/STOP

ShiftCLK

OCFLAG

SYNC

Period

"0"

Bit 7

DAT0

"0"

"1"

"0"

"1"

"0"

"1"

G2/G5

Output

IR/RF

CLOCK

¡

Figure 25: Sending series of encoded messages

Conditions:

BPSEL = 0x12 [ "1", " 0 " = 3 * IR/RF Clocks]

DAT0 = 0x52 , 0x92

No. bit to encode = 8 (HBCNTRL = XXXX0111b)

Software must set the START bit while OCFLAG is set in

order to send another message without introducing a delay.

TXBUSY

STOP bit clear,

transmission ends.

START/STOP

ShiftCLK

OCFLAG

SYNC

Period

Bit 7

"0"

"0" "0" "1" "0" "1" "0" "0" "1" "0" "1" "0" "0" "1" "0" "0" "1"

DAT0

G2/G5

Output

IR/RF

CLOCK

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27

ACE1202 Product Family Rev. B.1

6. Set the WKEN bits associated with the pins to be used, thus

enabling those pins for the Wakeup/Interrupt function.

9.0 Multi-Input Wakeup/Interrupt Block

TheMulti-InputWakeup(MIW)/Interruptcontainsthreememory-mapped

registers associated with this circuit: WKEDG (Wakeup Edge), WKEN

(Wakeup Enable), and WKPND (Wakeup Pending). Each register has

8-bits with each bit corresponding to an input pins as shown in Figure

26. All three registers are initialized to zero upon reset.

-

LD WKEN, #10H

; Enabling G4

Once the Multi-Input Wakeup/Interrupt function has been config-

ured, a transition sensed on any of the I/O pins will set the

corresponding bit in the WKPND register. The WKPND bits , where

thecorrespondingenable(WKEN)bitsareset, willbringthedevice

out of the HALT mode and can also trigger an interrupt if interrupts

are enabled. The interrupt service routine can read the WKPND

register to determine which pin sensed the interrupt.

The WKEDG register establishes the edge sensitivity for each of

the wake-up input pin: either positive going-edge (0) or negative-

going edge (1).

The WKEN register enables (1) or disables (0) each of the port

pins for the Wakeup/Interrupt function. The wakeup I/Os used for

theWakeup/Interruptfunctionmustalsobeconfiguredasaninput

pin in its associated port configuration register. However, an

interrupt of thecore willnot occurunlessinterruptsareenabled for

the blockviabit 7ofthe T0CNTRLregister(seeFigure19) andthe

G (global interrupt enable) bit of the SR is set.

The interrupt service routine or other software should clear the

pending bit. The device will not enter HALT mode as long as a

WKPND pending bit is pending and enabled. The user has the

responsibility of clearing the pending flags before attempting to

enter the HALT mode.

Upon reset, the WKEDG register is configured to select positive-

going edge sensitivity for all wakeup inputs. If the user wishes to

change the edge sensitivity of a port pin, use the following proce-

dure to avoid false triggering of a Wakeup/Interrupt condition.

The WKPND register contains the pending flags corresponding to

each of the port pins (1 for wakeup/interrupt pending, 0 for

wakeup/interrupt not pending).

1. Clear the WKEN bit associated with the pin to disable that pin.

TousetheMulti-InputWakeup/Interruptcircuit,performthestepslisted

below. Performing the steps in the order shown will prevent false

triggering of a Wakeup/Interrupt condition. This same procedure

should be used following any type of reset because the wakeup inputs

areleftfloatingafterresetsresultinginunknowndataontheportinputs.

2. Write the WKEDG register to select the new type of edge

sensitivity for the pin.

3. Clear the WKPND bit associated with the pin.

4. Set the WKEN bit associated with the pin to re-enable it.

PORTG provides the user with three fully selectable, edge sensi-

tive interrupts that are all vectored into the same service subrou-

tine. The interrupt from PORTG shares logic with the wakeup

circuitry. The WKEN register allows interrupts from PORTG to be

individually enabled or disabled. The WKEDG register specifies

the trigger condition to be either a positive or a negative edge. The

WKPND register latches in the pending trigger conditions.

1. Clear the WKEN register.

-

CLR WKEN

2. If necessary, write to the port configuration register to select

the desired port pins to be configured as inputs.

-

RBIT 4, PORTGC

; G4

3. If necessary, write to the port data register to select the

desired port pins input state.

Since PORTG is also used for exiting the device from the HALT mode,

theusercanelecttoexittheHALTmodeeitherwithorwithouttheinterrupt

enabled.Iftheuserelectstodisabletheinterrupt,thenthedevicerestarts

execution from the point at which it was stopped (first instruction cycle of

the instruction following HALT mode entrance instruction). In the other

case,thedevicefinishestheinstructionthatwasbeingexecutedwhenthe

part was stopped and then branches to the interrupt service routine. The

device then reverts to normal operation.

-

SBIT 4, PORTGD

; Pull-up

4. Write the WKEDG register to select the desired type of edge

sensitivity for each of the pins used.

-

LD WKEDG, #0FFH

5. Clear the WKPND register to cancel any pending bits.

CLR WKPND

; All negative-going edges

-

Figure 26: Multi-input Wakeup (MIW) Register bit assignments

WKEDG, WKEN, WKPND

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

¹¹G7

¹¹G6

G5

G4

G3

G2

G1

G0

¹¹Available only on the 14-pin package option

Figure 27: Multi-input Wakeup (MIW) Block Diagram

Data Bus

7

0

WKEN[7:0]

0

G0

G7

WKOUT

EDGEI

7

WKINTEN¹¹

WKEDG[0:7]

WKPND[0:7]

¹²WKINTEN: Bit 7 of T0CNTRL

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28

ACE1202 Product Family Rev. B.1

(PORTGC), a port data register (PORTGD), and a port input

register (PORTGP). PORTGC is used to configure the pins as

inputs or outputs. A pin may be configured as an input by writing

a 0or as anoutputby writinga 1to itscorresponding PORTGC bit.

If a pin is configured as an output, its PORTGD bit represents the

state of the pin (1 = logic high, 0 = logic low). If the pin is configured

as an input, its PORTGD bit selects whether the pin is a weak pull-

uporahigh-impedenceinput. Table14providesdetailsoftheport

configuration options. The port configuration and data registers

can both be read from or written to. Reading PORTGP returns the

value of the port pins regardless of how the pins are configured.

Since this device supports MIW, PORTG inputs have Schmitt

triggers.

10.0 I/O Port

The eight I/O pins (six on 8-pin package option) are bi-directional

(see Figure 28) with the exception of G3 which is always an input

with weak pull-up. The bi-directional I/O pins can be individually

configured by software to operate as high-impedance inputs, as

inputs with weak pull-up, or as push-pull outputs. The operating

state is determined by the contents of the corresponding bits in the

data and configuration registers. Each bi-directional I/O pin can be

used for general purpose I/O, or in some cases, for a specific

alternate function determined by the on-chip hardware.

10.1 I/O registers

The I/O pins (G0-G7) have three memory-mapped port registers

associated with the I/O circuitry: a port configuration register

Figure 28: PORTG Logic Diagram

GXPULLEN

GXBUFEN

GXOUT

PADGX

GXIN

Figure 29: I/O Register bit assignments (PORTGC,PORTGD, PORTGD)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

¹³G7

¹³G6

G5

G4

¹⁴G3

G2

G1

G0

¹³Available only on the 14-pin package option

¹⁴G3 is always an input with weak pull-up

Table 14: I/O configuration options

Configuration Bit

Data Bit

Port Pin Configuration

0

1

0

1

0

1

High-impedence input (TRI-STATE input)

Input with pull-up (weak one input)

Push-pull zero output

Push-pull one output

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29

ACE1202 Product Family Rev. B.1

11.0 In-circuit Programming Specification^15,16

The ACEx microcontroller supports in-circuit programming of the

internaldataEEPROM,codeEEPROM,andtheinitializationregisters.

0V phase (if the timing specifications in Figure 30 are obeyed).

The device will set the R bit of the Status register when the write

operation has completed. The external programmer must wait for

the SHIFT_OUT pin to go high before bringing the LOAD signal to

5V to initiate a normal command cycle.

An externally controlled four wire interface consisting of a LOAD

control pin (G3), a serial data SHIFT-IN input pin (G4), a serial data

SHIFT-OUToutputpin(G2),andaCLOCKpin(G1)isusedtoaccess

the on-chip memory locations. Communication between the ACEx

microcontroller and the external programmer is made through a 32-

bit command and response word described in Table 15.

11.2 Read Sequence

When reading the device after a write, the external programmer

must set the LOAD signal to 5V before it sends the new command

word. Next, the 32-bit serial command word (for during a READ)

should be shifted into the device using the SHIFT_IN and the

CLOCK signals while the data from the previous command is

serially shifted out on the SHIFT_OUT pin. After the Read com-

mand has been shifted into the device, the external programmer

must, once again, set the LOAD signal to 0V and apply two clock

pulses as shown in Figure 30 to complete READ cycle. Data from

the selected memory location, will be latched into the lower 8 bits

of the command word shortly after the second rising edge of the

CLOCK signal.

The serial data timing for the four-wire interface is shown in Figure

31 and the programming protocol is shown in Figure 30.

11.1 Write Sequence

The external programmer brings the ACEx microcontroller into

programming mode by applying a super voltage level to the LOAD

pin. TheexternalprogrammerthenneedstosettheLOADpinto5V

beforeshiftinginthe32-bitserialcommandwordusingtheSHIFT_IN

and CLOCK signals. By definition, bit 31 of the command word is

shifted in first. At the same time, the ACEx microcontroller shifts out

the 32-bit serial response to the last command on the SHIFT_OUT

pin. It is recommended that the external programmer samples this

signal t_ACCESS(500ns) after the rising edge of the CLOCK signal.

Theserialresponseword,sentimmediatelyafterenteringprogram-

ming mode, contains indeterminate data.

Writing a series of bytes to the device is achieved by sending a

series of Write command words while observing the devices

handshaking requirements.

Reading a series of bytes from the device is achieved by sending

a series of Read command words with the desired addresses in

sequence and reading the following response words to verify the

correct address and data contents.

After 32 bits have been shifted into the device, the external

programmer must set the LOAD signal to 0V, and then apply two

clock pulses as shown in Figure 30 to complete program cycle.

The addresses of the data EEPROM and code EEPROM loca-

tions are the same as those used in normal operation.

The SHIFT_OUT pin acts as the handshaking signal between the

device and programming hardware once the LOAD signal is

brought low. The device sets SHIFT_OUT low by the time the

programmer has sent the second rising edge during the LOAD =

Powering down the device will cause the part to exit programming

mode.

Table 15: 32-Bit Command and Response Word

Bit number

bits 31 – 30

bit 29

Input command word

Output response word

Must be set to 0

X

Set to 1 to read/write data EEPROM, or the

initialization registers, otherwise 0

bit 28

Set to 1 to read/write code EEPROM,

otherwise 0

X

bits 27 – 25

bit 24

Must be set to 0

X

Set to 1 to read, 0 to write

Must be set to 0

X

bits 23 – 19

bits 18 – 8

bits 7 – 0

X

Address of the byte to be read or written

Same as Input command word

Data to be programm ed or zero if data is to be read

Programmed data or data read at specified address

¹⁵For further information see Application Note AN-8005.

¹⁶During in-circuit programming, G5 must be either not connected or driven high.

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30

ACE1202 Product Family Rev. B.1

Figure 30: Programming Protocol¹⁶

A

t_SV1t_SV2

t_load1t_load2

t_ready

t_load3t_load4

enter prog.

mode

LOAD (G3)

32 clock pulses

CLOCK (G1)

bit 31

bit 30

bit 0

bit 31

SHIFT_IN (G4)

BUSY low by

2nd clock pulse

READY

SHIFT_OUT (G2)

(in write mode)

BUSY

SHIFT_OUT (G2)

(in read mode)

A: start of programming cycle

Figure 31: Serial Data Timing

t_HI

t_LO

CLOCK (G1)

t_DIS

t_DIH

Valid

SHIFT_IN (G4)

t_DOS

t_DOH

Valid

SHIFT_OUT (G2)

t_ACCESS

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31

ACE1202 Product Family Rev. B.1

zero before rising back to operating range. The Brown-out Reset

canbethoughtofasasupplementfunctiontothePower-onReset

when V_CCdoes not fall below ~1.5V. The Power-on Reset circuit

works best when V_CCstarts from zero and rises sharply. So in

applications where V_CCis not constant, the BOR will give added

device stability.

12.0 Brown-out/Low Battery Detect Circuit

The Brown-out Reset (BOR) and Low Battery Detect (LBD)

circuits on the ACEx microcontroller have been designed to offer

two types of voltage reference comparators. The sections below

will describe the functionality of both circuits.

Figure 32: BOR/LBD Block Diagram

The BOR circuit must be enabled through the BOR enable bit

(BOREN) in the initialization register. The BOREN bit can only be

set while the device is in programming mode. Once set, the BOR

will always be powered-up enabled. Software cannot disable the

BOR. The BOR can only be disabled in programming mode by

resettingtheBORENbitaslongastheglobalwriteprotect(WDIS)

feature is not enabled.

Vcc

0

1.8V

_

1

2.2V

BOR

+

to RESET logic

S

BLSEL¹⁷

¹⁸BOR is not available on the P.N. ACE1202B/ACE12022B device

_

+

LBD

12.2 Low Battery Detect

Adjust Reference Voltage

The Low Battery Detect (LBD) circuit allows software to monitor

the V_CClevel at the lower voltage ranges. LBD has an eight level

software programmable voltage reference threshold that can be

changed on the fly. Once V_CCfalls below the selected threshold,

the LBD flag in the LBD control register is set. The LBD flag will

hold its value until V_CCrises above the threshold. (See Table 16)

LBD

Control

Register

7

6

5

4

3

2

1

0

¹⁷See Figure 14 for information on BLSEL.

12.1 Brown Out Reset ¹⁸

The LBD bit is read only. If LBD is 0, it indicates that the V_CClevel

is higher than the selected threshold. If LBD is 1, it indicates that

the V_CClevel is below the selected threshold. The threshold level

can be adjusted up to eight levels using the three trim bits

(Bat_trim[2:0]) of the LBD control register. The LBD flag does not

cause any hardware actions or an interruption of the processor. It

is for software monitoring only.

The Brown-out Reset (BOR) function is used to hold the device in

reset when V_CCdrops below a fixed threshold. (See BOR Electri-

cal Characteristics for threshold voltage.) While in reset, the

device is held in its initial condition until V_CCrises above the

threshold value. Shortly after V_CCrises above the thresholdvalue,

aninternalresetsequenceisstarted.Aftertheresetsequence,the

core fetches the first instruction and starts normal operation.

The LBD function is disabled during HALT/IDLE mode. After

exiting HALT/IDLE, software must wait at least 10 µs before

reading the LBD bit to ensure that the internal circuit has stabi-

lized.

On the devices, the BOR should be used in situations when V_CC

rises and falls slowly and in situations when V_CCdoes not fall to

Table 16: LBD Control Register Definition

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bat_trim[2:0]

0

X

LBD

Voltage

Reference

Bat_trim[0] Range ( 20%)

Level

Bat_trim[2]

Bat_trim[1]

1

2

3

4

5

6

7

8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2.9 - 3.0

2.8 - 2.9

2.7 - 2.8

2.6 - 2.7

2.5 - 2.6

2.4 - 2.5

2.3 - 2.4

2.2 - 2.3

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32

ACE1202 Product Family Rev. B.1

The external reset provides a way to properly reset the ACEx

microcontroller if POR cannot be used in the application. The

external reset pin contains an internal pull-up resistor. Therefore,

to reset the device the reset pin should be held low for at least 2ms

so that the internal clock has enough time to stabilize.

13.0 RESET block

When a RESET sequence is initiated, all I/O registers will be reset

setting all I/Os to high-impedence inputs. The system clock is

restarted after the required clock start-up delay. A reset is gener-

ated by any one of the following three conditions:

15.0 CLOCK

• Power-on Reset (as described in Section 14.0)

• Brown-out Reset (as described in Section 12.1)

• Watchdog Reset (as described in Section 7.0)

The ACEx microcontroller has an on-board oscillator trimmed to

a frequency of 2MHz who is divided down by two yielding a 1MHz

frequency. (See AC Electrical Characteristics.) Upon power-up,

the on-chip oscillator runs continuously unless entering HALT

mode or using an external clock source.

• External Reset¹⁸(as described in Section 14.0)

¹⁸Available only on the 14-pin package option.

14.0 Power-On-Reset

Ifrequired,anexternaloscillatorcircuitmaybeuseddependingon

the states of the CMODE bits of the initialization register. (See

Table 17) When the device is driven using an external clock, the

clock input to the device (G1/CKI) can range between DC to

4MHz. For external crystal configuration, the output clock (CKO)

is on the G0 pin. (See Figure 34) If an external crystal or RC is

used, internally the input frequency (CKI) is divided-down by four

to yield the corresponding instruction clock. If the device is

configured for an external square clock, it will not be divided.

The Power-On Reset (POR) circuit is guaranteed to work if the

rate of rise of V_CCis no slower than 10ms/1volt. The POR circuit

wasdesignedtorespondtofastlowtohightransitionsbetween0V

and V_CC. The circuit will not work if V_CCdoes not drop to 0V before

thenextpower-upsequence. Inapplicationswhere1)the V_CCrise

is slower than 10ms/1 volt or 2) V_CCdoes not drop to 0v before the

nextpower-upsequencetheexternalresetoptionshouldbeused.

Table 17: CMODEx Bit Definition

CMODE[1]

CMODE[0]

Clock Type

Internal 1 MHz clock

0

1

0

1

0

1

External square clock

External crystal/resonator

External RC clock

Figure 33: BOR and POR Circuit Relationship Diagram

V

(Pin 8)

CC

BOR

output

V

CC

V

CC

1.75

0

V

CC

0

Reset

circuit

output

Global Reset

to Logic

Time

BOR Output

A

POR

output

External

Reset

B

The Reset circuit will trigger

when inputs A or B transition

from High to Low. At that time

the Global Reset signal will go

high which will reset all controller

logic. The Global Reset will go

high and stay high for around 1µs.

V

CC

(14-Pin Only)

5.0V

1.8V

0

(Pin 7)

V

CC

POR Output

Pulse

POR

output

0

www.fairchildsemi.com

33

ACE1202 Product Family Rev. B.1

Figure 34: Crystal (a) and RC (b) Oscillator Diagrams

a)

b)

CKI

(G1)

CKO

(G0)

CKI

(G1)

CKO

(G0)

1M

R

V

CC

C

33pF

15.0 HALT Mode

17.0 IDLE Mode

The HALT mode is a power saving feature that almost completely

shuts down the device for current conservation. The device is

placed into HALT mode by setting the HALT enable bit (EHALT)

of the HALT register through software using only the “LD M, #”

instruction. EHALT is a write only bit and is automatically cleared

upon exiting HALT. When entering HALT, the internal oscillator

and all the on-chip systems including the LBD and the BOR

circuits are shut down.

In addition to the HALT mode power saving feature, the device

also supports an IDLE mode operation. The device is placed into

IDLE mode by setting the IDLE enable bit (EIDLE) of the HALT

register through software using only the “LD M, #” instruction.

EIDLE is a write only bit and is automatically cleared upon exiting

IDLE. The IDLE mode operation is similar to HALT except the

internal oscillator, the Watchdog, and the Timer 0 remain active

while the other on-chip systems including the LBD and the BOR

circuits are shut down.

The device can exit HALT mode only by the MIW circuit. There-

fore, prior to entering HALT mode, software must configure the

MIW circuit accordingly. (See Section 9) After a wakeup from

HALT, a 1ms start-up delay is initiated to allow the internal

oscillator to stabilize before normal execution resumes. Immedi-

ately after exiting HALT, software must clear the Power Mode

Clear (PMC) register by only using the “LD M, #” instruction. (See

Figure 36)

The device automatically wakes from IDLE mode by the Timer 0

overflow every 8192 cycles (see Section 6). Before entering IDLE

mode, software must clear the WKEN register to disable the MIW

block. OnceawakefromIDLEmodeistriggered, thecorewillbegin

normal operation by the next clock cycle. Immediately after exiting

IDLE mode, software must clear the Power Mode Clear (PMC)

register by using only the "LD M, #" instruction. (See Figure 37)

Figure 35: HALT Register Definition

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

undefined

EIDLE

EHALT

Figure 36: Recommended HALT Flow

Figure 37: Recommended IDLE Flow

Normal Mode

CLR WKEN

LD HALT, #02h

LD HALT, #01h

Multi-Input

Halt

Timer 0

IDLE

Wakeup

Overflow

LD PMC, #00h

Resume

Normal Mode

Resume

Normal Mode

www.fairchildsemi.com

34

ACE1202 Product Family Rev. B.1

Ordering Information (ACE1202)

Part Number

Core Type

Max. #

I/Os

Program

Memory Size

Operating Voltage

Range

Temperature Range

Package

Tape &

Reel

0

1

2

8

1K

2K

1.8 – 2.2 – 2.7 – 0 to

5.5V 5.5V 5.5V 70°C +85C +125°C SOIC

-40 to -40 to

8-pin

14-pin

SOIC

8-pin

DIP

14-pin

DIP

ACE1202M8

X

ACE1202M8X

ACE1202M

X

ACE1202MX

ACE1202N

X

ACE1202N14

ACE1202EM8

ACE1202EM8X

ACE1202EM

X

ACE1202EMX

ACE1202EN

ACE1202EN14

ACE1202VM8

ACE1202VM8X

ACE1202VM

X

ACE1202VMX

ACE1202VN

ACE1202VN14

ACE1202BM8

ACE1202BM8X

ACE1202BM

X

ACE1202BMX

ACE1202BN

ACE1202BN14

ACE1202BEM8

ACE1202BEM8X

ACE1202BEM

ACE1202BEMX

ACE1202BEN

ACE1202BEN14

ACE1202BVM8

ACE1202BVM8X

ACE1202BVM

ACE1202BVMX

ACE1202BVN

ACE1202BVN14

ACE1202LM8

ACE1202LM8X

ACE1202LM

X

ACE1202LMX

ACE1202LN

ACE1202LN14

www.fairchildsemi.com

35

ACE1202 Product Family Rev. B.1

Ordering Information (ACE1202-2)

Part Number

Core Type

Max. #

I/Os

Program

Memory Size

Operating Voltage

Range

Temperature Range

Package

Tape &

Reel

0

1

2

8

1K

2K

1.8 – 2.2 – 2.7 – 0 to

5.5V 5.5V 5.5V 70°C +85C +125°C SOIC

-40 to -40 to

8-pin

14-pin

SOIC

8-pin

DIP

14-pin

DIP

ACE12022M8

X

ACE12022M8X

ACE12022M

X

ACE12022MX

ACE12022N

X

ACE12022N14

ACE12022EM8

ACE12022EM8X

ACE12022EM

X

ACE12022EMX

ACE12022EN

ACE12022EN14

ACE12022VM8

ACE12022VM8X

ACE12022VM

X

ACE12022VMX

ACE12022VN

ACE12022VN14

ACE12022BM8

ACE12022BM8X

ACE12022BM

X

ACE12022BMX

ACE12022BN

ACE12022BN14

ACE12022BEM8

ACE12022BEM8X

ACE12022BEM

ACE12022BEMX

ACE12022BEN

ACE12022BEN14

ACE12022BVM8

ACE12022BVM8X

ACE12022BVM

ACE12022BVMX

ACE12022BVN

ACE12022BVN14

X

www.fairchildsemi.com

36

ACE1202 Product Family Rev. B.1

Physical Dimensions inches (millimeters) unless otherwise noted

0.189 - 0.197

(4.800 - 5.004)

8

7

6

5

0.228 - 0.244

(5.791 - 6.198)

1

2

3

4

Lead #1

IDENT

0.150 - 0.157

(3.810 - 3.988)

0.053 - 0.069

(1.346 - 1.753)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45¡

8¡ Max, Typ.

All leads

Seating

Plane

0.004

(0.102)

All lead tips

0.0075 - 0.0098

(0.190 - 0.249)

Typ. All Leads

0.014

(0.356)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

0.050

(1.270)

Typ

0.014 - 0.020

Typ.

(0.356 - 0.508)

Molded Small Out-Line Package (M8)

Order Number ACE1202(12022, 1202L)M8/ACE1202(12022)EM8/ACE1202VM8

ACE1202(12022)BM8/ACE1202(12022)BEM8/ACE1202(12022)BVM8

Package Number M08A

0.373 - 0.400

(9.474 - 10.16)

0.090

(2.286)

8

7

0.032 0.005

(0.813 0.127)

RAD

8

7

6

5

4

0.092

(2.337)

DIA

0.250 - 0.005

(6.35 0.127)

Pin #1

IDENT

+

Pin #1 IDENT

1

Option 1

1

2

3

Option 2

0.280

MIN

0.040

(1.016)

Typ.

(7.112)

0.030

0.145 - 0.200

(3.683 - 5.080)

0.039

(0.991)

MAX

(0.762)

0.300 - 0.320

(7.62 - 8.128)

20° 1°

0.130 0.005

(3.302 0.127)

0.125 - 0.140

95° 5°

(3.175 - 3.556)

0.065

(1.651)

0.125

(3.175)

DIA

0.020

90° 4°

Typ

0.009 - 0.015

(0.229 - 0.381)

(0.508)

Min

NOM

0.018 0.003

(0.457 0.076)

+0.040

-0.015

0.325

0.100 0.010

+1.016

-0.381

8.255

(2.540 0.254)

0.045 0.015

(1.143 0.381)

0.060

(1.524)

0.050

(1.270)

8-Pin DIP (N)

Order Number ACE1202(12022, 1202L)N/ACE1202(12022)EN/ACE1202VN

ACE1202(12022)BN/ACE1202(12022)BEN/ACE1202(12022)BVN

Package Number N08A

www.fairchildsemi.com

37

ACE1202 Product Family Rev. B.1

Physical Dimensions inches (millimeters) unless otherwise noted

0.335 - 0.344

(8.509 - 8.788)

14 13 12 11 10

9

6

8

7

0.228 - 0.244

0.010

(0.254)

(5.791 - 6.198)

Max.

1

2

3

4

5

Lead #1

IDENT

30° Typ.

0.150 - 0.157

0.053 - 0.069

(1.346 - 1.753)

(3.810 - 3.988)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45°

8° Max, Typ.

All leads

Seating

Plane

0.04

0.014

(0.356)

(0.102)

All lead tips

0.008 - 0.010

(0.203 - 0.254)

Typ. all leads

0.050

(1.270)

Typ

0.014 - 0.020

(0.356 - 0.508)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

Typ.

0.008

(0.203)

Typ

Molded Small Out-Line Package (M)

Order Number ACE1202(12022, 1202L)M/ACE1202(12022)EM/ACE1202VM

ACE1202(12022)BM/ACE1202(12022)BEM/ACE1202(12022)BVM

Package Number M14A

14-Pin DIP (N14)

Order Number ACE1202(12022, 1202L)N14/ACE1202(12022)EN14/ACE1202VN14

ACE1202(12022)BN14/ACE1202(12022)BEN14/ACE1202(12022)BVN14

Package Number N14A

www.fairchildsemi.com

38

ACE1202 Product Family Rev. B.1

ACEx Emulator Kit: Fairchild also offers a low cost real-time in-

circuit emulator kit that includes:

ACEx Development Tools

General Information

Emulator board

Emulator software

Assembler and Manuals

Power supply

Fairchild Semiconductor offers different possibilities to evaluate

and emulate software written for ACEx.

ACEx Starter Kit includes:

Programmer Board

DIP14 target cable

PC cable

Simulator Software

Programmer Software

Assembler and Manuals

Cables and samples devices

DIP programming sockets

The ACEx emulator allows for debugging the program code in a

symbolic format. It is possible to place one breakpoint and watch

various data locations. It also has built-in programming capability.

Prototype Board Kits: Fairchild offer two solutions for the simpli-

fication of the breadboard operation so that ACEx Applications

can be quickly tested.

Programmer board: Interfaces with a PC through a Windows

program using the serial communication port. This board is

intended for engineering prototype and can be used for small

volume production. Fairchild offers factory pre-programming and

serialization (for justified quantities) for a small additional cost.

Please refer to your local distributor for details regarding factory

programming.

1) ACEDEMO is can be used for general purpose applications

2) ACETXRX for transmitting / receiving (RF, IR, RS232,

RS485) applications.

ACEDEMO has 8 switches, 8 LEDs, RS232 voltage translator,

buzzer, and a lamp with a small breadboard area.

Simulator: Is a Windows program able to load, assemble, and

debugACExprograms.Itispossibletoplaceasmanybreakpoints

as needed, trace the program execution in symbolic format, and

program a device with the proper options. The ACEx Simulator is

available free-of-charge and can be downloaded from Fairchild’s

web site at www.fairchildsemi.com/products/memory/ace

Ordering P/Ns

Starter Kit:

ACESTART1101

ACESTART1202

Programming Adapters:

DIP8 - ACESDIP8

DIP14 - ACESDIP14

TSSOP8 - ACESTSSOP8

SO8 - ACESSOP8

SO14 - ACESSOP15

Emulator Kit: ACEICE (110Vac)

ACEICE_EU (220Vac)

Prototype Boards:

ACEDEMO

ACETXRX (specify RF freq. 433 or 315MHz)

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

Fairchild Semiconductor

Americas

Fairchild Semiconductor

Europe

Fairchild Semiconductor

Hong Kong

Fairchild Semiconductor

Japan Ltd.

Customer Response Center

Tel. 1-888-522-5372

Fax:

Tel:

+44 (0) 1793-856858

8/F, Room 808, Empire Centre

68 Mody Road, Tsimshatsui East

Kowloon. Hong Kong

Tel; +852-2722-8338

Fax: +852-2722-8383

4F, Natsume Bldg.

Deutsch

English

Français

Italiano

+49 (0) 8141-6102-0

+44 (0) 1793-856856

+33 (0) 1-6930-3696

+39 (0) 2-249111-1

2-18-6, Yushima, Bunkyo-ku

Tokyo, 113-0034 Japan

Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

www.fairchildsemi.com

39

ACE1202 Product Family Rev. B.1


型号：	ACE12022MX
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Arithmetic Controller Engine (ACEx⑩) for Low Power Applications 运算器引擎（ ACEx⑩ ）针对低功耗应用
文件：	总39页 (文件大小：2121K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ACE12022MX [FAIRCHILD]

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