74VHC112SJ [FAIRCHILD]
Dual J-K Flip-Flops with Preset and Clear; 双J-K·触发器与预置和清除
| 型号： | 74VHC112SJ |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual J-K Flip-Flops with Preset and Clear |
| 文件： | 总7页 (文件大小：73K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1995
Revised April 1999
74VHC112
Dual J-K Flip-Flops with Preset and Clear
Simultaneous LOW signals on PR and CLR force both Q
and Q HIGH.
General Description
The VHC112 is an advanced high speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
The VHC112 contains two independent, high-speed JK flip-
flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trig-
gering occurs at a voltage level of the clock and is not
directly related to transition time. The J and K inputs can
change when the clock is in either state without affecting
the flip-flop, provided that they are in the desired state dur-
ing the recommended setup and hold times relative to the
falling edge of the clock. The LOW signal on PR or CLR
prevents clocking and forces Q and Q HIGH, respectively.
Features
■ High speed: fMAX = 200 MHz (typ) at VCC = 5.0V
■ Low power dissipation: ICC = 2 µA (max) at TA = 25°C
■ High noise immunity: VNIH = VNIL = 28% VCC (min)
■ Power down protection is provided on all inputs
■ Pin and function compatible with 74HC112
Ordering Code:
Order Number Package Number
Package Description
74VHC112M
74VHC112SJ
74VHC112MTC
74VHC112N
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
J1, J2, K1, K2
CLK1, CLK2
CLR1, CLR2
PR1, PR2
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Preset Inputs (Active LOW)
Outputs
Q1, Q2, Q1, Q2
© 1999 Fairchild Semiconductor Corporation
DS012123.prf
www.fairchildsemi.com
Truth Table
Inputs
Outputs
PR
L
CLR
H
CP
X
J
X
X
X
h
l
K
X
X
X
h
h
l
Q
H
Q
L
H
L
L
X
L
H
L
X
H
H
H
H
H
H
H
Q0
L
Q0
H
H
H
h
l
H
L
H
l
Q0
Q0
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Clock Transition
Q
(Q ) = Before HIGH-to-LOW Transition of Clock
0
0
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
(One Half Shown)
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Input Diode Current (IIK
Output Diode Current (IOK
DC Output Current (IOUT
DC VCC/GND Current (ICC
)
−0.5V to +7.0V
−0.5V to +7.0V
−0.5V to VCC + 0.5V
−20 mA
)
Supply Voltage (VCC
Input Voltage (VIN
Output Voltage (VOUT
Operating Temperature (TOPR
Input Rise and Fall Time (tr, tf)
)
2.0V to +5.5V
0V to +5.5V
)
)
)
)
0V to VCC
)
±20 mA
)
−40°C to +85°C
)
±25 mA
)
±50 mA
V
CC = 3.3V ± 0.3V
CC = 5.0V ± 0.5V
0
100 ns/V
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
−65°C to +150°C
V
0 20 ns/V
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
260°C
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Min
Typ
Max
Min
1.50
0.7 V
Max
V
HIGH Level
2.0
1.50
IH
V
V
Input Voltage
LOW Level
3.0 − 5.5 0.7 V
2.0
CC
CC
V
V
0.50
0.50
IL
Input Voltage
HIGH Level
Output Voltage
3.0 − 5.5
0.3 V
0.3 V
CC
CC
2.0
3.0
1.9
2.0
3.0
4.5
1.9
2.9
V
V
= V
I
= −50 µA
OH
IN
IH
OH
2.9
4.4
V
V
V
V
or V
IL
4.5
4.4
3.0
2.58
3.94
2.48
3.80
I
I
I
= −4 mA
= −8 mA
= 50 µA
OH
OH
OL
4.5
V
LOW Level
2.0
0.0
0.0
0.0
0.1
0.1
0.1
0.1
= V
IN
OL
IH
Output Voltage
3.0
or V
IL
4.5
0.1
0.1
3.0
0.36
0.36
±0.1
2.0
0.44
0.44
±1.0
20.0
I
I
= 4 mA
= 8 mA
OL
OL
4.5
I
Input Leakage Current
0 − 5.5
5.5
µA
µA
V
= 5.5V or GND
IN
IN
IN
I
Quiescent Supply Current
V
= V or GND
CC
CC
3
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AC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
MHz
MHz
ns
Conditions
= 15 pF
Min
110
90
Typ
150
120
200
185
8.5
Max
Min
Max
f
Maximum Clock
3.3 ± 0.3
100
80
C
C
C
C
C
C
MAX
L
L
L
L
L
L
Frequency
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
5.0 ± 0.5
3.3 ± 0.3
150
120
135
110
1.0
1.0
t
t
Propagation Delay
11.0
15.0
13.4
16.5
PLH
PHL
10.0
Time (CP to Q or Q )
n
n
5.0 ± 0.5
3.3 ± 0.3
5.1
6.3
6.7
9.7
7.3
1.0
1.0
1.0
1.0
8.8
C
C
C
C
= 15 pF
= 50 pF
= 15 pF
= 50 pF
L
L
L
L
ns
10.5
10.2
13.5
12.0
11.7
15.0
t
t
Propagation Delay Time
(PR or CLR to Q or Q )
PLH
PHL
ns
n
n
5.0 ± 0.5
4.6
6.4
4
6.7
9.5
10
1.0
1.0
8.0
11.0
10
C
C
= 15 pF
= 50 pF
L
ns
L
C
C
Input Capacitance
Power Dissipation
Capacitance
pF
V
= Open
IN
CC
18
pF (Note 3)
PD
Note 3: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained from the equation: I (opr.) = C * V * f + I /4 (per F/F), and the total C when n pcs of the Flip-Flop operate can
CC
PD
CC
IN
CC
PD
be calculated by the following equation: C (total) = 30 + 14 • n
PD
AC Operating Requirements
V
T
= 25°C
T = −40°C to +85°C
A
CC
A
Symbol
Parameter
Units
(Note 4)
(V)
Typ
Guaranteed Minimum
t
Minimum Pulse Width
(CP or CLR or PR)
Minimum Setup Time
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
5.0
5.0
5.0
5.0
4.0
1.0
1.0
6.0
5.0
W
ns
ns
ns
ns
5.0
5.0
4.0
1.0
1.0
6.0
5.0
t
S
(J or K to CP )
n
n
n
t
Minimum Hold Time
(J or K to CP )
H
n
n
n
t
Minimum Recovery Time
(CLR or PR to CP)
REC
Note 4: V is 3.3 ± 0.3V or 5.0 ± 0.5V
CC
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4
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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