74VCXH245DW [FAIRCHILD]
ALVC/VCX/A SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, SO-20;
| 型号： | 74VCXH245DW |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | ALVC/VCX/A SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, SO-20 |
| 文件： | 总9页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1999
Revised April 2005
74VCXH245
Low Voltage Bidirectional Transceiver with Bushold
General Description
Features
The VCXH245 contains eight non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bus ori-
ented applications. The T/R input determines the direction
of data flow. The OE input disables both the A and B Ports
by placing them in a high impedance state. The VCXH245
data inputs include active bushold circuitry, eliminating the
need for external pull-up resistors to hold unused or float-
ing data inputs at a valid logic level.
■ 1.2V to 3.6V VCC supply operation
■ Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
■ tPD
3.5 ns max for 3.0V to 3.6V VCC
■ Static Drive (IOH/IOL
)
24 mA @ 3.0V VCC
The 74VCXH245 is designed for low voltage (1.2V to 3.6V)
■ Uses patented Quiet Series noise/EMI reduction
VCC applications.
circuitry
The 74VCXH245 is fabricated with an advanced CMOS
technology to achieve high-speed operation while main-
taining low CMOS power dissipation.
■ Latchup performance exceeds 300 mA
■ ESD performance:
Human body model 2000V
Machine model 200V
Ordering Code:
Order Number Package Number
Package Description
74VCXH245WM
74VCXH245MTC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MTC20
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
Description
Output Enable Input (Active LOW)
Transmit/Receive Input
T/R
A0–A7
B0–B7
Side A Bushold Inputs or 3-STATE Outputs
Side B Bushold Inputs or 3-STATE Outputs
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500198
www.fairchildsemi.com
Connection Diagram
Truth Table
Inputs
Outputs
OE
L
T/R
L
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
HIGH Z State on A0–A7, B0–B7
L
H
H
X
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC
)
0.5V to 4.6V
0.5V to 4.6V
DC Input Voltage (VI)
Power Supply
DC Output Voltage (VO)
Outputs 3-STATE
Operating
1.2V to 3.6V
0.3V to 3.6V
0.5V to 4.6V
0.5V to VCC 0.5V
50 mA
Input Voltage
Outputs Active (Note 2)
DC Input Diode Current (IIK) VI 0V
Output Voltage (VO)
Output in Active States
Output in 3-STATE
0V to VCC
0V to 3.6V
DC Output Diode Current (IOK
VO 0V
)
50 mA
50 mA
Output Current in IOH/IOL
VCC 3.0V to 3.6V
VCC 2.3V to 2.7V
VCC 1.65V to 2.3V
VCC 1.4V to 1.65V
VCC 1.2V
VO VCC
24 mA
18 mA
6 mA
DC Output Source/Sink Current
(IOH/IOL
)
50 mA
100 mA
DC VCC or Ground Current
Storage Temperature (TSTG
2 mA
)
65 C to 150 C
100
A
Free Air Operating Temperature (TA)
Minimum Input Edge Rate ( t/ V)
VIN 0.8V to 2.0V, VCC 3.0V
40 C to 85 C
10 ns/V
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 2: I Absolute Maximum Rating must be observed.
O
Note 3: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
V
CC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
V
V
V
HIGH Level Input Voltage
2.7 - 3.6
2.3 - 2.7
2.0
1.6
IH
1.65 - 2.3 0.65 x V
V
CC
CC
CC
1.4 - 1.6
1.2
0.65 x V
0.65 x V
LOW Level Input Voltage
HIGH Level Output Voltage
2.7 - 3.6
2.3 - 2.7
1.65 - 2.3
1.4 - 1.6
1.2
0.8
0.7
IL
0.35 x V
0.35 x V
0.05 x V
V
CC
CC
CC
I
I
I
I
I
I
I
I
I
I
I
I
I
100
A
2.7 - 3.6
2.7
V
- 0.2
CC
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
12 mA
18 mA
24 mA
2.2
3.0
2.4
2.2
3.0
100
A
2.3 - 2.7
2.3
V
- 0.2
CC
6 mA
12 mA
18 mA
2.0
1.8
1.7
2.3
V
2.3
100
A
1.65 - 2.3
1.65
V
V
V
- 0.2
CC
6 mA
100
1.25
- 0.2
A
1.4 - 1.6
1.4
CC
2 mA
100
1.05
- 0.2
A
1.2
CC
3
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DC Electrical Characteristics (Continued)
V
CC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
2.7 - 3.6
2.7
V
LOW Level Output Voltage
I
100
A
0.2
0.4
OL
OL
I
12 mA
18 mA
24 mA
OL
I
3.0
0.4
OL
I
3.0
0.55
0.2
OL
I
100
A
2.3 - 2.7
2.3
OL
I
12 mA
18 mA
0.4
OL
V
I
2.3
0.6
OL
I
100
A
1.65 - 2.3
1.65
1.4 - 1.6
1.4
0.2
OL
I
6 mA
100
0.3
OL
I
A
A
0.2
OL
I
2 mA
100
0.35
0.05
5.0
OL
I
1.2
OL
I
Input Leakage Current
Bushold Input Minimum
Drive Hold Current
V
V
V
V
V
V
V
V or GND
CC
1.2 - 3.6
3.0
A
A
I
IN
IN
IN
IN
IN
IN
IN
I
0.8V
2.0V
0.7V
1.6V
75.0
75.0
45.0
45.0
25.0
25.0
450
450
300
300
200
200
I(HOLD)
3.0
2.3
2.3
0.57V
1.07V
1.65
1.65
3.6
I
Bushold Input Over-Drive
Current to Change State
(Note 4)
(Note 5)
(Note 4)
(Note 5)
(Note 4)
(Note 5)
I(OD)
3.6
2.7
A
A
2.7
1.95
1.95
I
3-STATE Output Leakage
Quiescent Supply Current
V
V
V
V
V
or GND
CC
OZ
O
I
1.2 - 3.6
10.0
V
or V
IL
IH
I
V
or GND
1.2 - 3.6
2.7 - 3.6
20.0
750
A
A
CC
I
CC
I
Increase in I per Input
V
CC
0.6V
CC
CC
IH
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
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4
AC Electrical Characteristics (Note 6)
V
T
40 C to 85 C
Figure
CC
A
Symbol
Parameter
Conditions
Units
(V)
Min
Max
3.5
Number
t
t
,
Propagation Delay
to B or B to A
n
C
30 pF, R
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
1.2
0.6
0.8
1.5
1.0
PHL
PLH
L
L
Figures
1, 2
A
4.2
n
n
n
8.4
ns
C
C
15 pF, R
30 pF, R
2k
16.8
42.0
4.5
L
L
Figures
5, 6
t
t
,
Output Enable Time
Output Disable Time
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
1.2
0.6
0.8
1.5
1.0
PZL
L
L
Figures
1, 3, 4
5.6
PZH
9.8
ns
ns
ns
C
C
15 pF, R
30 pF, R
2k
19.6
49.0
3.6
L
L
Figures
5, 7, 8
t
t
,
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
1.2
0.6
0.8
1.5
1.0
PLZ
L
L
Figures
1, 3, 4
4.0
PHZ
7.2
C
C
15 pF, R
30 pF, R
2k
14.4
36.0
0.5
L
L
Figures
5, 7, 8
t
t
Output to Output Skew
(Note 7)
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
1.2
OSHL
OSLH
L
L
0.5
0.75
1.5
C
15 pF, R
2k
L
L
1.5
Note 6: For C
50 pF, add approximately 300 ps to the AC maximum specification.
L
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
) or LOW-to-HIGH (t
).
OSLH
OSHL
Dynamic Switching Characteristics
V
T
25 C
CC
A
Symbol
Parameter
Conditions
Units
(V)
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
Typical
0.3
V
V
V
Quiet Output Dynamic Peak V
C
C
C
30 pF, V
30 pF, V
30 pF, V
V
V
V
, V
, V
, V
0V
0V
0V
OLP
OL
L
L
L
IH
IH
IH
CC
CC
CC
IL
0.7
V
1.0
Quiet Output Dynamic Valley V
Quiet Output Dynamic Valley V
0.3
OLV
OL
IL
0.7
V
V
1.0
1.3
OHV
OH
IL
1.7
2.0
Capacitance
T
25 C
A
Symbol
Parameter
Conditions
Units
Typical
C
Input Capacitance
Input/Output Capacitance
Power Dissipation Capacitance
V
V
V
0V or V , V
1.8V, 2.5V or 3.3V
1.8V, 2.5V or 3.3V
6
7
pF
pF
pF
IN
I
I
I
CC
CC
C
C
0V or V , V
CC
I/O
PD
CC
0V or V , f 10 MHz, V
CC
1.8V, 2.5V or 3.3V
20
CC
5
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AC Loading and Waveforms (V 3.3V r 0.3V to 1.8V r 0.5V)
CC
FIGURE 1. AC Test Circuit
TEST
SWITCH
t
PLH, tPHL
Open
6V at VCC 3.3 0.3V;
VCC x 2 at VCC 2.5V 0.2V; 1.8V 0.15V
GND
t
PZL, tPLZ
tPZH, tPHZ
FIGURE 2. Waveform for Inverting and Non-inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
3.3V 0.3V
1.5V
2.5V 0.2V
VCC/2
1.8V 0.15V
VCC/2
Vmi
Vmo
Vx
1.5V
VCC/2
VCC/2
VOL 0.3V
VOH 0.3V
VOL 0.15V
VOH 0.15V
VOL 0.15V
VOH 0.15V
Vy
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6
AC Loading and Waveforms (V 1.5V r 0.1V to 1.2V)
CC
FIGURE 5. AC Test Circuit
TEST
SWITCH
tPLH, tPHL
Open
VCC x 2 at VCC 1.5 0.1V
GND
tPZL, tPLZ
tPZH, tPHZ
FIGURE 6. Waveform for Inverting and Non-Inverting Functions
FIGURE 7. 3-STATE Output High Enable and Disable Times for Low voltage Logic
FIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
1.5V 0.1V
Vmi
Vmo
VX
VCC/2
VCC/2
VOL 0.1V
VOH 0.1V
VY
7
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit, JEDEC MS-013, 0.300” Wide Body
Package Number M20B
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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