74VCXH16374GX [FAIRCHILD]
Low Voltage 16-Bit D-Type Flip-Flop with Bushold; 低电压16位D型触发器与Bushold
| 型号： | 74VCXH16374GX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit D-Type Flip-Flop with Bushold |
| 文件： | 总11页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2000
Revised June 2005
74VCXH16374
Low Voltage 16-Bit D-Type Flip-Flops with Bushold
General Description
The VCXH16374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
Features
■ 1.4V to 3.6V VCC supply operation
ented applications. The device is byte controlled. A buff-
ered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
■ 3.6V tolerant control inputs and outputs
■ Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
The VCXH16374 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
■ tPD
3.0 ns max for 3.0V to 3.6V VCC
The 74VCXH16374 is designed for low voltage (1.4V to
3.6V) VCC applications with output compatibility up to 3.6V.
■ Static Drive (IOH/IOL
)
24 mA @ 3.0V VCC
The 74VCXH16374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 300 mA
■ ESD performance:
Human body model 2000V
Machine model 200V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number
Package Number
Package Descriptions
74VCXH16374GX
(Note 1)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74VCXH16374MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: BGA package available in Tape and Reel only.
Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
DS500228
www.fairchildsemi.com
Connection Diagrams
Pin Descriptions
Pin Assignment for TSSOP
Pin Names
Description
OEn
CPn
Output Enable Input (Active LOW)
Clock Pulse Input
Bushold Inputs
I0–I15
O0–O15
NC
Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
O0
O2
NC
O1
OE1
NC
CP1
NC
NC
I1
I0
I2
O4
O3
VCC
VCC
I3
I4
O6
O5
GND GND
GND GND
GND GND
I5
I6
O8
O7
I7
I8
O10
O12
O14
O9
I9
I10
I12
I14
G
H
O11
O13
VCC
NC
VCC
NC
I11
I13
J
O15
NC
OE2
CP2
NC
I15
Truth Tables
Inputs
Outputs
O0–O7
CP1
OE1
I0–I7
Pin Assignment for FBGA
L
L
H
L
H
L
L
L
X
X
O0
Z
X
H
Inputs
OE2
Outputs
O8–O15
CP2
I8–I15
L
L
H
L
H
L
L
L
X
X
O0
Z
(Top Thru View)
X
H
H
L
HIGH Voltage Level
LOW Voltage Level
X
Z
O
Immaterial (HIGH or LOW, control inputs may not float)
High Impedance
Previous O before HIGH-to-LOW of CP
0
0
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2
Functional Description
The 74VCXH16374 consists of sixteen edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte func-
tioning identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each clock has a buffered clock and buffered Output
Enable common to all flip-flops within that byte. The
description which follows applies to each byte. Each
flip-flop will store the state of their individual I inputs that
meet the setup and hold time requirements on the
LOW-to-HIGH Clock (CPn) transition. With the Output
Enable (OEn) LOW, the contents of the flip-flops are avail-
able at the outputs. When OEn is HIGH, the outputs go to
the high impedance state. Operations of the OEn input
does not affect the state of the flip-flops.
Logic Diagram
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 3)
Recommended Operating
Conditions (Note 5)
Supply Voltage (VCC
)
0.5V to 4.6V
DC Input Voltage (VI)
OEn, CPn
Power Supply
0.5V to 4.6V
Operating
1.4V to 3.6V
0.3V to VCC
I0 – I15
0.5V to VCC 0.5V
Input Voltage
Output Voltage (VO)
Outputs 3-STATED
Outputs Active (Note 4)
DC Input Diode Current (IIK
VI 0V
Output Voltage (VO)
Output in Active States
Output in “OFF” State
Output Current in IOH/IOL
VCC 3.0V to 3.6V
0.5V to 4.6V
0V to VCC
0.5V to VCC 0.5V
0.0V to 3.6V
)
50 mA
24 mA
18 mA
DC Output Diode Current (IOK
VO 0V
)
VCC 2.3V to 2.7V
50 mA
50 mA
VCC 1.65V to 2.3V
VCC 1.4V to 1.6V
6 mA
VO VCC
2 mA
DC Output Source/Sink Current
(IOH/IOL
Free Air Operating Temperature (TA)
Minimum Input Edge Rate ( t/ V)
VIN 0.8V to 2.0V, VCC 3.0V
40 C to 85 C
)
50 mA
DC VCC or GND Current per
Supply Pin (ICC or GND)
10 ns/V
Note 3: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
100 mA
Storage Temperature Range (TSTG
)
65 C to 150 C
Note 4: I Absolute Maximum Rating must be observed.
O
Note 5: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
V
CC
Symbol
Parameter
HIGH Level Input Voltage
Conditions
Min
Max
Units
(V)
V
V
V
2.7 - 3.6
2.3 - 2.7
2.0
1.6
IH
V
1.65 - 2.3 0.65 x V
CC
1.4 - 1.6
2.7 - 3.6
2.3 - 2.7
1.65 - 2.3
1.4 - 1.6
2.7 - 3.6
2.7
0.65 x V
CC
LOW Level Input Voltage
HIGH Level Output Voltage
0.8
0.7
IL
V
1.35 x V
1.35 x V
CC
CC
I
I
I
I
I
I
I
I
I
I
I
I
100
A
V - 0.2
CC
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
12 mA
2.2
18 mA
24 mA
3.0
2.4
2.2
3.0
100
A
2.3 - 2.7
2.3
V - 0.2
CC
6 mA
12 mA
18 mA
2.0
1.8
1.7
V
2.3
2.3
100
A
1.65 - 2.3
1.65
V - 0.2
CC
6 mA
100
1.25
- 0.2
A
1.4 - 1.6
1.4
V
CC
2 mA
1.05
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4
DC Electrical Characteristics (Continued)
V
CC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
2.7 - 3.6
2.7
V
LOW Level Output Voltage
I
I
I
I
I
I
I
I
I
I
I
100
A
0.2
0.4
0.4
0.55
0.2
0.4
0.6
0.2
0.3
0.2
0.35
5.0
5.0
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
12 mA
18 mA
24 mA
3.0
3.0
100
A
2.3 - 2.7
2.3
12 mA
18 mA
V
2.3
100
A
1.65 - 2.3
1.65
1.4 - 1.6
1.4
6 mA
100
A
2 mA
I
I
Input Leakage Current
Control Pins
Data Pins
0
V
3.6V
V or GND
CC
2.7 - 3.6
2.7 - 3.6
3.0
I
I
A
A
V
I
Bushold Input Minimum
Drive Hold Current
V
V
V
V
V
V
0.8V
2.0V
0.7V
1.6V
0.57V
1.07V
75.0
75.0
45.0
45.0
25.0
25.0
450
450
300
300
200
200
I(HOLD)
I(OD)
OZ
IN
IN
IN
IN
IN
IN
3.0
2.3
2.3
1.65
1.65
3.6
I
I
Bushold Input Over-Drive
Current to Change State
(Note 6)
(Note 7)
(Note 6)
(Note 7)
(Note 6)
(Note 7)
3.6
2.7
A
A
2.7
1.95
1.95
3-STATE Output Leakage
0
V
3.6V
or V
O
1.4 - 3.6
10.0
V
V
IH
I
IL
I
I
Power-OFF Leakage Current
Quiescent Supply Current
0
(V
V
)
3.6V
0
10.0
20.0
20.0
750
A
A
A
A
OFF
CC
O
V
V
V
or GND
1.4 - 3.6
1.4 - 3.6
2.7 - 3.6
I
CC
(V
)
3.6V (Note 8)
0.6V
CC
IH
O
I
Increase in I per Input
V
CC
CC
CC
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: Outputs disabled or 3-STATE only.
5
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AC Electrical Characteristics (Note 9)
V
T
40 C to 85 C
Max
Units
Figure
CC
A
Symbol
Parameter
Conditions
(V)
Min
Number
f
Maximum Clock Frequency
C
30 pF
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
250
200
100
80.0
0.8
MAX
L
MHz
C
C
15 pF
L
t
t
Propagation Delay
Output Enable Time
Output Disable Time
pF, R
500
3.0
3.9
PHL
PLH
L
L
Figures
1, 2
1.0
ns
ns
ns
1.5
7.8
C
C
15 pF, R
30 pF, R
2 k
1.0
15.6
Figures
7, 8
L
L
t
t
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
0.8
1.0
1.5
1.0
3.5
4.6
PZL
PZH
L
L
Figures
1, 3, 4
9.2
C
C
15 pF, R
30 pF, R
2 k
18.4
Figures
7, 9, 10
L
L
t
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
0.8
1.0
1.5
1.0
3.5
3.8
PLZ
L
L
Figures
1, 3, 4
6.8
C
C
15 pF, R
30 pF, R
2 k
13.6
Figures
7, 9, 10
L
L
t
t
t
Setup Time
Hold Time
Pulse Width
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
1.5
1.5
2.5
3.0
1.0
1.0
1.0
2.0
1.5
1.5
4.0
4.0
S
L
L
ns
ns
ns
ns
Figure 6
Figure 6
Figure 5
C
C
15 pF, R
30 pF, R
500
500
L
L
H
W
L
L
C
C
15 pF, R
30 pF, R
500
500
L
L
L
L
C
C
15 pF, R
30 pF, R
500
500
L
L
t
t
Output to Output Skew
(Note 10)
0.5
0.5
OSHL
OSLH
L
L
0.75
1.5
C
15 pF, R
2 k
L
L
Note 9: For C
50 F, add approximately 300 ps to the AC maximum specification.
P
L
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t ) or LOW-to-HIGH (t ).
OSHL
OSLH
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6
Dynamic Switching Characteristics
V
T
25 C
Typical
CC
A
Symbol
Parameter
Conditions
Units
(V)
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
V
V
V
Quiet Output Dynamic Peak V
C
C
C
30 pF, V
30 pF, V
30 pF, V
V
V
V
, V
, V
, V
0V
0V
0V
0.25
0.6
0.8
0.25
0.6
OLP
OL
L
L
L
IH
IH
IH
CC
CC
CC
IL
IL
IL
V
Quiet Output Dynamic Valley V
Quiet Output Dynamic Valley V
OLV
OL
V
V
0.8
1.5
1.9
2.2
OHV
OH
Capacitance
T
25 C
A
Symbol
Parameter
Conditions
Units
Typical
6.0
C
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
V
V
1.8V, 2.5V or 3.3V, V 0V or V
CC
pF
pF
IN
CC
I
C
0V or V , V
CC
1.8V, 2.5V or 3.3V
7.0
OUT
PD
I
CC
C
V
V
0V or V , f 10 MHz,
CC
I
20.0
pF
1.8V, 2.5V or 3.3V
CC
7
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AC Loading and Waveforms (V 3.3V r 0.3V to 1.8V r 0.15V)
CC
TEST
SWITCH
t
PLH, tPHL
Open
t
PZL, tPLZ
6V at VCC 3.3V 0.3V;
VCC x 2 at VCC 2.5V 0.2V; 1.8V 0.15V
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
tREC Waveforms
VCC
Symbol
3.3V 0.3V
1.5V
2.5V 0.2V
VCC/2
1.8V 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
VCC/2
VCC/2
VOL 0.3V
VOH 0.3V
VOL 0.15V
VOH 0.15V
VOL 0.15V
VOH 0.15V
VY
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8
AC Loading and Waveforms (V 1.5V r 0.1V)
CC
TEST
SWITCH
t
PLH, tPHL
Open
VCC x 2 at VCC 1.5 0.1V
GND
tPZL, tPLZ
tPZH, tPHZ
FIGURE 7. AC Test Circuit
FIGURE 8. Waveform for Inverting and Non-Inverting Functions
FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 10. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
1.5V 0.1V
Vmi
Vmo
VX
VCC/2
VCC/2
VOL 0.1V
VOH 0.1V
VY
9
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Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
(Preliminary)
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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11
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