74OL6000.3S [FAIRCHILD]
Logic IC Output Optocoupler, 1-Element, 5300V Isolation, 10MBps, SURFACE MOUNT, PLASTIC, DIP-6;
| 型号： | 74OL6000.3S |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Logic IC Output Optocoupler, 1-Element, 5300V Isolation, 10MBps, SURFACE MOUNT, PLASTIC, DIP-6 输出元件 光电 |
| 文件： | 总15页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
OPTOPLANAR HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
TTL BUFFER
74OL6000
74OL6001
74OL6010
74OL6011
TTL INVERTER
CMOS BUFFER
CMOS INVERTER
LSTTL TO
PACKAGE
SYMBOL
BUFFER
6
6
6
1
1
INVERTER
1
DESCRIPTION
OPTOLOGIC™ is the first family of truly logic compatible optically coupled logic interface gates.
The family consists of four device types offering LSTTL to TTL and LSTTL to CMOS interfacing. Each of these interfacing functions
is available as a buffer (A=B), or as an inverter (A=B).
The LSTTL input compatibility is provided by an input integrated circuit, with industry standard logic levels. This input amplifier IC
switches a temperature compensated current source driving a high speed 850 nm AlGaAs LED emitter. This novel integration
scheme eliminates CTR degradation over time and temperature.
The emitter is optically coupled to an integrated photodetector/high-gain, high-speed output amplifier IC. The superior 15kV/µS
common-mode noise rejection is ensured through the use of an optically transparent noise shield.
The TTL compatible output has a totem-pole with a fan-out of 10. The CMOS compatible output has an open collector Schottky-
clamped transistor that interfaces to any CMOS logic between 4.5 and 15 volts.The 74OL6010/11 may also by used to drive power
MOSFETS or transistors up to 15 volts.
The Optologic coupler family typically offers propagation of delays of 60 ns and can support 15 MBaud data communication.
The two input chips and the output chip are assembled in a 6-pin DIP high insulation voltage plastic package. Fairchild’s proprietary
®
OPTOPLANAR construction provides a withstand test voltage of 5300 VRMS (1 minute).
FEATURES
APPLICATIONS
•
Industry first LSTTL to TTL and LSTTL to CMOS complete
logic-to-logic optocoupler
Incorporates LED drive circuitry — use as logic gate
Very high speed
•
•
•
•
•
•
•
•
Transmission line interface — receiver and driver
Excellent as bridged receiver in fast LAN highways
Bus interface
Logic family interface with ground loop noise elimination
High speed ACꢁDC voltage sensing
Driver for power semiconductor devices
Level shifting
•
•
•
•
•
•
•
•
Choice of buffer or inverter
Choice of TTL or CMOS compatible output up to 15 volts
Fan-out of 10 TTL loads, fan-in 1 LSTTL load
Internal noise shield — very high CMR of 15 ꢀVꢁ/S
UL recognized (File #E90700)
Replaces fast pulse transformers
Same noise immunity as LSTTLꢁTTL.
© 2003 Fairchild Semiconductor Corporation
Page 1 of 15
10/1/03
®
OPTOPLANAR HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
TTL BUFFER
74OL6000
74OL6001
74OL6010
74OL6011
TTL INVERTER
CMOS BUFFER
CMOS INVERTER
LSTTL TO
Vcc
Vcc
150 Ω TYP.
Vcc
RL
22 ꢀΩ TYP.
INPUT
OUTPUT
GND
LSTTL INPUT CIRCUIT
OUTPUT
GND
CMOS OUTPUT CIRCUIT
GND
TTL OUTPUT CIRCUIT
All Inputs
74OL6000ꢁ01 Output
74OL6010ꢁ11 Output
PIN CONFIGURATION
1-V
(Input V
)
6-V
(Output V
)
CCI
CC
CCO
CC
2-V (Data In)
5-V (Data Out)
O
IN
3-GND, (Input GND) 4-GND (Output GND)
O
DEVICE CONFIGURATION
Logic Compatibility
Part Number
Logic Function
Output Configuration
Input
Output
74OL 6000
74OL 6001
74OL 6010
74OL 6011
LSTTL
LSTTL
LSTTL
LSTTL
TTL
TTL
BUFFER
INVERTER
BUFFER
TOTEM POLE
TOTEM POLE
CMOS
CMOS
OPEN COLLECTOR
OPEN COLLECTOR
INVERTER
© 2003 Fairchild Semiconductor Corporation
Page 2 of 15
10ꢁ1ꢁ03
®
OPTOPLANAR HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
TTL BUFFER
74OL6000
74OL6001
74OL6010
74OL6011
TTL INVERTER
CMOS BUFFER
CMOS INVERTER
LSTTL TO
SCHEMATIC
74OOLL6000
74OOLL6001
74OOLL6010
74OOLL6011
NOISE
NOISE
NOISE
NOISE
SHIELD
SHIELD
SHIELD
SHIELD
1
2
3
1
2
3
1
2
3
1
2
3
6
5
4
6
5
4
6
5
4
6
5
4
LSTLL to TTL Buffer
LSTLL to TTL Inverter
LSTLL to CMOS Buffer
LSTLL to CMOS Inverter
© 2003 Fairchild Semiconductor Corporation
Page 3 of 15
10ꢁ1ꢁ03
®
OPTOPLANAR HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
TTL BUFFER
74OL6000
74OL6001
74OL6010
74OL6011
TTL INVERTER
CMOS BUFFER
CMOS INVERTER
LSTTL TO
ELECTRICAL CHARACTERISTICS (T = 0°C to 70°C Unless otherwise specified)
A
Test Conditions
Parameter
Symbol Min Typ* Max Units
Notes
74OL6000 74OL6001
74OL6000/01
TTL OUTPUT 74OL6000/01
Input Supply Voltage
V
4.5 5.0
4.5 5.0
2.0
5.5
5.5
V
V
1
1
1
1
CCI
Output Supply Voltage
High-Level Input Voltage
Low-Level Input Voltage
Input Clamp Voltage
V
CCO
V
V
IH
V
0.8
-1.2
40.0
V
IL
V
V
V
V
= 4.5 V, I = -18 mA
1
1
1
1
1
IK
CCI
I
High-Level Input Current
Low-Level Input Current
Input Supply Current (high)
Input Supply Current (low)
I
1.0
/A
= 5.5 V, V = 4.5 V
IH
IH
CCI
I
-200.0 -400.0 /A
10.0 14.0 mA
10.0 14.0 mA
V
= 5.5 V, V = 0.4 V
IL
CCI IL
I
V
= 5.5 V, V = V
CCIH
CCI IN IH
I
V
= 5.5 V, V = V
CCIL
CCI IN IL
V
V
V
V
V
V
= 4.5 V, V
= 4.5 V,
CCI
CCI
CCI
CCI
CCI
CCI
CCO
High-Level Output Voltage
Low-Level Output Voltage
High-Level Output Current
V
2.4 3.0
V
V
= 2.0 V
= 0.8V
V
IN
= 0.8 V
= 2.0V
1
1
1
OH
IN
I
= -400 mA
OH
= 4.5 V, V
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
CCO
0.6
0.5
I
= 16 mA
OL
V
0.3
V
V
V
OL
IN
IN
= 4.5 V, V
CCO
I
= 4 mA
OL
= 4.5 V, V
CCO
I
-8.0 -10.0 mA
mA
V
= V
V
= V
IL
OH
IN
IH
IN
V
= 2.4 V
OH
= 4.5 V, V
CCO
Low-Level Output Current
Short-Circuit Output Current
Output Supply Current (high)
I
16.0
V
= 0.8 V
V
= 2.0V
1
1
1
OL
IN
IN
V
= 0.6 V
OL
I
-5.0 -25.0 -40.0 mA
V
= V
= V
V
= V
= V
= 5.5 V, V
CCO
OS
IN
IN
IH
IH
IN
IN
IL
IL
V
= 5.5 V, V = V
,
CCI
O
OH
I
9.0
8.0
15.0 mA
12.0 mA
V
V
CCOH
V
= 5.5 V
CCO
V
= 5.5 V, V = V
,
CCI
O
OL
Output Supply Current (low)
I
V
= V
V
= V
1
CCOL
IN
IL
IN
IH
V
= 5.5 V
CCO
*All typical values are at T =25°C
A
SWITCHING CHARACTERISTCS (T = 25°C Unless otherwise specified)
A
Parameter
Symbol Min Typ Max Units
Test Conditions
Fig. Notes
TTL OUTPUT 74OL6000/01
Propagation Delay Time For Output Low Level
Propagation Delay Time For Output High Level
Output Rise Time For Output High Level
Output Fall Time For Output Low Level
t
60
70
45
5
100
100
ns
ns
n
15, 17
1
1
1
1
PHL
t
V
= 5 V, V
CCO
= 5 V 15, 17
15, 17
PLH
CCI
t
r
t
ns
15, 17
f
© 2003 Fairchild Semiconductor Corporation
Page 4 of 15
10ꢁ1ꢁ03
®
OPTOPLANAR HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
TTL BUFFER
74OL6000
74OL6001
74OL6010
74OL6011
TTL INVERTER
CMOS BUFFER
CMOS INVERTER
LSTTL TO
ELECTRICAL CHARACTERISTICS (T = 0°C to 70°C Unless otherwise specified)
A
Test Conditions
Parameter
Symbol Min Typ* Max Units
Notes
74OL6010 74OL6011
74OL6010/11
CMOS OUTPUT 74OL6010/11
Input Supply Voltage
V
4.5
4.5
2.0
5.0
5.5
V
V
1
1,3
1
CCI
Output Supply Voltage
High-Level Input Voltage
Low-Level Input Voltage
Input Clamp Voltage
V
15.0
CCO
V
V
IH
V
0.8
-1.2
40.0
V
1
IL
V
V
V
V
= 4.5 V, I = -18 mA
1
1
1
1
1
IK
CCI
CCI
CCI
I
High-Level Input Current
Low-Level Input Current
Input Supply Current (high)
Input Supply Current (low)
I
1.0
/A
= 5.5 V, V = 4.5 V
IH
IH
I
-200.0 -400.0 /A
10.0 14.0 mA
10.0 14.0 mA
V
= 5.5 V, V = -0.4 V
IL
IL
I
V
= 5.5 V, V = V
CCIH
CCI IN IH
I
V
= 5.5 V, V = V
CCIL
CCI IN IL
V
V
= 4.5 V, V
= 4.5 V,
CCI
CCO
0.6
I
= 16 mA
OL
Low-Level Output Voltage
V
0.4
V
V
= 0.8V V = 2.0V
1
OL
IN
IN
= 4.5 V, V
= 4.5 V,
CCI
CCO
0.5
I
= 4 mA
OL
V
= 4.5 V, V = 15 V,
OH
CCI
V
High-Level Output Current
Low-Level Output Current
I
1.0 100.0 /A
mA
V
= V
V
= V
IL
1
1
OH
IN
IH
IN
= 4.5 - 15 V
CCO
V
= 4.5 V, V = 0.6V,
OL
CCI
V
I
16.0
V
= 0.8 V V = 2.0V
IN
OL
IN
= 4.5 - 15 V
CCO
V
= 5.5 V, V = V
,
CCI
O
OH
9.0
11.0 18.0
8.0 12.0
11.0 18.0
12.0
V
= 4.5 V
CCO
Output Supply Current (high)
Output Supply Current (low)
I
mA
mA
V
= V
V
= V
1
1
CCOH
IN
IH
IN
IL
V
= 5.5 V, V = V
,
,
,
CCI
CCI
CCI
O
OL
OL
OL
V
= 15 V
CCO
V
= 5.5 V, V = V
O
V
= 4.5 V
CCO
I
V
= V
V
= V
CCOL
IN
IL
IN
IH
V
= 5.5 V, V = V
O
V
= 15 V
CCO
*All typical values are at T =25°C
A
SWITCHING CHARACTERISTCS (T = 25°C Unless otherwise specified)
A
Parameter
Symbol Min Typ Max Units
Test Conditions
Fig.
Notes
TTL OUTPUT 74OL6010/11
Propagation Delay Time For Output Low Level
Propagation Delay Time For Output High Level
Output Rise Time For Output High Level
Output Fail Time For Output Low Level
t
60 120
ns
ns
ns
ns
15, 18
15, 18
15, 18
15, 18
1
1
1
1
PHL
V
= 5 V,
CCI
t
100 180
PLH
V
= 5 V, R = 470 Ω
CCO
L
t
50
5
r
t
f
© 2003 Fairchild Semiconductor Corporation
Page 5 of 15
10ꢁ1ꢁ03
®
OPTOPLANAR HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
TTL BUFFER
74OL6000
74OL6001
74OL6010
74OL6011
TTL INVERTER
CMOS BUFFER
CMOS INVERTER
LSTTL TO
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise specified)
A
Parameter
Symbol
Device
Value
Units
TOTAL DEVICE
Storage Temperature
Operating Temperature
Lead Solder Temperature
Power Dissipation
EMITTER
T
All
All
All
All
-55 to +125
0 to +70
°C
°C
STG
T
OPR
T
260 for 10 sec
350
°C
SOL
P
mW
D
Input Supply Voltage
Input Voltage
V
All
All
7
7
V
V
CCI
V
IN
DETECTOR
Average Output Current
I
All
40
7
mA
V
O (avg)
74OL6000ꢁ01
74OL6010ꢁ11
74OL6000ꢁ01
74OL6010ꢁ11
Output Supply Voltage
Output Voltage
V
CCO
18
7
V
V
O
18
ELECTRICAL CHARACERISTICS (T = 0°C to 70°C Unless otherwise specified)
A
Parameter
Symbol Min
Typ
Max Units
Test Conditions
Fig. Notes
74OL6000/01/10/11
Common Mode Transient Immunity at
Logic High Level Output
CM
5000 15000
-5000 -15000
Vꢁ/S
Vꢁ/S
16, 19
16, 19
H
V
= 5 V, V
= 5 V,
CCI
CCO
V
= 50 Vp-p
Common Mode Transient Immunity at
Logic Low Level Output
CM
CM
L
Common Mode Coupling Capacitance
Capacitance (input-output)
C
0.005
0.7
pF
pF
CM
C
VI-O = 0, f = 1 MHz
T = 25°C,
2
2
2
I-O
A
Withstand Insulation Test Voltage
Insulation Resistance
V
5300
10
VRMS
ISO
t = 1 min, I ≤ 1mA
I-O
R
Ω
V
= 500 VDC
ISO
I-O
© 2003 Fairchild Semiconductor Corporation
Page 6 of 15
10ꢁ1ꢁ03
®
OPTOPLANAR HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
TTL BUFFER
74OL6000
74OL6001
74OL6010
74OL6011
TTL INVERTER
CMOS BUFFER
CMOS INVERTER
LSTTL TO
Figure 1. Input Current vs. Ambient Temperature
100
Figure 2. Input Supply Current vs. Ambient Temperature
15
14
13
IIH
0
12
ICCIH - 74OL6000-6010
ICCIL - 74OL6001-6011
11
VCCI = 5.5V
VIH = 4.5V
VIL = 0.4V
-100
-200
-300
10
9
IIL
8
ICCIH - 74OL6001-6011
ICCIL - 74OL6000-6010
7
6
VCCI = 5.5V
5
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
TA - AMBIENT TEMPERATURE (˚C)
TA - AMBIENT TEMPERATURE (˚C)
Figure 3. Output Supply Current vs. Ambient Temperature
Figure 4. Output Current vs. Ambient Temperature
60
15
50
IOL
12
40
VCCI = 4.5V
VCCO = 4.5V
30
ICCOH
9
VOL = 0.6V
VOH = 2.4V
ICCOL
ICCOH
ICCOL
20
10
0
6
ICCOH
ICCOL
74OL6010ꢁ6011
VCCI = 5.5V
VCCO = 15V
IOH
-10
-20
-30
3
0
(74OL6000ꢁ6001)
74OL6010ꢁ6011
VCCI = 5.5V
74OL6000ꢁ6001
VCCI = 5.5V
VCCO = 5.5V
VCCO = 5.5V
-40
-20
0
20
40
60
80 100
-40
-20
0
20
40
60
80
100
TA - AMBIENT TEMPERATURE (˚C)
TA - AMBIENT TEMPERATURE (˚C)
Figure 5. High-Level Output Voltage vs. Ambient Temperature
Figure 6. Low-Level Output Voltage vs. Ambient Temperature
0.5
5
VCCI = 4.5V
VCCO = 4.5V
IOH = -400µA
4
3
2
0.4
@ IOL
= 16mA
= 4mA
0.3
0.2
0.1
@ IOL
1
0
V
V
CCI
= 4.5V
CCO = 4.5V
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
TA - AMBIENT TEMPERATURE (˚C)
TA - AMBIENT TEMPERATURE (˚C)
© 2003 Fairchild Semiconductor Corporation
Page 7 of 15
10ꢁ1ꢁ03
®
OPTOPLANAR HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
TTL BUFFER
74OL6000
74OL6001
74OL6010
74OL6011
TTL INVERTER
CMOS BUFFER
CMOS INVERTER
LSTTL TO
Figure 7. 74OL6010ꢁ11 Leaꢀage Current vs. Ambient Temperature
Figure 8. 74OL6000ꢁ01 Switching Times vs. Ambient Temperature
5
VCCI = 5.0V
VCCO = 5.0V
P.W = 200ns
VCCIN = 4.5V
CCO = 15V
VOUT = 15V
4
3
2
1
V
PERIOD = 1µS
200
tPLH
tPHL
tr
100
50
10
5
tf
0
-40
1
-40
-20
0
20
40
60
80
100
-20
0
20
40
60
80 100
T
A - AMBIENT TEMPERATURE (˚C)
T
A - AMBIENT TEMPERATURE (˚C)
Figure 9. 74OL6010ꢁ11 Switching Times vs. Ambient Temperature
Figure 10. Common Mode Rejection vs. Common Mode Voltage
11
VCCO = 5V
VCCO = 15V
VCCI = 5V
RL = 470Ω
10
9
P.W = 200ns
PERIOD = 1µS
tPLH
tPLH
tr
tPHL
tr
200
100
50
8
VCCO = 5V
VCCO = 5V
VOH = 2V
VOL = 0.8V
7
6
5
RL = 470Ω (74OL6010ꢁ6011)
4
3
10
5
tf
tf
2
1
1
-40
-20
0
20
40
60
80 100
0
500
1000
15000
2000
2500
T
A - AMBIENT TEMPERATURE (˚C)
VCM - COMMON MODE TRANSIENT
Figure 11. Supply Current vs. Supply Voltage
Figure 12. Power Dissipation vs. Ambient Temperature
MAXIMUM ALLOWABLE POWER
12
DISSIPATION @ TA = 25˚C
ICCO
ICC
10
8
300
200
100
0
@TA = 55˚C
6
VCCO
RANGE FOR 74OL6000ꢁ6001
V
CCI = 5.5V
@T
@T
A
A
= 70˚C
= 85˚C
4
2
V
CCI = 4.5V
0
4
5
6
7
8
9
10 11 12 13 14 15
4
5
6
7
8
9
10 11 12 13 14 15
V
CCO - OUTPUT SUPPLY VOLTAGE (V)
V
CC - SUPPLY VOLTAGE (V)
© 2003 Fairchild Semiconductor Corporation
Page 8 of 15
10ꢁ1ꢁ03
®
OPTOPLANAR HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
TTL BUFFER
74OL6000
74OL6001
74OL6010
74OL6011
TTL INVERTER
CMOS BUFFER
CMOS INVERTER
LSTTL TO
Figure 13. Input Threshold Voltage vs. Ambient Temperature
Figure 14. Input Current vs. Input Voltage
1.6
100
1.5
0
1.4
1.3
1.2
-100
-200
1.1
VCCI = 5.0V
VCCO = 5.0V
1.0
0.0
VCCI = 4.5V
-300
0
1
2
3
4
5
6
-40
-20
0
20
40
60
80
100
TA - AMBIENT TEMPERATURE (°C)
VIN - INPUT VOLTAGE (V)
Figure 15. Switching Time Test Circuit
Figure 16. Common Mode Rejection Test Circuit
VCCO
+5 V
VCCI
+5 V
VCCO
+5 V
1
2
3
6
5
6
1
2
3
6
5
4
.1µF
1ꢀΩ
.1µF
.1µF
470Ω (74OL6010ꢁ11)
.1µF
470Ω (74OL6010ꢁ11)
HꢁL
LꢁH
PULSE
GEN
PW =200ns
PERIOD = 1
tr = 5ns
Zo = 50Ω
µS
VO
CL*
*CL = 15pF STRAY CAPACITANCE
INCLUDING PROBE
+
-
V
CM
© 2003 Fairchild Semiconductor Corporation
Page 9 of 15
10ꢁ1ꢁ03
®
OPTOPLANAR HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
TTL BUFFER
74OL6000
74OL6001
74OL6010
74OL6011
TTL INVERTER
CMOS BUFFER
CMOS INVERTER
LSTTL TO
Figure 18. Switching Parameters 74OL6010ꢁ11
Figure 17. 74OL6000ꢁ01 Switching Times vs. Ambient Temperature
INPUT, VI
3.2V
INPUT, VI 3.2V
1.3V
1.3V
tPHL
tPLH
tPHL
tPLH
90%
50%
10%
90%
1.3V
OUTPUT, VO
(74OL6000)
OUTPUT, VO
(74OL6010)
10%
tr
tf
tf
tr
tr
tf
tf
tr
90%
50%
90%
OUTPUT, VO
(74OL6011)
OUTPUT, VO
(74OL6001)
1.3V
10%
10%
tPHL
tPLH
tPHL
tPLH
Figure 20. Suggested PCB Lay-Out
Figure 19. Common Mode Rejection Waveforms
50V
INPUT
V
CC
BUS
INPUT
GND
BUS
OUTPUT
GND
BUS
OUTPUT
V
CC
BUS
dVCM
dt
VCM
tr
VCM
0V
=
VOH
CMH
1
2
6
5
VO = 2.0V (MIN.)
VO = 0.8V (MAX.)
DATA
IN
DATA
OUT
.1µF
.1µF
3
4
VOL
CML
NOTE
1. The VCCO and VCCI supply voltages to the device must each be bypassed by a 0.1/F capacitor or larger. This can be either a
ceramic or solid tantalum capacitor with good high frequency characteristics. Its purpose is to stabilize the operation of the high-
gain amplifiers. Failure to provide the bypass will impair the DC and switching properties. The total lead length between capaci-
tor and optocoupler should not exceed 1.5mm. See Fig. 20.
2. Device considered a two-terminal device. Pins 1, 2 and 3 shorted together, and Pins 4, 5 and 6 shorted together.
3. For example, assuming a V
of 5.0V, and an ambient temperature of 70°C, the maximum allowable V
is 12.1V.
CCI
CCO
© 2003 Fairchild Semiconductor Corporation
Page 10 of 15
10ꢁ1ꢁ03
®
OPTOPLANAR HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
TTL BUFFER
74OL6000
74OL6001
74OL6010
74OL6011
TTL INVERTER
CMOS BUFFER
CMOS INVERTER
LSTTL TO
Package Dimensions (Through Hole)
Package Dimensions (Surface Mount)
PIN 1
ID.
0.350 (8.89)
0.330 (8.38)
PIN 1
ID.
3
1
0.270 (6.86)
0.240 (6.10)
0.270 (6.86)
0.240 (6.10)
0.350 (8.89)
0.330 (8.38)
6
0.070 (1.78)
0.045 (1.14)
0.300 (7.62)
TYP
0.070 (1.78)
0.045 (1.14)
0.200 (5.08)
0.115 (2.92)
0.200 (5.08)
0.165 (4.18)
0.016 (0.41)
0.008 (0.20)
0.020 (0.51)
MIN
0.020 (0.51)
MIN
0.016 (0.40) MIN
0.154 (3.90)
0.100 (2.54)
0.022 (0.56)
0.016 (0.41)
0.100 (2.54)
TYP
0.315 (8.00)
MIN
0.016 (0.40)
0.008 (0.20)
0.405 (10.30)
MAX
0.300 (7.62)
TYP
0.022 (0.56)
0.016 (0.41)
0° to 15°
Lead Coplanarity : 0.004 (0.10) MAX
0.100 (2.54)
TYP
Package Dimensions (0.4” Lead Spacing)
Recommended Pad Layout for
Surface Mount Leadform
PIN 1
ID.
0.070 (1.78)
0.270 (6.86)
0.240 (6.10)
0.060 (1.52)
0.350 (8.89)
0.330 (8.38)
0.415 (10.54)
0.100 (2.54)
0.295 (7.49)
0.070 (1.78)
0.045 (1.14)
0.030 (0.76)
0.200 (5.08)
0.135 (3.43)
0.154 (3.90)
0.100 (2.54)
0.016 (0.40)
0.008 (0.20)
0.004 (0.10)
MIN
0° to 15°
0.022 (0.56)
0.016 (0.41)
0.400 (10.16)
TYP
0.100 (2.54) TYP
NOTE
All dimensions are in inches (millimeters)
© 2003 Fairchild Semiconductor Corporation
Page 11 of 15
10ꢁ1ꢁ03
®
OPTOPLANAR HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
TTL BUFFER
74OL6000
74OL6001
74OL6010
74OL6011
TTL INVERTER
CMOS BUFFER
CMOS INVERTER
LSTTL TO
ORDERING INFORMATION
Option
Order Entry Identifier
Description
S
.S
.SD
Surface Mount Lead Bend
Surface Mount; Tape and Reel
0.4" Lead Spacing
SD
W
.W
300
.300
.300W
.3S
VDE 0884
300W
3S
VDE 0884, 0.4" Lead Spacing
VDE 0884, Surface Mount
VDE 0884, Surface Mount, Tape and Reel
3SD
.3SD
MARKING INFORMATION
1
2
74OL6000
V XX YY K
6
5
3
4
Definitions
1
2
Fairchild logo
Device number
VDE marꢀ (Note: Only appears on parts ordered with VDE
option – See order entry table)
3
4
5
6
Two digit year code, e.g., ‘03’
Two digit worꢀ weeꢀ ranging from ‘01’ to ‘53’
Assembly pacꢀage code
© 2003 Fairchild Semiconductor Corporation
Page 12 of 15
10ꢁ1ꢁ03
®
OPTOPLANAR HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
TTL BUFFER
74OL6000
74OL6001
74OL6010
74OL6011
TTL INVERTER
CMOS BUFFER
CMOS INVERTER
LSTTL TO
Reflow Profile (Black Package, No Suffix)
300
250
215°C, 10–30 s
225 C peaꢀ
200
150
Time above 183°C, 60–150 sec
Ramp up = 3Cꢁsec
100
50
0
• Peaꢀ reflow temperature: 225°C (pacꢀage surface temperature)
• Time of temperature higher than 183°C for 60–150 seconds
• One time soldering reflow is recommended
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Time (Minute)
© 2003 Fairchild Semiconductor Corporation
Page 13 of 15
10ꢁ1ꢁ03
®
OPTOPLANAR HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
TTL BUFFER
74OL6000
74OL6001
74OL6010
74OL6011
TTL INVERTER
CMOS BUFFER
CMOS INVERTER
LSTTL TO
APPLICATION
Local area data communication systems can greately improve their noise immunity by including OPOTOLOGIC gates in the
design.
The Optologic input amplifier offers the feature of very high input impedance that permits their use as bridged line receivers. The
system show above illustrates an optically isolated transmitter and multidrop receiver system. The networꢀ uses a 74OL6000 and
buffer (Figure D) to isolate the transmitter and drive the 75Ω coax cable. This application uses a 1000 ft. aerial suspension 75Ω
CATV coax cable with data taps at 250 ft. intervals. The 74OL6001s function as bridged receivers, and as many as 30 receivers
could be placed along the line with minimal signal degradation. The communication cable is terminated with a single 75Ω load at
the far end of the line.
Signal quality "Eye Pattern" is shown in Figures A, B and C with a 10MBaud NRZ Psuedo-Random Sequence (PRS).Traces 1-3 in
Figure A describes the transmitter section. Traces 4-7 in Figure B show the output of the four Optologic bridged terminations.
Traces 8-11 in Figure C illustrate "Eye Pattern" as seen at the output of a 74LS04 logic gate. The data quality is well preserved in
that only a 30% Eye closure is seen at the receiver located 1000 ft. from the transmitter.
The data communication system is completely optically isolated from all of the terminal equipments. Power for the transmitter
(V
) and receiver (V ) is taꢀen from an isolated power supply and distributed through a drain or messenger wire.
CCO
CCI
Figure A
Figure B
Figure C
HORIZONTAL = 20 nsꢁDIV 42-11
VERTICAL = 2 VꢁDIV
HORIZONTAL = 20 nsꢁDIV 42-12, 02
VERTICAL = 2 VꢁDIV
HORIZONTAL = 20 nsꢁDIV 42-13ꢁ03
VERTICAL = 2 VꢁDIV
1000 FT.
3
1
2
75
Ω
0.1 µ
F
TERMINAION
10 Ω
250 FT.
250 FT.
250 FT.
250 FT.
BUFFER
74
6000
OL
2N4252
100 µ
F
74
6001
74
6001
OL
74
6001
OL
74
6001
OL
OL
4
8
5
9
6
7
1.1 KΩ
LS04
LS04
LS04
LS04
10
11
2N2222
ALL DIODES
1N6263
Figure D Buffer
© 2003 Fairchild Semiconductor Corporation
Page 14 of 15
10ꢁ1ꢁ03
®
OPTOPLANAR HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
TTL BUFFER
74OL6000
74OL6001
74OL6010
74OL6011
TTL INVERTER
CMOS BUFFER
CMOS INVERTER
LSTTL TO
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
© 2003 Fairchild Semiconductor Corporation
Page 15 of 15
10ꢁ1ꢁ03
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