74LVX374MX_NL [FAIRCHILD]
Bus Driver, LV/LV-A/LVX/H Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, MS-013, SOIC-20;
| 型号： | 74LVX374MX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, LV/LV-A/LVX/H Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, MS-013, SOIC-20 触发器 |
| 文件： | 总7页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1993
Revised April 2005
74LVX374
Low Voltage Octal D-Type Flip-Flop with
3-STATE Outputs
General Description
Features
■ Input voltage translation from 5V to 3V
The LVX374 is a high-speed, low-power octal D-type flip-
flop featuring separate D-type inputs for each flip-flop and
3-STATE outputs for bus-oriented applications. A buffered
Clock (CP) and Output Enable (OE) are common to all flip-
flops. The inputs tolerate up to 7V allowing interface of 5V
systems to 3V systems.
■ Ideal for low power/low noise 3.3V applications
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number Package Number
Package Description
74LVX374M
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVX374SJ
74LVX374MTC
MTC20
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
D0–D7
CP
Data Inputs
Clock Pulse Input
OE
3-STATE Output Enable Input
3-STATE Outputs
O0–O7
© 2005 Fairchild Semiconductor Corporation
DS011612
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Truth Table
Inputs
Outputs
Dn
H
L
CP
OE
L
On
H
L
L
X
X
H
Z
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
LOW-to-HIGH Transition
Functional Description
The LVX374 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
DC Input Diode Current (IIK
VI 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK
VO 0.5V
)
0.5V to 7.0V
)
Supply Voltage (VCC
)
2.0V to 3.6V
0V to 5.5V
20 mA
Input Voltage (VI)
0.5V to 7V
Output Voltage (VO)
0V to VCC
)
Operating Temperature (TA)
40 C to 85 C
0 ns/V to 100 ns/V
20 mA
20 mA
Input Rise and Fall Time ( t/ V)
VO VCC 0.5V
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
DC Output Voltage (VO)
DC Output Source
0.5V to VCC 0.5V
or Sink Current (IO)
25 mA
DC VCC or Ground Current
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
(ICC or IGND
)
75 mA
65 C to 150 C
180mW
Storage Temperature (TSTG
Power Dissipation
)
DC Electrical Characteristics
T
25 C
Typ
T
40 C to 85 C
A
A
V
Symbol
Parameter
Units
Conditions
CC
Min
1.5
2.0
2.4
Max
Min
Max
V
HIGH Level
2.0
3.0
3.6
2.0
3.0
3.6
2.0
3.0
3.0
2.0
3.0
3.0
3.6
1.5
2.0
2.4
IH
Input Voltage
V
V
V
V
LOW Level
0.5
0.8
0.8
0.5
0.8
0.8
IL
Input Voltage
V
V
V
HIGH Level
1.9
2.9
2.0
3.0
1.9
2.9
V
V
I
50
50
4mA
A
OH
OL
IN
IH
OH
OH
OH
OL
OL
OL
IL
Output Voltage
or V
I
A
IL
2.58
2.48
I
LOW Level
0.0
0.0
0.1
0.1
0.1
0.1
V
V
I
50
50
A
A
IN
IH
Output Voltage
or V
I
I
IL
0.36
0.25
0.44
2.5
4mA
I
3-STATE Output
V
V
or V
OZ
IN
IH
Off-State Current
A
A
A
V
V
V
V
or GND
CC
OUT
IN
I
I
Input Leakage Current
Quiescent Supply Current
3.6
3.6
0.1
4.0
1.0
5.5V or GND
V or GND
CC
IN
40.0
CC
IN
Noise Characteristics (Note 3)
V
T
25 C
CC
A
C
(pF)
Symbol
Parameter
Quiet Output Maximum Dynamic V
Units
L
(V)
3.3
3.3
3.3
3.3
Typ
Limit
V
V
V
V
0.5
0.5
0.8
0.8
2.0
0.8
V
V
V
V
50
OLP
OLV
IHD
ILD
OL
Quiet Output Minimum Dynamic V
50
50
50
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
Note 3: Input t
t
3 ns
r
f
3
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AC Electrical Characteristics
V
T
25 C
Typ
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
Min
60
Max
Min
Max
f
Maximum Clock
2.7
115
60
50
40
C
C
C
C
C
C
C
C
C
C
C
C
C
C
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
MAX
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Frequency
45
MHz
3.3 0.3
2.7
100
60
160
95
85
55
t
t
Propagation Delay Time
8.5
11.0
6.7
9.2
7.6
10.1
5.9
8.4
11.5
9.6
16.3
19.8
10.6
14.1
14.5
18.0
9.3
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
8.0
5.5
6.5
4.5
2.0
2.0
19.5
23.0
12.5
16.0
17.5
21.0
11.0
14.5
22.0
15.0
PLH
PHL
CP to O
n
ns
ns
3.3 0.3
2.7
t
t
3-STATE Output
Enable Time
15 pF, R
50 pF, R
15 pF, R
50 pF, R
50 pF, R
50 pF, R
1 k
1 k
1 k
1 k
1 k
1 k
PZL
PZH
L
L
L
L
L
L
3.3 0.3
12.8
18.5
13.2
t
t
t
3-STATE Output
Disable Time
CP Pulse
2.7
3.3 0.3
2.7
PLZ
PHZ
W
ns
ns
ns
ns
ns
7.5
5.0
6.5
4.5
2.0
2.0
Width
3.3 0.3
2.7
t
t
Setup Time
S
H
D
to CP
3.3 0.3
2.7
n
Hold Time
to CP
D
3.3 0.3
2.7
n
t
t
Output to Output
Skew (Note 4)
1.5
1.5
1.5
1.5
C
50 pF
OSLH
OSHL
L
3.3
Note 4: Parameter guaranteed by design. t
|t
t
|, t
|t
t
|
PHLn
OSLH
PLHm
PLHn OSHL
PHLm
Capacitance
T
25 C
Typ
T
40 C to 85 C
A
A
Symbol
Parameter
Units
Min
Max
10
Min
Max
C
C
C
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance (Note 5)
4
6
10
pF
pF
pF
IN
OUT
PD
32
Note 5: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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